diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2012-04-11 12:05:50 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2012-04-11 12:05:50 +0900 |
| commit | 4d6ddb08acc48368c5b7ac431f9d00db7227d2ed (patch) | |
| tree | 5030162ef3c2f9954e43baf02cff7f8794a8ba74 /include | |
| parent | a9e1e53bcfb29b3b503a5e75ce498d9a64f32c1e (diff) | |
sh: clkfwk: Support variable size accesses for MSTP clocks.
The bulk of the MSTP users require 32-bit access, but this isn't the case
for some of the SH-2A parts, so add in some basic infrastructure to let
the CPU define its required access size in preparation.
Requested-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/sh_clk.h | 34 |
1 files changed, 31 insertions, 3 deletions
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h index 0a9d8f2ac519..c513b73cd7cb 100644 --- a/include/linux/sh_clk.h +++ b/include/linux/sh_clk.h @@ -59,7 +59,15 @@ struct clk { unsigned int nr_freqs; }; -#define CLK_ENABLE_ON_INIT (1 << 0) +#define CLK_ENABLE_ON_INIT BIT(0) + +#define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */ +#define CLK_ENABLE_REG_16BIT BIT(2) +#define CLK_ENABLE_REG_8BIT BIT(3) + +#define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \ + CLK_ENABLE_REG_16BIT | \ + CLK_ENABLE_REG_8BIT) /* drivers/sh/clk.c */ unsigned long followparent_recalc(struct clk *); @@ -102,7 +110,7 @@ long clk_round_parent(struct clk *clk, unsigned long target, unsigned long *best_freq, unsigned long *parent_freq, unsigned int div_min, unsigned int div_max); -#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \ +#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \ { \ .parent = _parent, \ .enable_reg = (void __iomem *)_enable_reg, \ @@ -110,7 +118,27 @@ long clk_round_parent(struct clk *clk, unsigned long target, .flags = _flags, \ } -int sh_clk_mstp32_register(struct clk *clks, int nr); +#define SH_CLK_MSTP32(_p, _r, _b, _f) \ + SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT) + +#define SH_CLK_MSTP16(_p, _r, _b, _f) \ + SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT) + +#define SH_CLK_MSTP8(_p, _r, _b, _f) \ + SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT) + +int sh_clk_mstp_register(struct clk *clks, int nr); + +/* + * MSTP registration never really cared about access size, despite the + * original enable/disable pairs assuming a 32-bit access. Clocks are + * responsible for defining their access sizes either directly or via the + * clock definition wrappers. + */ +static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr) +{ + return sh_clk_mstp_register(clks, nr); +} #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ { \ |