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authorJoakim Zhang <qiangqing.zhang@nxp.com>2020-02-25 20:56:43 +0800
committerWill Deacon <will@kernel.org>2020-03-02 12:07:19 +0000
commit049d919168458ac54e7fad27cd156a958b042d2f (patch)
tree7a1fa34cf4825d70c3bbdef0c9b9d6760f0abe75 /drivers/perf/arm-ccn.c
parentdcde237319e626d1ec3c9d8b7613032f0fd4663a (diff)
drivers/perf: fsl_imx8_ddr: Correct the CLEAR bit definition
When disabling a counter from ddr_perf_event_stop(), the counter value is reset to 0 at the same time. Preserve the counter value by performing a read-modify-write of the PMU register and clearing only the enable bit. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/perf/arm-ccn.c')
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