diff options
| author | Hariprasad Kelam <hkelam@marvell.com> | 2022-12-05 12:35:21 +0530 |
|---|---|---|
| committer | Paolo Abeni <pabeni@redhat.com> | 2022-12-07 12:24:29 +0100 |
| commit | 84ad3642115dfc2f17b6bd98e0470f799b8411e3 (patch) | |
| tree | 3fb8c803998d50a64e8ef0fbd457af9e1c360561 /drivers/net/ethernet/marvell/octeontx2/af/rpm.h | |
| parent | b441c4ac5ea37251d6acabe679215a828025004b (diff) | |
octeontx2-af: Add FEC stats for RPM/RPM_USX block
CN10K silicon MAC block RPM and CN10KB silicon MAC block RPM_USX
both support BASER and RSFEC modes.
Also MAC (CGX) on OcteonTx2 silicon variants and MAC (RPM) on
OcteonTx3 CN10K are different and FEC stats need to be read
differently. CN10KB MAC block (RPM_USX) fec csr offsets are same
as CN10K MAC block (RPM) mac_ops points to same fn(). Upper layer
interface between RVU AF and PF netdev is kept same. Based on
silicon variant appropriate fn() pointer is called to read FEC stats
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/af/rpm.h')
| -rw-r--r-- | drivers/net/ethernet/marvell/octeontx2/af/rpm.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h index fc20a35bd8f9..22147b4c2137 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h @@ -25,7 +25,6 @@ #define RPMX_CMRX_SW_INT_ENA_W1S 0x198 #define RPMX_CMRX_LINK_CFG 0x1070 #define RPMX_MTI_PCS100X_CONTROL1 0x20000 -#define RPMX_MTI_LPCSX_CONTROL1 0x30000 #define RPMX_MTI_PCS_LBK BIT_ULL(14) #define RPMX_MTI_LPCSX_CONTROL(id) (0x30000 | ((id) * 0x100)) @@ -81,6 +80,18 @@ #define RPMX_TS_BINARY_MODE BIT_ULL(11) #define RPMX_CONST1 0x2008 +/* FEC stats */ +#define RPMX_MTI_STAT_STATN_CONTROL 0x10018 +#define RPMX_MTI_STAT_DATA_HI_CDC 0x10038 +#define RPMX_RSFEC_RX_CAPTURE BIT_ULL(27) +#define RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_2 0x40050 +#define RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_3 0x40058 +#define RPMX_MTI_FCFECX_VL0_CCW_LO 0x38618 +#define RPMX_MTI_FCFECX_VL0_NCCW_LO 0x38620 +#define RPMX_MTI_FCFECX_VL1_CCW_LO 0x38628 +#define RPMX_MTI_FCFECX_VL1_NCCW_LO 0x38630 +#define RPMX_MTI_FCFECX_CW_HI 0x38638 + /* CN10KB CSR Declaration */ #define RPM2_CMRX_SW_INT 0x1b0 #define RPM2_CMRX_SW_INT_ENA_W1S 0x1b8 @@ -119,4 +130,5 @@ int rpm_lmac_get_pfc_frm_cfg(void *rpmd, int lmac_id, u8 *tx_pause, u8 *rx_pause); int rpm2_get_nr_lmacs(void *rpmd); bool is_dev_rpm2(void *rpmd); +int rpm_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp); #endif /* RPM_H */ |