Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6

Conflicts:
	drivers/net/smsc911x.c

5 files changed, 36 insertions, 36 deletions

diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index b7ff87b35fbb..e0fca701d2f3 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -1220,7 +1220,7 @@ struct bnx2x {
 	struct bnx2x_dcbx_port_params		dcbx_port_params;
 	int					dcb_version;
 
-	/* DCBX Negotation results */
+	/* DCBX Negotiation results */
 	struct dcbx_features			dcbx_local_feat;
 	u32					dcbx_error;
 	u32					pending_max;
diff --git a/drivers/net/bnx2x/bnx2x_hsi.h b/drivers/net/bnx2x/bnx2x_hsi.h
index d9d0184b8c22..2b5940af5d1b 100644
--- a/drivers/net/bnx2x/bnx2x_hsi.h
+++ b/drivers/net/bnx2x/bnx2x_hsi.h
@@ -3019,7 +3019,7 @@ struct tstorm_eth_mac_filter_config {
 
 
 /*
- * common flag to indicate existance of TPA.
+ * common flag to indicate existence of TPA.
  */
 struct tstorm_eth_tpa_exist {
 #if defined(__BIG_ENDIAN)
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index f2f367d4e74d..974ef2be36a5 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -2823,7 +2823,7 @@ static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
 				     struct link_params *params)
 {
 	u16 cnt, ctrl;
-	/* Wait for soft reset to get cleared upto 1 sec */
+	/* Wait for soft reset to get cleared up to 1 sec */
 	for (cnt = 0; cnt < 1000; cnt++) {
 		bnx2x_cl45_read(bp, phy,
 				MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
@@ -4141,7 +4141,7 @@ static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
 			val = (1<<5);
 			/*
 			 * Note that 2.5G works only when used with 1G
-			 * advertisment
+			 * advertisement
 			 */
 		} else
 			val = (1<<5);
@@ -4151,7 +4151,7 @@ static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
 			PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
 			val |= (1<<7);
 
-		/* Note that 2.5G works only when used with 1G advertisment */
+		/* Note that 2.5G works only when used with 1G advertisement */
 		if (phy->speed_cap_mask &
 			(PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
 			 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
@@ -5232,14 +5232,14 @@ static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
 		bnx2x_cl45_write(bp, phy,
 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
 	} else {
-		/* Force 1Gbps using autoneg with 1G advertisment */
+		/* Force 1Gbps using autoneg with 1G advertisement */
 
 		/* Allow CL37 through CL73 */
 		DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
 		bnx2x_cl45_write(bp, phy,
 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
 
-		/* Enable Full-Duplex advertisment on CL37 */
+		/* Enable Full-Duplex advertisement on CL37 */
 		bnx2x_cl45_write(bp, phy,
 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
 		/* Enable CL37 AN */
@@ -6269,7 +6269,7 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
 
 	switch (actual_phy_selection) {
 	case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
-		/* Do nothing. Essentialy this is like the priority copper */
+		/* Do nothing. Essentially this is like the priority copper */
 		break;
 	case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
 		val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
@@ -7765,7 +7765,7 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
 	REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
 
 	msleep(10);
-	/* The PHY reset is controled by GPIO 1
+	/* The PHY reset is controlled by GPIO 1
 	 * Hold it as vars low
 	 */
 	 /* clear link led */
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index f3cf88918a9e..a6915aafa695 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -3702,7 +3702,7 @@ static void bnx2x_eq_int(struct bnx2x *bp)
 	if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
 		hw_cons++;
 
-	/* This function may never run in parralel with itself for a
+	/* This function may never run in parallel with itself for a
 	 * specific bp, thus there is no need in "paired" read memory
 	 * barrier here.
 	 */
@@ -5089,7 +5089,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
 		/* Step 1: set zeroes to all ilt page entries with valid bit on
 		 * Step 2: set the timers first/last ilt entry to point
 		 * to the entire range to prevent ILT range error for 3rd/4th
-		 * vnic	(this code assumes existance of the vnic)
+		 * vnic	(this code assumes existence of the vnic)
 		 *
 		 * both steps performed by call to bnx2x_ilt_client_init_op()
 		 * with dummy TM client
@@ -8685,7 +8685,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
 				E1H_FUNC_MAX * sizeof(struct drv_func_mb);
 		/*
 		 * get mf configuration:
-		 * 1. existance of MF configuration
+		 * 1. existence of MF configuration
 		 * 2. MAC address must be legal (check only upper bytes)
 		 *    for  Switch-Independent mode;
 		 *    OVLAN must be legal for Switch-Dependent mode
@@ -8727,7 +8727,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
 			default:
 				/* Unknown configuration: reset mf_config */
 				bp->mf_config[vn] = 0;
-				DP(NETIF_MSG_PROBE, "Unkown MF mode 0x%x\n",
+				DP(NETIF_MSG_PROBE, "Unknown MF mode 0x%x\n",
 				   val);
 			}
 		}
@@ -9777,7 +9777,7 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
 
 #endif
 
-	/* Configure interupt mode: try to enable MSI-X/MSI if
+	/* Configure interrupt mode: try to enable MSI-X/MSI if
 	 * needed, set bp->num_queues appropriately.
 	 */
 	bnx2x_set_int_mode(bp);
diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h
index 1c89f19a4425..1509a2318af9 100644
--- a/drivers/net/bnx2x/bnx2x_reg.h
+++ b/drivers/net/bnx2x/bnx2x_reg.h
@@ -175,9 +175,9 @@
    the initial credit value; read returns the current value of the credit
    counter. Must be initialized to 1 at start-up. */
 #define CCM_REG_CFC_INIT_CRD					 0xd0204
-/* [RW 2] Auxillary counter flag Q number 1. */
+/* [RW 2] Auxiliary counter flag Q number 1. */
 #define CCM_REG_CNT_AUX1_Q					 0xd00c8
-/* [RW 2] Auxillary counter flag Q number 2. */
+/* [RW 2] Auxiliary counter flag Q number 2. */
 #define CCM_REG_CNT_AUX2_Q					 0xd00cc
 /* [RW 28] The CM header value for QM request (primary). */
 #define CCM_REG_CQM_CCM_HDR_P					 0xd008c
@@ -457,13 +457,13 @@
 #define CSDM_REG_AGG_INT_MODE_9 				 0xc21dc
 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
 #define CSDM_REG_CFC_RSP_START_ADDR				 0xc2008
-/* [RW 16] The maximum value of the competion counter #0 */
+/* [RW 16] The maximum value of the completion counter #0 */
 #define CSDM_REG_CMP_COUNTER_MAX0				 0xc201c
-/* [RW 16] The maximum value of the competion counter #1 */
+/* [RW 16] The maximum value of the completion counter #1 */
 #define CSDM_REG_CMP_COUNTER_MAX1				 0xc2020
-/* [RW 16] The maximum value of the competion counter #2 */
+/* [RW 16] The maximum value of the completion counter #2 */
 #define CSDM_REG_CMP_COUNTER_MAX2				 0xc2024
-/* [RW 16] The maximum value of the competion counter #3 */
+/* [RW 16] The maximum value of the completion counter #3 */
 #define CSDM_REG_CMP_COUNTER_MAX3				 0xc2028
 /* [RW 13] The start address in the internal RAM for the completion
    counters. */
@@ -851,7 +851,7 @@
 #define IGU_REG_ATTN_MSG_ADDR_L				 0x130120
 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
  * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
- * write done didnt receive. */
+ * write done didn't receive. */
 #define IGU_REG_ATTN_WRITE_DONE_PENDING			 0x130030
 #define IGU_REG_BLOCK_CONFIGURATION				 0x130000
 #define IGU_REG_COMMAND_REG_32LSB_DATA				 0x130124
@@ -862,7 +862,7 @@
 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP			 0x130200
 /* [R 5] Debug: ctrl_fsm */
 #define IGU_REG_CTRL_FSM					 0x130064
-/* [R 1] data availble for error memory. If this bit is clear do not red
+/* [R 1] data available for error memory. If this bit is clear do not red
  * from error_handling_memory. */
 #define IGU_REG_ERROR_HANDLING_DATA_VALID			 0x130130
 /* [RW 11] Parity mask register #0 read/write */
@@ -3015,7 +3015,7 @@
    block. Should be used for close the gates. */
 #define PXP_REG_HST_DISCARD_DOORBELLS				 0x1030a4
 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
-   should update accoring to 'hst_discard_doorbells' register when the state
+   should update according to 'hst_discard_doorbells' register when the state
    machine is idle */
 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS			 0x1030a0
 /* [RW 1] When 1; new internal writes arriving to the block are discarded.
@@ -3023,7 +3023,7 @@
 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES			 0x1030a8
 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
    means this PSWHST is discarding inputs from this client. Each bit should
-   update accoring to 'hst_discard_internal_writes' register when the state
+   update according to 'hst_discard_internal_writes' register when the state
    machine is idle. */
 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS		 0x10309c
 /* [WB 160] Used for initialization of the inbound interrupts memory */
@@ -3822,13 +3822,13 @@
 #define TSDM_REG_AGG_INT_T_1					 0x420bc
 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
 #define TSDM_REG_CFC_RSP_START_ADDR				 0x42008
-/* [RW 16] The maximum value of the competion counter #0 */
+/* [RW 16] The maximum value of the completion counter #0 */
 #define TSDM_REG_CMP_COUNTER_MAX0				 0x4201c
-/* [RW 16] The maximum value of the competion counter #1 */
+/* [RW 16] The maximum value of the completion counter #1 */
 #define TSDM_REG_CMP_COUNTER_MAX1				 0x42020
-/* [RW 16] The maximum value of the competion counter #2 */
+/* [RW 16] The maximum value of the completion counter #2 */
 #define TSDM_REG_CMP_COUNTER_MAX2				 0x42024
-/* [RW 16] The maximum value of the competion counter #3 */
+/* [RW 16] The maximum value of the completion counter #3 */
 #define TSDM_REG_CMP_COUNTER_MAX3				 0x42028
 /* [RW 13] The start address in the internal RAM for the completion
    counters. */
@@ -4284,13 +4284,13 @@
 #define USDM_REG_AGG_INT_T_6					 0xc40d0
 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
 #define USDM_REG_CFC_RSP_START_ADDR				 0xc4008
-/* [RW 16] The maximum value of the competion counter #0 */
+/* [RW 16] The maximum value of the completion counter #0 */
 #define USDM_REG_CMP_COUNTER_MAX0				 0xc401c
-/* [RW 16] The maximum value of the competion counter #1 */
+/* [RW 16] The maximum value of the completion counter #1 */
 #define USDM_REG_CMP_COUNTER_MAX1				 0xc4020
-/* [RW 16] The maximum value of the competion counter #2 */
+/* [RW 16] The maximum value of the completion counter #2 */
 #define USDM_REG_CMP_COUNTER_MAX2				 0xc4024
-/* [RW 16] The maximum value of the competion counter #3 */
+/* [RW 16] The maximum value of the completion counter #3 */
 #define USDM_REG_CMP_COUNTER_MAX3				 0xc4028
 /* [RW 13] The start address in the internal RAM for the completion
    counters. */
@@ -4798,13 +4798,13 @@
 #define XSDM_REG_AGG_INT_MODE_1 				 0x1661bc
 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
 #define XSDM_REG_CFC_RSP_START_ADDR				 0x166008
-/* [RW 16] The maximum value of the competion counter #0 */
+/* [RW 16] The maximum value of the completion counter #0 */
 #define XSDM_REG_CMP_COUNTER_MAX0				 0x16601c
-/* [RW 16] The maximum value of the competion counter #1 */
+/* [RW 16] The maximum value of the completion counter #1 */
 #define XSDM_REG_CMP_COUNTER_MAX1				 0x166020
-/* [RW 16] The maximum value of the competion counter #2 */
+/* [RW 16] The maximum value of the completion counter #2 */
 #define XSDM_REG_CMP_COUNTER_MAX2				 0x166024
-/* [RW 16] The maximum value of the competion counter #3 */
+/* [RW 16] The maximum value of the completion counter #3 */
 #define XSDM_REG_CMP_COUNTER_MAX3				 0x166028
 /* [RW 13] The start address in the internal RAM for the completion
    counters. */