diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2016-08-09 07:50:44 +0100 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2016-08-17 18:31:20 +0100 |
| commit | 059e232089e45b0befc9933d31209c225e08b426 (patch) | |
| tree | d872c69b79fb8e2845a60a167af15ef66d466ad4 /drivers/irqchip/irq-gic.c | |
| parent | 1e12c4a9393b75a744aada2c8115434572698bc3 (diff) | |
irqchip/gic: Allow self-SGIs for SMP on UP configurations
On systems where a single CPU is present, the GIC may not support
having SGIs delivered to a target list. In that case, we use the
self-SGI mechanism to allow the interrupt to be delivered locally.
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/irqchip/irq-gic.c')
| -rw-r--r-- | drivers/irqchip/irq-gic.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index c2cab572c511..390fac59c6bc 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -769,6 +769,13 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) int cpu; unsigned long flags, map = 0; + if (unlikely(nr_cpu_ids == 1)) { + /* Only one CPU? let's do a self-IPI... */ + writel_relaxed(2 << 24 | irq, + gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); + return; + } + raw_spin_lock_irqsave(&irq_controller_lock, flags); /* Convert our logical CPU mask into a physical one. */ |