diff options
| author | Yicong Yang <yangyicong@hisilicon.com> | 2023-10-10 16:47:27 +0800 |
|---|---|---|
| committer | Suzuki K Poulose <suzuki.poulose@arm.com> | 2023-11-16 11:36:27 +0000 |
| commit | 46f69b197b6cd06c709581f7ad271bc02dbedb7a (patch) | |
| tree | c386dae7aa05b16261b71881ca3cf70e446e5f62 /drivers/hwtracing | |
| parent | 9d4408feff89f8d86b8f34339b08ceb5f8400190 (diff) | |
hwtracing: hisi_ptt: Disable interrupt after trace end
On trace end we disable the hardware but leave the interrupt
unmasked. Mask the interrupt to make the process reverse to
the start. No actual issue since hardware should send no
interrupt after disabled.
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20231010084731.30450-2-yangyicong@huawei.com
Diffstat (limited to 'drivers/hwtracing')
| -rw-r--r-- | drivers/hwtracing/ptt/hisi_ptt.c | 4 | ||||
| -rw-r--r-- | drivers/hwtracing/ptt/hisi_ptt.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/hwtracing/ptt/hisi_ptt.c b/drivers/hwtracing/ptt/hisi_ptt.c index a991ecb7515a..01a1eb0d4988 100644 --- a/drivers/hwtracing/ptt/hisi_ptt.c +++ b/drivers/hwtracing/ptt/hisi_ptt.c @@ -183,6 +183,10 @@ static void hisi_ptt_wait_dma_reset_done(struct hisi_ptt *hisi_ptt) static void hisi_ptt_trace_end(struct hisi_ptt *hisi_ptt) { writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); + + /* Mask the interrupt on the end */ + writel(HISI_PTT_TRACE_INT_MASK_ALL, hisi_ptt->iobase + HISI_PTT_TRACE_INT_MASK); + hisi_ptt->trace_ctrl.started = false; } diff --git a/drivers/hwtracing/ptt/hisi_ptt.h b/drivers/hwtracing/ptt/hisi_ptt.h index e17f045d7e72..46030aa88081 100644 --- a/drivers/hwtracing/ptt/hisi_ptt.h +++ b/drivers/hwtracing/ptt/hisi_ptt.h @@ -47,6 +47,7 @@ #define HISI_PTT_TRACE_INT_STAT 0x0890 #define HISI_PTT_TRACE_INT_STAT_MASK GENMASK(3, 0) #define HISI_PTT_TRACE_INT_MASK 0x0894 +#define HISI_PTT_TRACE_INT_MASK_ALL GENMASK(3, 0) #define HISI_PTT_TUNING_INT_STAT 0x0898 #define HISI_PTT_TUNING_INT_STAT_MASK BIT(0) #define HISI_PTT_TRACE_WR_STS 0x08a0 |