diff options
| author | Thor Thayer <tthayer@opensource.altera.com> | 2016-07-28 10:03:57 +0200 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2016-08-08 05:59:36 +0200 |
| commit | e8263793b7248ec78316d5915152c105e1034a28 (patch) | |
| tree | e4595f4bab2b16caedd2df511ea851636e015fad /drivers/edac | |
| parent | c6882fb2e83525e97663df1d2d96f29d034189ab (diff) | |
EDAC, altera: Add Arria10 DMA support
Add Altera Arria10 DMA FIFO memory support.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1468512408-5156-7-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'drivers/edac')
| -rw-r--r-- | drivers/edac/Kconfig | 7 | ||||
| -rw-r--r-- | drivers/edac/altera_edac.c | 33 |
2 files changed, 39 insertions, 1 deletions
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 47378b30c8c3..d1fd57ab742b 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -405,6 +405,13 @@ config EDAC_ALTERA_NAND Support for error detection and correction on the Altera NAND FIFO Memory for Altera SoCs. +config EDAC_ALTERA_DMA + bool "Altera DMA FIFO ECC" + depends on EDAC_ALTERA=y && PL330_DMA=y + help + Support for error detection and correction on the + Altera DMA FIFO Memory for Altera SoCs. + config EDAC_SYNOPSYS tristate "Synopsys DDR Memory Controller" depends on EDAC_MM_EDAC && ARCH_ZYNQ diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c index fe6374236bd9..83edc6861eb1 100644 --- a/drivers/edac/altera_edac.c +++ b/drivers/edac/altera_edac.c @@ -1312,6 +1312,33 @@ early_initcall(socfpga_init_nand_ecc); #endif /* CONFIG_EDAC_ALTERA_NAND */ +/********************** DMA Device Functions **********************/ + +#ifdef CONFIG_EDAC_ALTERA_DMA + +static const struct edac_device_prv_data a10_dmaecc_data = { + .setup = altr_check_ecc_deps, + .ce_clear_mask = ALTR_A10_ECC_SERRPENA, + .ue_clear_mask = ALTR_A10_ECC_DERRPENA, + .dbgfs_name = "altr_trigger", + .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, + .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, + .ce_set_mask = ALTR_A10_ECC_TSERRA, + .ue_set_mask = ALTR_A10_ECC_TDERRA, + .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, + .ecc_irq_handler = altr_edac_a10_ecc_irq, + .inject_fops = &altr_edac_a10_device_inject_fops, +}; + +static int __init socfpga_init_dma_ecc(void) +{ + return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc"); +} + +early_initcall(socfpga_init_dma_ecc); + +#endif /* CONFIG_EDAC_ALTERA_DMA */ + /********************* Arria10 EDAC Device Functions *************************/ static const struct of_device_id altr_edac_a10_device_of_match[] = { #ifdef CONFIG_EDAC_ALTERA_L2C @@ -1328,6 +1355,9 @@ static const struct of_device_id altr_edac_a10_device_of_match[] = { #ifdef CONFIG_EDAC_ALTERA_NAND { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data }, #endif +#ifdef CONFIG_EDAC_ALTERA_DMA + { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data }, +#endif {}, }; MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match); @@ -1618,7 +1648,8 @@ static int altr_edac_a10_probe(struct platform_device *pdev) if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") || of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") || of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") || - of_device_is_compatible(child, "altr,socfpga-nand-ecc")) + of_device_is_compatible(child, "altr,socfpga-nand-ecc") || + of_device_is_compatible(child, "altr,socfpga-dma-ecc")) altr_edac_a10_device_add(edac, child); |