diff options
| author | Colin Ian King <colin.king@canonical.com> | 2019-10-23 12:28:09 +0100 |
|---|---|---|
| committer | Maxime Ripard <mripard@kernel.org> | 2019-10-29 08:42:52 +0100 |
| commit | cdfc2e2086bf9c465f44e2db25561373b084a113 (patch) | |
| tree | 5541768f3b3232aa5f38ba3bd77e5e4194e45d34 /drivers/clk/sunxi-ng | |
| parent | afdc74ed2d57e86c10b1d6831339770a802bab9a (diff) | |
clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18
The zero'ing of bits 16 and 18 is incorrect. Currently the code
is masking with the bitwise-and of BIT(16) & BIT(18) which is
0, so the updated value for val is always zero. Fix this by bitwise
and-ing value with the correct mask that will zero bits 16 and 18.
Addresses-Coverity: (" Suspicious &= or |= constant expression")
Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Diffstat (limited to 'drivers/clk/sunxi-ng')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c index dcac1391767f..ef29582676f6 100644 --- a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c @@ -1224,7 +1224,7 @@ static int sun9i_a80_ccu_probe(struct platform_device *pdev) /* Enforce d1 = 0, d2 = 0 for Audio PLL */ val = readl(reg + SUN9I_A80_PLL_AUDIO_REG); - val &= (BIT(16) & BIT(18)); + val &= ~(BIT(16) | BIT(18)); writel(val, reg + SUN9I_A80_PLL_AUDIO_REG); /* Enforce P = 1 for both CPU cluster PLLs */ |