diff options
| author | Tero Kristo <t-kristo@ti.com> | 2015-11-30 16:43:25 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-11-30 11:34:17 -0800 |
| commit | 07ff73a932b725b2a4675bd0cc1a86b4933e433e (patch) | |
| tree | da9e26ac88590535060e130e8ce51c4369a7c2a8 /drivers/clk/socfpga/clk-pll-a10.c | |
| parent | cf81a1cf711d71daafe8f1b8eca96b54c3f5c8ed (diff) | |
clk: ti: omap5+: dpll: implement errata i810
Errata i810 states that DPLL controller can get stuck while transitioning
to a power saving state, while its M/N ratio is being re-programmed.
As a workaround, before re-programming the M/N ratio, SW has to ensure
the DPLL cannot start an idle state transition. SW can disable DPLL
idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request
active by setting a dependent clock domain in SW_WKUP.
This errata impacts OMAP5 and DRA7 chips, so enable the errata for these.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/socfpga/clk-pll-a10.c')
0 files changed, 0 insertions, 0 deletions