diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2017-08-07 13:19:19 +0100 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2017-08-21 11:52:35 +0300 |
| commit | d41a3c2be178783c85e05025265ab58fbb4d4ce1 (patch) | |
| tree | fce8343d1c02f5ab1104ef8bbb89c46d62c0935b /crypto/simd.c | |
| parent | a93c11527528c951b8d8db638162128a09e09ec2 (diff) | |
drm/i915: Clear lost context-switch interrupts across reset
During a global reset, we disable the irq. As we disable the irq, the
hardware may be raising a GT interrupt that we then ignore, leaving it
pending in the GTIIR. After the reset, we then re-enable the irq,
triggering the pending interrupt. However, that interrupt was for the
stale state from before the reset, and the contents of the CSB buffer
are now invalid.
v2: Add a comment to make it clear that the double clear is purely my
paranoia.
Reported-by: "Dong, Chuanxiao" <chuanxiao.dong@intel.com>
Fixes: 821ed7df6e2a ("drm/i915: Update reset path to fix incomplete requests")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Dong, Chuanxiao" <chuanxiao.dong@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Winiarski <michal.winiarski@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170807121919.30165-1-chris@chris-wilson.co.uk
Link: https://patchwork.freedesktop.org/patch/msgid/20170818090509.5363-1-chris@chris-wilson.co.uk
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
(cherry picked from commit 64f09f00caf0a7cb40a8c0b85789bacba0f51d9e)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'crypto/simd.c')
0 files changed, 0 insertions, 0 deletions