diff options
| author | Huazhong Tan <tanhuazhong@huawei.com> | 2018-01-18 20:31:37 +0800 |
|---|---|---|
| committer | Wei Xu <xuwei5@hisilicon.com> | 2018-03-02 15:29:51 +0000 |
| commit | 45cc842d5b75ba8f9a958f2dd12b95c6dd0452bd (patch) | |
| tree | c394e76afdb3b0fd33aef88f6bc0e063ab53f3c2 /arch | |
| parent | 7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff) | |
arm64: dts: hisi: add hns-dsaf cpld control for the hip07 SoC
Add cpld-syscon node to support the cpld control for hns-dsaf
on the hip07 SoC.
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hip07.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 2c01a21c3665..4bd6416122d5 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1127,6 +1127,12 @@ reg = <0x0 0xc0000000 0x0 0x10000>; }; + dsa_cpld: dsa_cpld@78000010 { + compatible = "syscon"; + reg = <0x0 0x78000010 0x0 0x100>; + reg-io-width = <2>; + }; + pcie_subctl: pcie_subctl@a0000000 { compatible = "hisilicon,pcie-sas-subctrl", "syscon"; reg = <0x0 0xa0000000 0x0 0x10000>; @@ -1258,6 +1264,7 @@ port@0 { reg = <0>; serdes-syscon = <&serdes_ctrl>; + cpld-syscon = <&dsa_cpld 0x0>; port-rst-offset = <0>; port-mode-offset = <0>; mc-mac-mask = [ff f0 00 00 00 00]; @@ -1267,6 +1274,7 @@ port@1 { reg = <1>; serdes-syscon= <&serdes_ctrl>; + cpld-syscon = <&dsa_cpld 0x4>; port-rst-offset = <1>; port-mode-offset = <1>; mc-mac-mask = [ff f0 00 00 00 00]; |