diff options
| author | Len Brown <len.brown@intel.com> | 2017-02-10 00:27:20 -0500 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2017-03-01 00:14:02 -0500 |
| commit | 0539ba118fe241b0d03202fda0cd19cb758b7fbd (patch) | |
| tree | f4c62d97e838497c699a33ef0f94aaa4ecccae96 /arch | |
| parent | 419c9e986ea453d07140bffb9708d730b6317e8e (diff) | |
tools/power turbostat: Baytrail c-state support
The Baytrail SOC, with its Silvermont core, has some unique properties:
1. a hardware CC1 residency counter
2. a module-c6 residency counter
3. a package-c6 counter at traditional package-c7 counter address.
The SOC does not support c3, pc3, c7 or pc7 counters.
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 12ecc6c1e7f8..079db99f6560 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -147,6 +147,7 @@ /* C-state Residency Counters */ #define MSR_PKG_C3_RESIDENCY 0x000003f8 #define MSR_PKG_C6_RESIDENCY 0x000003f9 +#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa #define MSR_PKG_C7_RESIDENCY 0x000003fa #define MSR_CORE_C3_RESIDENCY 0x000003fc #define MSR_CORE_C6_RESIDENCY 0x000003fd @@ -203,6 +204,7 @@ #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B #define MSR_CORE_C1_RES 0x00000660 +#define MSR_MODULE_C6_RES_MS 0x00000664 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 |