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authorNiklas Schnelle <schnelle@linux.ibm.com>2022-01-05 16:10:54 +0100
committerHeiko Carstens <hca@linux.ibm.com>2022-01-07 11:48:17 +0100
commit7b2932162f66ab33a00a7cdb6d3b2db6dfdbf634 (patch)
tree59b12e6f751bb650c5e05559f7eabe61a9dbaa69 /arch/s390/pci
parentc4538d0f19010f22854360d99551eb293228b946 (diff)
s390/pci: simplify __pciwb_mio() inline asm
The PCI Write Barrier instruction ignores the registers encoded in it. There is thus no need to explicitly set the register to zero or to associate it with a variable at all. In the resulting binary this removes an unnecessary lghi and it makes the code simpler. Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
Diffstat (limited to 'arch/s390/pci')
-rw-r--r--arch/s390/pci/pci_insn.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/arch/s390/pci/pci_insn.c b/arch/s390/pci/pci_insn.c
index 28d863aaafea..4dd58b196cea 100644
--- a/arch/s390/pci/pci_insn.c
+++ b/arch/s390/pci/pci_insn.c
@@ -365,10 +365,7 @@ EXPORT_SYMBOL_GPL(zpci_write_block);
static inline void __pciwb_mio(void)
{
- unsigned long unused = 0;
-
- asm volatile (".insn rre,0xb9d50000,%[op],%[op]\n"
- : [op] "+d" (unused));
+ asm volatile (".insn rre,0xb9d50000,0,0\n");
}
void zpci_barrier(void)