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authorCyrill Gorcunov <gorcunov@openvz.org>2010-08-05 19:09:17 +0400
committerIngo Molnar <mingo@elte.hu>2010-08-08 22:53:50 +0200
commit1c250d709fdc8aa5bf42d90be99428a01a256a55 (patch)
treee71c6d304b12017a034a6ad26468abe296ea5a6c /arch/powerpc/configs/chrp32_defconfig
parentef8f34aabf2450a9fb36b2c87fe0ea0b86a38195 (diff)
perf, x86: P4 PMU -- update nmi irq statistics and unmask lvt entry properly
In case if last active performance counter is not overflowed at moment of NMI being triggered by another counter, the irq statistics may miss an update stage. As a more serious consequence -- apic quirk may not be triggered so apic lvt entry stay masked. Tested-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Stephane Eranian <eranian@google.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Frederic Weisbecker <fweisbec@gmail.com> LKML-Reference: <20100805150917.GA6311@lenovo> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/powerpc/configs/chrp32_defconfig')
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