diff options
| author | Peter Horton <pdh@colonel-panic.org> | 2006-01-29 21:33:48 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-02-07 13:30:24 +0000 |
| commit | 52378445da0253d5031590e5e9186ee448dc0b4a (patch) | |
| tree | bb4028a9ff2543e29c5f31863a441f1f9d7608f5 /arch/mips/pci | |
| parent | c315a2b5fed42aea4dda98b5ced35d1d1a3a8349 (diff) | |
[MIPS] Fix Cobalt PCI cache line sizes
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
| -rw-r--r-- | arch/mips/pci/fixup-cobalt.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index b664df150a3e..75a01e764898 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -52,7 +52,7 @@ static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); if (lt < 64) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); - pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, @@ -69,7 +69,7 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) * host bridge. */ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); - pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); /* * The code described by the comment below has been removed |