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authorSteven J. Hill <sjhill@mips.com>2012-11-14 23:34:17 -0600
committerRalf Baechle <ralf@linux-mips.org>2012-12-13 18:15:24 +0100
commitd7ea335c05ba7c013615d1e0d5a71459eb4195e8 (patch)
tree333f0cb8edd150b6c967bffacad07c03fea393da /arch/mips/include
parentdcb96a4e36425d563cefd44a20d3386e02a547f3 (diff)
MIPS: Remove usage of CSRC_R4K_LIB config option.
Manuel Lauss <manuel.lauss@gmail.com> writes: I introduced it as a fallback because early revisions of Alchemy hardware we shipped had a non-functional 32kHz timer and had to rely on the r4k timer instead. Previously the r4k timer was initialized regardless, but it's useless with the "wait" instruction. So long story short: I need either the on-chip 32kHz timer OR the r4k timer if the 32kHz one is unusable, but not both, and r4k timer is useless when au1k_idle is in use. The current in-kernel Alchemy boards all work with the 32kHz timer, so I'm not against removing R4K_LIB symbols. Signed-off-by: Steven J. Hill <sjhill@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/time.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index bc14447e69b5..6be93a468ec9 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -71,7 +71,7 @@ static inline int mips_clockevent_init(void)
/*
* Initialize the count register as a clocksource
*/
-#ifdef CONFIG_CSRC_R4K_LIB
+#ifdef CONFIG_CSRC_R4K
extern int init_r4k_clocksource(void);
#endif