diff options
author | Eric Miao <eric.miao@marvell.com> | 2009-01-06 17:37:37 +0800 |
---|---|---|
committer | Eric Miao <eric.miao@marvell.com> | 2009-03-09 21:22:37 +0800 |
commit | a58fbcd8ad17ddaa0c7aadbbbd20de4ebc807fa4 (patch) | |
tree | 00b0a13c0dbe7155d5b529f9d36cc423996a3e19 /arch/arm/mach-pxa/gpio.c | |
parent | 7ebc8d56f407184a457dd5fc739cf39e423a25aa (diff) |
[ARM] pxa: move IRQ handling of GPIO 0 and 1 outside of gpio.c
This is part of the work making gpio.c generic enough, the changes
include:
1. move IRQ handling of GPIO 0 and 1 outside (and back into irq.c)
2. pxa_init_gpio() accepts a range for muxed GPIO IRQs, and an IRQ
number for the muxed GPIOs
3. __gpio_is_occupied() and __gpio_is_inverted() are made inline,
and are moved into <mach/gpio.h> instead of generic gpio.c
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Diffstat (limited to 'arch/arm/mach-pxa/gpio.c')
-rw-r--r-- | arch/arm/mach-pxa/gpio.c | 113 |
1 files changed, 25 insertions, 88 deletions
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c index 5fec1e479cb3..198246019028 100644 --- a/arch/arm/mach-pxa/gpio.c +++ b/arch/arm/mach-pxa/gpio.c @@ -45,18 +45,6 @@ struct pxa_gpio_chip { int pxa_last_gpio; -#ifdef CONFIG_CPU_PXA26x -/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, - * as well as their Alternate Function value being '1' for GPIO in GAFRx. - */ -static int __gpio_is_inverted(unsigned gpio) -{ - return cpu_is_pxa25x() && gpio > 85; -} -#else -#define __gpio_is_inverted(gpio) (0) -#endif - /* * Configure pins for GPIO or other functions */ @@ -185,6 +173,20 @@ static struct pxa_gpio_chip pxa_gpio_chip[] = { #endif }; +static void __init pxa_init_gpio_chip(int gpio_nr) +{ + int i, gpio; + + /* add a GPIO chip for each register bank. + * the last PXA25x register only contains 21 GPIOs + */ + for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) { + if (gpio + 32 > gpio_nr) + pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio; + gpiochip_add(&pxa_gpio_chip[i].chip); + } +} + /* * PXA GPIO edge detection for IRQs: * IRQs are generated on Falling-Edge, Rising-Edge, or both. @@ -195,27 +197,6 @@ static unsigned long GPIO_IRQ_rising_edge[4]; static unsigned long GPIO_IRQ_falling_edge[4]; static unsigned long GPIO_IRQ_mask[4]; -/* - * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate - * function of a GPIO, and GPDRx cannot be altered once configured. It - * is attributed as "occupied" here (I know this terminology isn't - * accurate, you are welcome to propose a better one :-) - */ -static int __gpio_is_occupied(unsigned gpio) -{ - if (cpu_is_pxa27x() || cpu_is_pxa25x()) { - int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; - int dir = GPDR(gpio) & GPIO_bit(gpio); - - if (__gpio_is_inverted(gpio)) - return af != 1 || dir == 0; - else - return af != 0 || dir != 0; - } - - return 0; -} - static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) { int gpio, idx; @@ -262,33 +243,6 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) } /* - * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. - */ - -static void pxa_ack_low_gpio(unsigned int irq) -{ - GEDR0 = (1 << (irq - IRQ_GPIO0)); -} - -static void pxa_mask_low_gpio(unsigned int irq) -{ - ICMR &= ~(1 << (irq - PXA_IRQ(0))); -} - -static void pxa_unmask_low_gpio(unsigned int irq) -{ - ICMR |= 1 << (irq - PXA_IRQ(0)); -} - -static struct irq_chip pxa_low_gpio_chip = { - .name = "GPIO-l", - .ack = pxa_ack_low_gpio, - .mask = pxa_mask_low_gpio, - .unmask = pxa_unmask_low_gpio, - .set_type = pxa_gpio_irq_type, -}; - -/* * Demux handler for GPIO>=2 edge detect interrupts */ @@ -352,48 +306,31 @@ static struct irq_chip pxa_muxed_gpio_chip = { .set_type = pxa_gpio_irq_type, }; -void __init pxa_init_gpio(int gpio_nr, set_wake_t fn) +void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) { - int irq, i, gpio; + int irq, i; - pxa_last_gpio = gpio_nr - 1; + pxa_last_gpio = end; /* clear all GPIO edge detects */ - for (i = 0; i < gpio_nr; i += 32) { - GFER(i) = 0; - GRER(i) = 0; - GEDR(i) = GEDR(i); + for (i = start; i <= end; i += 32) { + GFER(i) &= ~GPIO_IRQ_mask[i]; + GRER(i) &= ~GPIO_IRQ_mask[i]; + GEDR(i) = GPIO_IRQ_mask[i]; } - /* GPIO 0 and 1 must have their mask bit always set */ - GPIO_IRQ_mask[0] = 3; - - for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { - set_irq_chip(irq, &pxa_low_gpio_chip); - set_irq_handler(irq, handle_edge_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - - for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) { + for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { set_irq_chip(irq, &pxa_muxed_gpio_chip); set_irq_handler(irq, handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* Install handler for GPIO>=2 edge detect interrupts */ - set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); - - pxa_low_gpio_chip.set_wake = fn; + set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler); pxa_muxed_gpio_chip.set_wake = fn; - /* add a GPIO chip for each register bank. - * the last PXA25x register only contains 21 GPIOs - */ - for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) { - if (gpio + 32 > gpio_nr) - pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio; - gpiochip_add(&pxa_gpio_chip[i].chip); - } + /* Initialize GPIO chips */ + pxa_init_gpio_chip(end + 1); } #ifdef CONFIG_PM |