diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2011-11-06 13:54:56 +0900 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-11-06 13:54:56 +0900 |
commit | 830145796a5c8f1ca3f87ea619063c1d99a57df5 (patch) | |
tree | e72a0ecacfcce228c46d93c946cfd65a44cc1fd3 /arch/arm/mach-exynos/setup-fimc.c | |
parent | e700e41d9abfbf9fee01e979a41b185695132c19 (diff) |
ARM: EXYNOS: Add ARCH_EXYNOS and reorganize arch/arm/mach-exynos
The arch/arm/mach-exynos4 directory (CONFIG_ARCH_EXYNOS4) has
made for plaforms based on EXYNOS4 SoCs. But since upcoming
Samsung's SoCs such as EXYNOS5 (ARM Cortex A15) can reuse most
codes in current mach-exynos4, one mach-exynos directory will
be used for them.
This patch changes to CONFIG_ARCH_EXYNOS (arch/arm/mach-exynos)
but keeps original CONFIG_ARCH_EXYNOS4 in mach-exynos/Kconfig to
avoid changing in driver side.
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/setup-fimc.c')
-rw-r--r-- | arch/arm/mach-exynos/setup-fimc.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c new file mode 100644 index 000000000000..6a45078d9d12 --- /dev/null +++ b/arch/arm/mach-exynos/setup-fimc.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co., Ltd. + * + * Exynos4 camera interface GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <plat/gpio-cfg.h> +#include <plat/camport.h> + +int exynos4_fimc_setup_gpio(enum s5p_camport_id id) +{ + u32 gpio8, gpio5; + u32 sfn; + int ret; + + switch (id) { + case S5P_CAMPORT_A: + gpio8 = EXYNOS4_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */ + gpio5 = EXYNOS4_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */ + sfn = S3C_GPIO_SFN(2); + break; + + case S5P_CAMPORT_B: + gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */ + gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */ + sfn = S3C_GPIO_SFN(3); + break; + + default: + WARN(1, "Wrong camport id: %d\n", id); + return -EINVAL; + } + + ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP); + if (ret) + return ret; + + return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP); +} |