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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2014-02-20 02:22:31 +0300
committerSimon Horman <horms+renesas@verge.net.au>2014-02-25 10:55:43 +0900
commitda4ea9514df42f69ec42a098142aaeac8c101da5 (patch)
tree30491bbec12fe59541505826f53f3f3e257acc08 /arch/arm/boot/dts/r8a7790-lager.dts
parentd8913c6799ed776d096a7f41d83afce815f93819 (diff)
ARM: shmobile: lager: add Ether DT support
Define the Lager board dependent part of the Ether device node. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7790-lager.dts')
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts28
1 files changed, 27 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 26a90106e96c..6e99eb2df076 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -1,7 +1,8 @@
/*
* Device Tree Source for the Lager board
*
- * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013-2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -124,6 +125,16 @@
renesas,function = "scif0";
};
+ ether_pins: ether {
+ renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
+ renesas,function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ renesas,groups = "intc_irq0";
+ renesas,function = "intc";
+ };
+
scif1_pins: serial1 {
renesas,groups = "scif1_data";
renesas,function = "scif1";
@@ -150,6 +161,21 @@
};
};
+&ether {
+ pinctrl-0 = <&ether_pins &phy1_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "ok";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
&mmcif1 {
pinctrl-0 = <&mmc1_pins>;
pinctrl-names = "default";