diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2015-01-06 10:35:16 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2015-01-21 09:58:58 +0100 |
| commit | d96b7161916f1b5c1a676fba2d54ef0106a88aff (patch) | |
| tree | a1f079e2228eaa0ed76f9d91e1d7f8529df9e152 /arch/arm/boot/dts | |
| parent | 41e7afb1c14f92e02055d130352843665a170a07 (diff) | |
ARM: dts: sun7i: Add cpu clock reference and operating points to dtsi
The cpu core is clocked from the "cpu" clock. Add a reference to it
in the first cpu node. Also add "cpu0" label to the node.
The operating points were taken from the A20 FEX files in the
sunxi-boards repository. Not all boards have the same settings. The
settings in this patch are the most generic ones.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/sun7i-a20.dtsi | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 17639ad57186..c2e964939991 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -87,10 +87,26 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + clocks = <&cpu>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1450000 + 960000 1400000 + 912000 1400000 + 864000 1300000 + 720000 1200000 + 528000 1100000 + 312000 1000000 + 144000 900000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; }; cpu@1 { |