diff options
| author | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2018-05-07 06:35:41 -0300 |
|---|---|---|
| committer | Jonathan Corbet <corbet@lwn.net> | 2018-05-08 10:02:34 -0600 |
| commit | de0f51e4b1391145e47d6aa60681dab091bcc777 (patch) | |
| tree | 03307fd645fcf3b2c9d45d8cb3711b4143891904 /Documentation/memory-barriers.txt | |
| parent | fe8703cc0de67695e3385ba78b5dfb1091769d50 (diff) | |
docs: core-api: add cachetlb documentation
The cachetlb.txt is already in ReST format. So, move it to the
core-api guide, where it belongs.
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation/memory-barriers.txt')
| -rw-r--r-- | Documentation/memory-barriers.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 6dafc8085acc..983249906fc6 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -2903,7 +2903,7 @@ is discarded from the CPU's cache and reloaded. To deal with this, the appropriate part of the kernel must invalidate the overlapping bits of the cache on each CPU. -See Documentation/cachetlb.txt for more information on cache management. +See Documentation/core-api/cachetlb.rst for more information on cache management. CACHE COHERENCY VS MMIO |