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authorArnd Bergmann <arnd@arndb.de>2014-12-04 17:20:02 +0100
committerArnd Bergmann <arnd@arndb.de>2014-12-04 17:20:02 +0100
commite58e501a9b3e0db722263b02d6c06f1656a5dee7 (patch)
treeba828148967f084f3301016d7215e0338cec1445 /Documentation/devicetree
parenta8afa2645ccf3525409c749c1dc4ec1cf95ff3f5 (diff)
parent8918465163171322c77a19d5258a95f56d89d2e4 (diff)
Merge tag 'tegra-for-3.19-iommu' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers
Pull "ARM: tegra: IOMMU support for v3.19" from Thierry Reding: This adds the driver pieces required for IOMMU support on Tegra30, Tegra114 and Tegra124. * tag 'tegra-for-3.19-iommu' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: Add NVIDIA Tegra memory controller support of: Add NVIDIA Tegra memory controller binding ARM: tegra: Move AHB Kconfig to drivers/amba amba: Add Kconfig file clk: tegra: Implement memory-controller clock powerpc/iommu: Rename iommu_[un]map_sg functions iommu: Improve error handling when setting bus iommu iommu: Do more input validation in iommu_map_sg() iommu: Add iommu_map_sg() function Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt36
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diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt
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+NVIDIA Tegra Memory Controller device tree bindings
+===================================================
+
+Required properties:
+- compatible: Should be "nvidia,tegra<chip>-mc"
+- reg: Physical base address and length of the controller's registers.
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - mc: the module's clock input
+- interrupts: The interrupt outputs from the controller.
+- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
+ the SWGROUP of the master.
+
+This device implements an IOMMU that complies with the generic IOMMU binding.
+See ../iommu/iommu.txt for details.
+
+Example:
+--------
+
+ mc: memory-controller@0,70019000 {
+ compatible = "nvidia,tegra124-mc";
+ reg = <0x0 0x70019000 0x0 0x1000>;
+ clocks = <&tegra_car TEGRA124_CLK_MC>;
+ clock-names = "mc";
+
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <1>;
+ };
+
+ sdhci@0,700b0000 {
+ compatible = "nvidia,tegra124-sdhci";
+ ...
+ iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
+ };