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authorRomain Perier <romain.perier@free-electrons.com>2016-09-16 12:08:50 +0200
committerHerbert Xu <herbert@gondor.apana.org.au>2016-10-21 10:26:20 +0800
commit52060836f79080849dd90e3ae1aeb288411f3def (patch)
treec72348e5377177fd451b6041ee83eca6a2d8c014 /Documentation/devicetree/bindings/rng/omap_rng.txt
parente4d6013eafb6c40e5805d02e673a5f023fe0f699 (diff)
dt-bindings: omap-rng: Document SafeXcel IP-76 device variant
This commits add missing fields in the documentation that are used by the new device variant. It also includes DT example to show how the variant should be used. Signed-off-by: Romain Perier <romain.perier@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'Documentation/devicetree/bindings/rng/omap_rng.txt')
-rw-r--r--Documentation/devicetree/bindings/rng/omap_rng.txt14
1 files changed, 12 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/rng/omap_rng.txt b/Documentation/devicetree/bindings/rng/omap_rng.txt
index 6a62acd86953..471477299ece 100644
--- a/Documentation/devicetree/bindings/rng/omap_rng.txt
+++ b/Documentation/devicetree/bindings/rng/omap_rng.txt
@@ -1,4 +1,4 @@
-OMAP SoC HWRNG Module
+OMAP SoC and Inside-Secure HWRNG Module
Required properties:
@@ -6,11 +6,13 @@ Required properties:
RNG versions:
- "ti,omap2-rng" for OMAP2.
- "ti,omap4-rng" for OMAP4, OMAP5 and AM33XX.
+ - "inside-secure,safexcel-eip76" for SoCs with EIP76 IP block
Note that these two versions are incompatible.
- ti,hwmods: Name of the hwmod associated with the RNG module
- reg : Offset and length of the register set for the module
- interrupts : the interrupt number for the RNG module.
- Only used for "ti,omap4-rng".
+ Used for "ti,omap4-rng" and "inside-secure,safexcel-eip76"
+- clocks: the trng clock source
Example:
/* AM335x */
@@ -20,3 +22,11 @@ rng: rng@48310000 {
reg = <0x48310000 0x2000>;
interrupts = <111>;
};
+
+/* SafeXcel IP-76 */
+trng: rng@f2760000 {
+ compatible = "inside-secure,safexcel-eip76";
+ reg = <0xf2760000 0x7d>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_syscon0 1 25>;
+};