diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-11-16 15:48:26 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-11-16 15:48:26 -0800 |
| commit | 527d1470744d338c912f94bc1f4dba08ffdff349 (patch) | |
| tree | 36efab7e8fecaac465986b315c014166c03a079e | |
| parent | 8c609698569578913ad40bb160b97c3f6cfa15ec (diff) | |
| parent | ba5b5034bd29ad94a16d73ed64fbeab0fa863f4d (diff) | |
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM device-tree updates from Arnd Bergmann:
"We add device tree files for a couple of additional SoCs in various
areas:
Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for
networking, Amlogic A113D for audio, and Renesas R-Car V3M for
automotive.
As usual, lots of new boards get added based on those and other SoCs:
- Actions S500 based CubieBoard6 single-board computer
- Amlogic Meson-AXG A113D based development board
- Amlogic S912 based Khadas VIM2 single-board computer
- Amlogic S912 based Tronsmart Vega S96 set-top-box
- Allwinner H5 based NanoPi NEO Plus2 single-board computer
- Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers
- Allwinner A83T based TBS A711 Tablet
- Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8
- Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500
wireless access points and routers
- NXP i.MX51 based Zodiac Inflight Innovations RDU1 board
- NXP i.MX53 based GE Healthcare PPD biometric monitor
- NXP i.MX6 based Pistachio single-board computer
- NXP i.MX6 based Vining-2000 automotive diagnostic interface
- NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants
- Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone
- Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet
- Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA
- Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board
- Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards
- Renasas r8a7745 based iWave G22D-SODIMM SoM
- Rockchip rk3288 based Amarula Vyasa single-board computer
- Samsung Exynos5800 based Odroid HC1 single-board computer
For existing SoC support, there was a lot of ongoing work, as usual
most of that concentrated on the Renesas, Rockchip, OMAP, i.MX,
Amlogic and Allwinner platforms, but others were also active.
Rob Herring and many others worked on reducing the number of issues
that the latest version of 'dtc' now warns about. Unfortunately there
is still a lot left to do.
A rework of the ARM foundation model introduced several new files for
common variations of the model"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (599 commits)
arm64: dts: uniphier: route on-board device IRQ to GPIO controller for PXs3
dt-bindings: bus: Add documentation for the Technologic Systems NBUS
arm64: dts: actions: s900-bubblegum-96: Add fake uart5 clock
ARM: dts: owl-s500: Add CubieBoard6
dt-bindings: arm: actions: Add CubieBoard6
ARM: dts: owl-s500-guitar-bb-rev-b: Add fake uart3 clock
ARM: dts: owl-s500: Set power domains for CPU2 and CPU3
arm: dts: mt7623: remove unused compatible string for pio node
arm: dts: mt7623: update usb related nodes
arm: dts: mt7623: update crypto node
ARM: dts: sun8i: a711: Enable USB OTG
ARM: dts: sun8i: a711: Add regulator support
ARM: dts: sun8i: a83t: bananapi-m3: Enable AP6212 WiFi on mmc1
ARM: dts: sun8i: a83t: cubietruck-plus: Enable AP6330 WiFi on mmc1
ARM: dts: sun8i: a83t: Move mmc1 pinctrl setting to dtsi file
ARM: dts: sun8i: a83t: allwinner-h8homlet-v2: Add AXP818 regulator nodes
ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813 regulator nodes
ARM: dts: sun8i: a83t: cubietruck-plus: Add AXP818 regulator nodes
ARM: dts: sunxi: Add dtsi for AXP81x PMIC
arm64: dts: allwinner: H5: Restore EMAC changes
...
608 files changed, 28063 insertions, 15882 deletions
diff --git a/Documentation/devicetree/bindings/arm/actions.txt b/Documentation/devicetree/bindings/arm/actions.txt index 3bc7ea575564..ced764a8549e 100644 --- a/Documentation/devicetree/bindings/arm/actions.txt +++ b/Documentation/devicetree/bindings/arm/actions.txt @@ -21,6 +21,7 @@ Boards: Root node property compatible must contain, depending on board: + - Cubietech CubieBoard6: "cubietech,cubieboard6" - LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar" diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 4e4bc0bae597..f747f47922c5 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -41,6 +41,10 @@ Boards with the Amlogic Meson GXM S912 SoC shall have the following properties: Required root node property: compatible: "amlogic,s912", "amlogic,meson-gxm"; +Boards with the Amlogic Meson AXG A113D SoC shall have the following properties: + Required root node property: + compatible: "amlogic,a113d", "amlogic,meson-axg"; + Board compatible values (alphabetically, grouped by SoC): - "geniatech,atv1200" (Meson6) @@ -71,8 +75,12 @@ Board compatible values (alphabetically, grouped by SoC): - "amlogic,q200" (Meson gxm s912) - "amlogic,q201" (Meson gxm s912) + - "khadas,vim2" (Meson gxm s912) - "kingnovel,r-box-pro" (Meson gxm S912) - "nexbox,a1" (Meson gxm s912) + - "tronsmart,vega-s96" (Meson gxm s912) + + - "amlogic,s400" (Meson axg a113d) Amlogic Meson Firmware registers Interface ------------------------------------------ diff --git a/Documentation/devicetree/bindings/arm/amlogic/analog-top.txt b/Documentation/devicetree/bindings/arm/amlogic/analog-top.txt new file mode 100644 index 000000000000..101dc21014ec --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/analog-top.txt @@ -0,0 +1,20 @@ +Amlogic Meson8 and Meson8b "analog top" registers: +-------------------------------------------------- + +The analog top registers contain information about the so-called +"metal revision" (which encodes the "minor version") of the SoC. + +Required properties: +- reg: the register range of the analog top registers +- compatible: depending on the SoC this should be one of: + - "amlogic,meson8-analog-top" + - "amlogic,meson8b-analog-top" + along with "syscon" + + +Example: + + analog_top: analog-top@81a8 { + compatible = "amlogic,meson8-analog-top", "syscon"; + reg = <0x81a8 0x14>; + }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/assist.txt b/Documentation/devicetree/bindings/arm/amlogic/assist.txt new file mode 100644 index 000000000000..7656812b67b9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/assist.txt @@ -0,0 +1,17 @@ +Amlogic Meson6/Meson8/Meson8b assist registers: +----------------------------------------------- + +The assist registers contain basic information about the SoC, +for example the encoded SoC part number. + +Required properties: +- reg: the register range of the assist registers +- compatible: should be "amlogic,meson-mx-assist" along with "syscon" + + +Example: + + assist: assist@7c00 { + compatible = "amlogic,meson-mx-assist", "syscon"; + reg = <0x7c00 0x200>; + }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/bootrom.txt b/Documentation/devicetree/bindings/arm/amlogic/bootrom.txt new file mode 100644 index 000000000000..407e27f230ab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/bootrom.txt @@ -0,0 +1,17 @@ +Amlogic Meson6/Meson8/Meson8b bootrom: +-------------------------------------- + +The bootrom register area can be used to access SoC specific +information, such as the "misc version". + +Required properties: +- reg: the register range of the bootrom registers +- compatible: should be "amlogic,meson-mx-bootrom" along with "syscon" + + +Example: + + bootrom: bootrom@d9040000 { + compatible = "amlogic,meson-mx-bootrom", "syscon"; + reg = <0xd9040000 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt new file mode 100644 index 000000000000..a124c7fc4dcd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt @@ -0,0 +1,14 @@ +Broadcom Hurricane 2 device tree bindings +--------------------------------------- + +Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs +are based on Broadcom's iProc SoC architecture and feature a single core Cortex +A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND +flash and a PCIe attached integrated switching engine. + +Boards with Hurricane SoCs shall have the following properties: + +Required root node property: + +BCM53342 +compatible = "brcm,bcm53342", "brcm,hr2"; diff --git a/Documentation/devicetree/bindings/arm/realtek.txt b/Documentation/devicetree/bindings/arm/realtek.txt index 13d755787b4f..95839e19ae92 100644 --- a/Documentation/devicetree/bindings/arm/realtek.txt +++ b/Documentation/devicetree/bindings/arm/realtek.txt @@ -12,6 +12,8 @@ Required root node properties: Root node property compatible must contain, depending on board: + - MeLE V9: "mele,v9" + - ProBox2 AVA: "probox2,ava" - Zidoo X9S: "zidoo,x9s" diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index b003148e2945..326d24bca1a9 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -1,5 +1,9 @@ Rockchip platforms device tree bindings --------------------------------------- +- Amarula Vyasa RK3288 board + Required root node properties: + - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; + - Asus Tinker board Required root node properties: - compatible = "asus,rk3288-tinker", "rockchip,rk3288"; diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index fa674818e7e8..e13459618581 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -57,6 +57,7 @@ Required root node properties: - "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel Odroid XU3 Lite board. - "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4. + - "hardkernel,odroid-hc1" - for Exynos5422-based Hardkernel Odroid HC1. * Insignal - "insignal,arndale" - for Exynos5250-based Insignal Arndale board. diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index ae75cb3b1331..020d758fc0c5 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -39,6 +39,8 @@ SoCs: compatible = "renesas,r8a7795" - R-Car M3-W (R8A77960) compatible = "renesas,r8a7796" + - R-Car V3M (R8A77970) + compatible = "renesas,r8a77970" - R-Car D3 (R8A77995) compatible = "renesas,r8a77995" @@ -57,6 +59,8 @@ Boards: compatible = "renesas,bockw", "renesas,r8a7778" - Draak (RTP0RC77995SEB0010S) compatible = "renesas,draak", "renesas,r8a77995" + - Eagle (RTP0RC77970SEB0010S) + compatible = "renesas,eagle", "renesas,r8a77970" - Genmai (RTK772100BC00000BR) compatible = "renesas,genmai", "renesas,r7s72100" - GR-Peach (X28A-M01-E/F) @@ -65,7 +69,7 @@ Boards: compatible = "renesas,gose", "renesas,r8a7793" - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1)) H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0)) - compatible = "renesas,h3ulcb", "renesas,r8a7795"; + compatible = "renesas,h3ulcb", "renesas,r8a7795" - Henninger compatible = "renesas,henninger", "renesas,r8a7791" - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D) @@ -76,6 +80,8 @@ Boards: compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743" - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) compatible = "iwave,g20m", "renesas,r8a7743" + - Kingfisher (SBEV-RCAR-KF-M03) + compatible = "shimafuji,kingfisher" - Koelsch (RTP0RC7791SEB00010S) compatible = "renesas,koelsch", "renesas,r8a7791" - Kyoto Microcomputer Co. KZM-A9-Dual @@ -85,7 +91,7 @@ Boards: - Lager (RTP0RC7790SEB00010S) compatible = "renesas,lager", "renesas,r8a7790" - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0)) - compatible = "renesas,m3ulcb", "renesas,r8a7796"; + compatible = "renesas,m3ulcb", "renesas,r8a7796" - Marzen (R0P7779A00010S) compatible = "renesas,marzen", "renesas,r8a7779" - Porter (M2-LCDP) @@ -93,11 +99,11 @@ Boards: - RSKRZA1 (YR0K77210C000BE) compatible = "renesas,rskrza1", "renesas,r7s72100" - Salvator-X (RTP0RC7795SIPB0010S) - compatible = "renesas,salvator-x", "renesas,r8a7795"; + compatible = "renesas,salvator-x", "renesas,r8a7795" - Salvator-X (RTP0RC7796SIPB0011S) - compatible = "renesas,salvator-x", "renesas,r8a7796"; + compatible = "renesas,salvator-x", "renesas,r8a7796" - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S) - compatible = "renesas,salvator-xs", "renesas,r8a7795"; + compatible = "renesas,salvator-xs", "renesas,r8a7795" - SILK (RTP0RC7794LCB00011S) compatible = "renesas,silk", "renesas,r8a7794" - SK-RZG1E (YR8A77450S000BE) diff --git a/Documentation/devicetree/bindings/bus/ts-nbus.txt b/Documentation/devicetree/bindings/bus/ts-nbus.txt new file mode 100644 index 000000000000..2a10d065b9fa --- /dev/null +++ b/Documentation/devicetree/bindings/bus/ts-nbus.txt @@ -0,0 +1,50 @@ +Technologic Systems NBUS + +The NBUS is a bus used to interface with peripherals in the Technologic +Systems FPGA on the TS-4600 SoM. + +Required properties : + - compatible : "technologic,ts-nbus" + - #address-cells : must be 1 + - #size-cells : must be 0 + - pwms : The PWM bound to the FPGA + - ts,data-gpios : The 8 GPIO pins connected to the data lines on the FPGA + - ts,csn-gpios : The GPIO pin connected to the csn line on the FPGA + - ts,txrx-gpios : The GPIO pin connected to the txrx line on the FPGA + - ts,strobe-gpios : The GPIO pin connected to the stobe line on the FPGA + - ts,ale-gpios : The GPIO pin connected to the ale line on the FPGA + - ts,rdy-gpios : The GPIO pin connected to the rdy line on the FPGA + +Child nodes: + +The NBUS node can contain zero or more child nodes representing peripherals +on the bus. + +Example: + + nbus { + compatible = "technologic,ts-nbus"; + pinctrl-0 = <&nbus_pins>; + #address-cells = <1>; + #size-cells = <0>; + pwms = <&pwm 2 83>; + ts,data-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH + &gpio0 1 GPIO_ACTIVE_HIGH + &gpio0 2 GPIO_ACTIVE_HIGH + &gpio0 3 GPIO_ACTIVE_HIGH + &gpio0 4 GPIO_ACTIVE_HIGH + &gpio0 5 GPIO_ACTIVE_HIGH + &gpio0 6 GPIO_ACTIVE_HIGH + &gpio0 7 GPIO_ACTIVE_HIGH>; + ts,csn-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + ts,txrx-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + ts,strobe-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + ts,ale-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + ts,rdy-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + + watchdog@2a { + compatible = "..."; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index f2c5f0e4a363..f8e4a93466cb 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -137,6 +137,20 @@ These clock IDs are defined in: ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1 ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2 +Hurricane 2 +------ +PLL and leaf clock compatible strings for Hurricane 2 are: + "brcm,hr2-armpll" + +The following table defines the set of PLL/clock for Hurricane 2: + + Clock Source Index ID + --- ----- ----- --------- + crystal N/A N/A N/A + + armpll crystal N/A N/A + + Northstar and Northstar Plus ------ PLL and leaf clock compatible strings for Northstar and Northstar Plus are: diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt index b1a8929c2536..3a72a103a18a 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt @@ -37,7 +37,7 @@ Optional properties: Example: - hdmi0: hdmi0@fead0000 { + hdmi0: hdmi@fead0000 { compatible = "renesas,r8a7795-dw-hdmi"; reg = <0 0xfead0000 0 0x10000>; interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>; diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt index d4c34774d626..7fccc20d8331 100644 --- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt +++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt @@ -18,7 +18,7 @@ Required properties: - #dma-cells : Should be 1, a single cell holding a line request number Example: - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun6i-a31-dma"; reg = <0x01c02000 0x1000>; interrupts = <0 50 4>; diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index b4ebd56d03f3..c6814d7cc2b2 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -13,6 +13,10 @@ Required properties: + allwinner,sun50i-h5-mali + amlogic,meson-gxbb-mali + amlogic,meson-gxl-mali + + rockchip,rk3036-mali + + rockchip,rk3066-mali + + rockchip,rk3188-mali + + rockchip,rk3228-mali + stericsson,db8500-mali - reg: Physical base address and length of the GPU registers @@ -40,10 +44,18 @@ Optional properties: Memory region to allocate from, as defined in Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt + - mali-supply: + Phandle to regulator for the Mali device, as defined in + Documentation/devicetree/bindings/regulator/regulator.txt for details. + - operating-points-v2: Operating Points for the GPU, as defined in Documentation/devicetree/bindings/opp/opp.txt + - power-domains: + A power domain consumer specifier as defined in + Documentation/devicetree/bindings/power/power_domain.txt + Vendor-specific bindings ------------------------ @@ -63,6 +75,10 @@ to specify one more vendor-specific compatible, among: Required properties: * resets: phandle to the reset line for the GPU + - Rockchip variants: + Required properties: + * resets: phandle to the reset line for the GPU + - stericsson,db8500-mali Required properties: * interrupt-names and interrupts: diff --git a/Documentation/devicetree/bindings/misc/ge-achc.txt b/Documentation/devicetree/bindings/misc/ge-achc.txt new file mode 100644 index 000000000000..77df94d7a32f --- /dev/null +++ b/Documentation/devicetree/bindings/misc/ge-achc.txt @@ -0,0 +1,26 @@ +* GE Healthcare USB Management Controller + +A device which handles data aquisition from compatible USB based peripherals. +SPI is used for device management. + +Note: This device does not expose the peripherals as USB devices. + +Required properties: + +- compatible : Should be "ge,achc" + +Required SPI properties: + +- reg : Should be address of the device chip select within + the controller. + +- spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be + 1MHz for the GE ACHC. + +Example: + +spidev0: spi@0 { + compatible = "ge,achc"; + reg = <0>; + spi-max-frequency = <1000000>; +}; diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt index 9ce35af8507c..4cab5d85cf6f 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt @@ -13,6 +13,7 @@ Required properties: at25df321a at25df641 at26df081a + en25s64 mr25h256 mr25h10 mr25h40 @@ -31,6 +32,7 @@ Required properties: s25fl008k s25fl064k sst25vf040b + sst25wf040b m25p40 m25p80 m25p16 diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt new file mode 100644 index 000000000000..3d6d5fa0c4d5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -0,0 +1,207 @@ +* Allwinner sun8i GMAC ethernet controller + +This device is a platform glue layer for stmmac. +Please see stmmac.txt for the other unchanged properties. + +Required properties: +- compatible: must be one of the following string: + "allwinner,sun8i-a83t-emac" + "allwinner,sun8i-h3-emac" + "allwinner,sun8i-v3s-emac" + "allwinner,sun50i-a64-emac" +- reg: address and length of the register for the device. +- interrupts: interrupt for the device +- interrupt-names: must be "macirq" +- clocks: A phandle to the reference clock for this device +- clock-names: must be "stmmaceth" +- resets: A phandle to the reset control for this device +- reset-names: must be "stmmaceth" +- phy-mode: See ethernet.txt +- phy-handle: See ethernet.txt +- #address-cells: shall be 1 +- #size-cells: shall be 0 +- syscon: A phandle to the syscon of the SoC with one of the following + compatible string: + - allwinner,sun8i-h3-system-controller + - allwinner,sun8i-v3s-system-controller + - allwinner,sun50i-a64-system-controller + - allwinner,sun8i-a83t-system-controller + +Optional properties: +- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0) +- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0) +Both delay properties need to be a multiple of 100. They control the delay for +external PHY. + +Optional properties for the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- allwinner,leds-active-low: EPHY LEDs are active low + +Required child node of emac: +- mdio bus node: should be named mdio with compatible "snps,dwmac-mdio" + +Required properties of the mdio node: +- #address-cells: shall be 1 +- #size-cells: shall be 0 + +The device node referenced by "phy" or "phy-handle" must be a child node +of the mdio node. See phy.txt for the generic PHY bindings. + +The following compatibles require that the emac node have a mdio-mux child +node called "mdio-mux": + - "allwinner,sun8i-h3-emac" + - "allwinner,sun8i-v3s-emac": +Required properties for the mdio-mux node: + - compatible = "allwinner,sun8i-h3-mdio-mux" + - mdio-parent-bus: a phandle to EMAC mdio + - one child mdio for the integrated mdio with the compatible + "allwinner,sun8i-h3-mdio-internal" + - one child mdio for the external mdio if present (V3s have none) +Required properties for the mdio-mux children node: + - reg: 1 for internal MDIO bus, 2 for external MDIO bus + +The following compatibles require a PHY node representing the integrated +PHY, under the integrated MDIO bus node if an mdio-mux node is used: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": + +Additional information regarding generic multiplexer properties can be found +at Documentation/devicetree/bindings/net/mdio-mux.txt + +Required properties of the integrated phy node: +- clocks: a phandle to the reference clock for the EPHY +- resets: a phandle to the reset control for the EPHY +- Must be a child of the integrated mdio + +Example with integrated PHY: +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + mdio-parent-bus = <&mdio>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +Example with external PHY: +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + allwinner,leds-active-low; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + mdio-parent-bus = <&mdio>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + ext_rgmii_phy: ethernet-phy@1 { + reg = <1>; + }; + }: + }; +}; + +Example with SoC without integrated PHY + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + ext_rgmii_phy: ethernet-phy@1 { + reg = <1>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 33e3d3c47552..58c2a4c229db 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -143,6 +143,24 @@ Required properties: * 16 : Alternate Function 15 * 17 : Analog + To simplify the usage, macro is available to generate "pinmux" field. + This macro is available here: + - include/dt-bindings/pinctrl/stm32-pinfunc.h + + Some examples of using macro: + /* GPIO A9 set as alernate function 2 */ + ... { + pinmux = <STM32_PINMUX('A', 9, AF2)>; + }; + /* GPIO A9 set as GPIO */ + ... { + pinmux = <STM32_PINMUX('A', 9, GPIO)>; + }; + /* GPIO A9 set as analog */ + ... { + pinmux = <STM32_PINMUX('A', 9, ANALOG)>; + }; + Optional properties: - GENERIC_PINCONFIG: is the generic pinconfig options to use. Available options are: @@ -165,13 +183,13 @@ pin-controller { ... usart1_pins_a: usart1@0 { pins1 { - pinmux = <STM32F429_PA9_FUNC_USART1_TX>; + pinmux = <STM32_PINMUX('A', 9, AF7)>; bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32F429_PA10_FUNC_USART1_RX>; + pinmux = <STM32_PINMUX('A', 10, AF7)>; bias-disable; }; }; diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt index af21502e939c..f747f95eee58 100644 --- a/Documentation/devicetree/bindings/power/renesas,apmu.txt +++ b/Documentation/devicetree/bindings/power/renesas,apmu.txt @@ -8,6 +8,7 @@ Required properties: - compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback. Examples with soctypes are: - "renesas,r8a7743-apmu" (RZ/G1M) + - "renesas,r8a7745-apmu" (RZ/G1E) - "renesas,r8a7790-apmu" (R-Car H2) - "renesas,r8a7791-apmu" (R-Car M2-W) - "renesas,r8a7792-apmu" (R-Car V2H) diff --git a/Documentation/devicetree/bindings/serial/mvebu-uart.txt b/Documentation/devicetree/bindings/serial/mvebu-uart.txt index 6087defd9f93..d37fabe17bd1 100644 --- a/Documentation/devicetree/bindings/serial/mvebu-uart.txt +++ b/Documentation/devicetree/bindings/serial/mvebu-uart.txt @@ -8,6 +8,6 @@ Required properties: Example: serial@12000 { compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x400>; + reg = <0x12000 0x200>; interrupts = <43>; }; diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt index 13b1fcc8469e..dcc7eaada511 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt @@ -5,6 +5,7 @@ Required properties: "fsl,ls2085a-dspi" or "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi" + "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi" - reg : Offset and length of the register set for the device - interrupts : Should contain SPI controller interrupt - clocks: from common clock binding: handle to dspi clock. diff --git a/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt b/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt index d48fc5280d5a..cef716a236f1 100644 --- a/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt @@ -13,6 +13,7 @@ Example : +for Hi6220: tsensor: tsensor@0,f7030700 { compatible = "hisilicon,tsensor"; reg = <0x0 0xf7030700 0x0 0x1000>; @@ -21,3 +22,11 @@ Example : clock-names = "thermal_clk"; #thermal-sensor-cells = <1>; } + +for Hi3660: + tsensor: tsensor@fff30000 { + compatible = "hisilicon,hi3660-tsensor"; + reg = <0x0 0xfff30000 0x0 0x1000>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + #thermal-sensor-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt new file mode 100644 index 000000000000..276387dd6815 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt @@ -0,0 +1,32 @@ +NVIDIA Tegra186 BPMP thermal sensor + +In Tegra186, the BPMP (Boot and Power Management Processor) implements an +interface that is used to read system temperatures, including CPU cluster +and GPU temperatures. This binding describes the thermal sensor that is +exposed by BPMP. + +The BPMP thermal node must be located directly inside the main BPMP node. See +../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding. + +This node represents a thermal sensor. See thermal.txt for details of the +core thermal binding. + +Required properties: +- compatible: + Array of strings. + One of: + - "nvidia,tegra186-bpmp-thermal". +- #thermal-sensor-cells: Cell for sensor index. + Single-cell integer. + Must be <1>. + +Example: + +bpmp { + ... + + bpmp_thermal: thermal { + compatible = "nvidia,tegra186-bpmp-thermal"; + #thermal-sensor-cells = <1>; + }; +}; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1db9dbef3e56..0994bdd82cd3 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -18,6 +18,7 @@ al Annapurna Labs allwinner Allwinner Technology Co., Ltd. alphascale AlphaScale Integrated Circuits Systems, Inc. altr Altera Corp. +amarula Amarula Solutions amazon Amazon.com, Inc. amcc Applied Micro Circuits Corporation (APM, formally AMCC) amd Advanced Micro Devices (AMD), Inc. @@ -114,6 +115,7 @@ everspin Everspin Technologies, Inc. exar Exar Corporation excito Excito ezchip EZchip Semiconductor +fairphone Fairphone B.V. faraday Faraday Technology Corporation fcs Fairchild Semiconductor firefly Firefly @@ -199,6 +201,7 @@ mcube mCube meas Measurement Specialties mediatek MediaTek Inc. megachips MegaChips +mele Shenzhen MeLE Digital Technology Ltd. melexis Melexis N.V. melfas MELFAS Inc. mellanox Mellanox Technologies @@ -270,6 +273,7 @@ plathome Plat'Home Co., Ltd. plda PLDA poslab Poslab Technology Co., Ltd. powervr PowerVR (deprecated, use img) +probox2 PROBOX2 (by W2COMP Co., Ltd.) pulsedlight PulsedLight, Inc qca Qualcomm Atheros, Inc. qcom Qualcomm Technologies, Inc @@ -338,6 +342,7 @@ swir Sierra Wireless syna Synaptics Inc. synology Synology, Inc. tbs TBS Technologies +tbs-biometrics Touchless Biometric Systems AG tcg Trusted Computing Group tcl Toby Churchill Ltd. technexion TechNexion @@ -361,6 +366,7 @@ truly Truly Semiconductors Limited tsd Theobroma Systems Design und Consulting GmbH tyan Tyan Computer Corporation ucrobotics uCRobotics +ubnt Ubiquiti Networks udoo Udoo uniwest United Western Technologies Corp (UniWest) upisemi uPI Semiconductor Corp. diff --git a/MAINTAINERS b/MAINTAINERS index b549f4dd6160..485f793029c9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1761,6 +1761,7 @@ Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next S: Supported F: arch/arm64/boot/dts/renesas/ +F: Documentation/devicetree/bindings/arm/shmobile.txt F: drivers/soc/renesas/ F: include/linux/soc/renesas/ @@ -1880,6 +1881,7 @@ F: arch/arm/boot/dts/sh* F: arch/arm/configs/shmobile_defconfig F: arch/arm/include/debug/renesas-scif.S F: arch/arm/mach-shmobile/ +F: Documentation/devicetree/bindings/arm/shmobile.txt F: drivers/soc/renesas/ F: include/linux/soc/renesas/ diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 25dcf4e534e6..d0381e9caf21 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -101,6 +101,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4709-tplink-archer-c9-v1.dtb \ bcm47094-dlink-dir-885l.dtb \ bcm47094-linksys-panamera.dtb \ + bcm47094-luxul-abr-4500.dtb \ + bcm47094-luxul-xbr-4500.dtb \ bcm47094-luxul-xwr-3100.dtb \ bcm47094-netgear-r8500.dtb \ bcm94708.dtb \ @@ -109,6 +111,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm953012hr.dtb \ bcm953012k.dtb dtb-$(CONFIG_ARCH_BCM_53573) += \ + bcm47189-luxul-xap-1440.dtb \ + bcm47189-luxul-xap-810.dtb \ bcm47189-tenda-ac9.dtb \ bcm947189acdbmr.dtb dtb-$(CONFIG_ARCH_BCM_63XX) += \ @@ -118,6 +122,8 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ bcm911360k.dtb \ bcm958300k.dtb \ bcm958305k.dtb +dtb-$(CONFIG_ARCH_BCM_HR2) += \ + bcm53340-ubnt-unifi-switch8.dtb dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ bcm28155-ap.dtb \ bcm21664-garnet.dtb \ @@ -177,6 +183,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5420-arndale-octa.dtb \ exynos5420-peach-pit.dtb \ exynos5420-smdk5420.dtb \ + exynos5422-odroidhc1.dtb \ exynos5422-odroidxu3.dtb \ exynos5422-odroidxu3-lite.dtb \ exynos5422-odroidxu4.dtb \ @@ -342,12 +349,14 @@ dtb-$(CONFIG_SOC_IMX51) += \ imx51-babbage.dtb \ imx51-digi-connectcore-jsk.dtb \ imx51-eukrea-mbimxsd51-baseboard.dtb \ - imx51-ts4800.dtb + imx51-ts4800.dtb \ + imx51-zii-rdu1.dtb dtb-$(CONFIG_SOC_IMX53) += \ imx53-ard.dtb \ imx53-cx9020.dtb \ imx53-m53evk.dtb \ imx53-mba53.dtb \ + imx53-ppd.dtb \ imx53-qsb.dtb \ imx53-qsrb.dtb \ imx53-smd.dtb \ @@ -389,14 +398,19 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-ts4900.dtb \ imx6dl-tx6dl-comtft.dtb \ imx6dl-tx6s-8034.dtb \ + imx6dl-tx6s-8034-mb7.dtb \ imx6dl-tx6s-8035.dtb \ + imx6dl-tx6s-8035-mb7.dtb \ imx6dl-tx6u-801x.dtb \ + imx6dl-tx6u-80xx-mb7.dtb \ imx6dl-tx6u-8033.dtb \ + imx6dl-tx6u-8033-mb7.dtb \ imx6dl-tx6u-811x.dtb \ imx6dl-tx6u-81xx-mb7.dtb \ imx6dl-udoo.dtb \ imx6dl-wandboard.dtb \ imx6dl-wandboard-revb1.dtb \ + imx6dl-wandboard-revd1.dtb \ imx6q-apalis-eval.dtb \ imx6q-apalis-ixora.dtb \ imx6q-apalis-ixora-v1.1.dtb \ @@ -408,6 +422,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-cm-fx6.dtb \ imx6q-cubox-i.dtb \ imx6q-dfi-fs700-m60.dtb \ + imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ @@ -435,6 +450,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-nitrogen6_som2.dtb \ imx6q-novena.dtb \ imx6q-phytec-pbab01.dtb \ + imx6q-pistachio.dtb \ imx6q-rex-pro.dtb \ imx6q-sabreauto.dtb \ imx6q-sabrelite.dtb \ @@ -448,17 +464,25 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-tx6q-1020.dtb \ imx6q-tx6q-1020-comtft.dtb \ imx6q-tx6q-1036.dtb \ + imx6q-tx6q-1036-mb7.dtb \ + imx6q-tx6q-10x0-mb7.dtb \ imx6q-tx6q-1110.dtb \ imx6q-tx6q-11x0-mb7.dtb \ imx6q-udoo.dtb \ imx6q-utilite-pro.dtb \ imx6q-wandboard.dtb \ imx6q-wandboard-revb1.dtb \ + imx6q-wandboard-revd1.dtb \ imx6q-zii-rdu2.dtb \ imx6qp-nitrogen6_max.dtb \ imx6qp-nitrogen6_som2.dtb \ imx6qp-sabreauto.dtb \ imx6qp-sabresd.dtb \ + imx6qp-tx6qp-8037.dtb \ + imx6qp-tx6qp-8037-mb7.dtb \ + imx6qp-tx6qp-8137.dtb \ + imx6qp-tx6qp-8137-mb7.dtb \ + imx6qp-wandboard-revd1.dtb \ imx6qp-zii-rdu2.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-evk.dtb \ @@ -469,6 +493,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-sdb-reva.dtb \ imx6sx-sdb-sai.dtb \ imx6sx-sdb.dtb \ + imx6sx-softing-vining-2000.dtb \ imx6sx-udoo-neo-basic.dtb \ imx6sx-udoo-neo-extended.dtb \ imx6sx-udoo-neo-full.dtb @@ -681,6 +706,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-netgear-wnr854t.dtb \ orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_ACTIONS) += \ + owl-s500-cubieboard6.dtb \ owl-s500-guitar-bb-rev-b.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb @@ -701,7 +727,9 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq8064-ap148.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ + qcom-msm8974-fairphone-fp2.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ + qcom-msm8974-sony-xperia-castor.dtb \ qcom-msm8974-sony-xperia-honami.dtb \ qcom-mdm9615-wp8548-mangoh-green.dtb dtb-$(CONFIG_ARCH_REALVIEW) += \ @@ -725,7 +753,9 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ r8a7743-iwg20d-q7.dtb \ + r8a7743-iwg20d-q7-dbcm-ca.dtb \ r8a7743-sk-rzg1m.dtb \ + r8a7745-iwg22d-sodimm.dtb \ r8a7745-sk-rzg1e.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ @@ -768,7 +798,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ rk3288-veyron-pinky.dtb \ - rk3288-veyron-speedy.dtb + rk3288-veyron-speedy.dtb \ + rk3288-vyasa.dtb dtb-$(CONFIG_ARCH_S3C24XX) += \ s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_S3C64XX) += \ @@ -891,6 +922,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-olinuxino-lime2.dtb \ sun7i-a20-olinuxino-lime2-emmc.dtb \ sun7i-a20-olinuxino-micro.dtb \ + sun7i-a20-olinuxino-micro-emmc.dtb \ sun7i-a20-orangepi.dtb \ sun7i-a20-orangepi-mini.dtb \ sun7i-a20-pcduino3.dtb \ @@ -916,6 +948,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-allwinner-h8homlet-v2.dtb \ sun8i-a83t-bananapi-m3.dtb \ sun8i-a83t-cubietruck-plus.dtb \ + sun8i-a83t-tbs-a711.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-beelink-x2.dtb \ @@ -932,8 +965,10 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-r16-bananapi-m2m.dtb \ sun8i-r16-parrot.dtb \ + sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-v3s-licheepi-zero.dtb \ - sun8i-v3s-licheepi-zero-dock.dtb + sun8i-v3s-licheepi-zero-dock.dtb \ + sun8i-v40-bananapi-m2-berry.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 081fa68b6f98..a04d79ec212a 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -75,6 +75,9 @@ compatible = "gpio-matrix-keypad"; debounce-delay-ms = <5>; col-scan-delay-us = <2>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&matrix_keypad_default>; + pinctrl-1 = <&matrix_keypad_sleep>; row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ @@ -145,6 +148,43 @@ }; &am43xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&unused_pins>; + + unused_pins: unused_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x858, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x860, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x864, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x868, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x86c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x878, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x908, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x91c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x920, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9e0, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA0c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA38, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA3c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA40, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA44, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA48, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA4c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA50, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA54, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA58, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA5c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA60, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA64, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0xA68, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA6C, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA74, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xA78, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ @@ -198,7 +238,7 @@ >; }; - nand_flash_x8: nand_flash_x8 { + nand_flash_x8_default: nand_flash_x8_default { pinctrl-single,pins = < AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ @@ -219,12 +259,39 @@ >; }; - ecap0_pins: backlight_pins { + nand_flash_x8_sleep: nand_flash_x8_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x804, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x808, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x80c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x810, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x814, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x818, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x81c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x870, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x874, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + ecap0_pins_default: backlight_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ >; }; + ecap0_pins_sleep: backlight_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ @@ -232,7 +299,7 @@ >; }; - spi0_pins: pinmux_spi0_pins { + spi0_pins_default: pinmux_spi0_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ @@ -241,7 +308,16 @@ >; }; - spi1_pins: pinmux_spi1_pins { + spi0_pins_sleep: pinmux_spi0_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x958, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + spi1_pins_default: pinmux_spi1_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ @@ -250,13 +326,54 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + spi1_pins_sleep: pinmux_spi1_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x998, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins_default: pinmux_mmc1_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; - qspi1_default: qspi1_default { + mmc1_pins_sleep: pinmux_mmc1_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7) + >; + }; + + matrix_keypad_default: matrix_keypad_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */ + AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */ + AM4372_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd3.gpio2_18 */ + AM4372_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd2.gpio2_19 */ + AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ + AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ + AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.gpio0_14 */ + AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.gpio0_15 */ + >; + }; + + matrix_keypad_sleep: matrix_keypad_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + qspi1_pins_default: qspi1_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) @@ -267,12 +384,29 @@ >; }; - pixcir_ts_pins: pixcir_ts_pins { + qspi1_pins_sleep: qspi1_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + pixcir_ts_pins_default: pixcir_ts_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ >; }; + pixcir_ts_pins_sleep: pixcir_ts_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ + >; + }; + hdq_pins: pinmux_hdq_pins { pinctrl-single,pins = < AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ @@ -355,6 +489,48 @@ >; }; + uart0_pins_default: uart0_pins_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ + AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ + AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart0_pins_sleep: uart0_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) + AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) + >; + }; + + usb2_phy1_default: usb2_phy1_default { + pinctrl-single,pins = < + AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; + + usb2_phy1_sleep: usb2_phy1_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + usb2_phy2_default: usb2_phy2_default { + pinctrl-single,pins = < + AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; + + usb2_phy2_sleep: usb2_phy2_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + mcasp1_pins: mcasp1_pins { pinctrl-single,pins = < AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ @@ -378,8 +554,9 @@ status = "okay"; vmmc-supply = <&vmmcsd_fixed>; bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_sleep>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; @@ -478,8 +655,10 @@ pixcir_ts@5c { compatible = "pixcir,pixcir_tangoc"; - pinctrl-names = "default"; - pinctrl-0 = <&pixcir_ts_pins>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pixcir_ts_pins_default>; + pinctrl-1 = <&pixcir_ts_pins_sleep>; + reg = <0x5c>; interrupt-parent = <&gpio1>; interrupts = <17 IRQ_TYPE_EDGE_FALLING>; @@ -550,8 +729,9 @@ &gpmc { status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ - pinctrl-names = "default"; - pinctrl-0 = <&nand_flash_x8>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&nand_flash_x8_default>; + pinctrl-1 = <&nand_flash_x8_sleep>; ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ nand@0,0 { compatible = "ti,omap2-nand"; @@ -647,24 +827,30 @@ &ecap0 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&ecap0_pins_default>; + pinctrl-1 = <&ecap0_pins_sleep>; }; &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi0_pins_default>; + pinctrl-1 = <&spi0_pins_sleep>; }; &spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_default>; + pinctrl-1 = <&spi1_pins_sleep>; }; &usb2_phy1 { status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb2_phy1_default>; + pinctrl-1 = <&usb2_phy1_sleep>; }; &usb1 { @@ -674,6 +860,9 @@ &usb2_phy2 { status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb2_phy2_default>; + pinctrl-1 = <&usb2_phy2_sleep>; }; &usb2 { @@ -683,8 +872,9 @@ &qspi { status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ - pinctrl-names = "default"; - pinctrl-0 = <&qspi1_default>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi1_pins_default>; + pinctrl-1 = <&qspi1_pins_sleep>; spi-max-frequency = <48000000>; m25p80@0 { @@ -770,6 +960,13 @@ }; }; +&uart0 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart0_pins_default>; + pinctrl-1 = <&uart0_pins_sleep>; +}; + &mcasp1 { #sound-dai-cells = <0>; pinctrl-names = "default", "sleep"; diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts index 4978011df5bd..95040810c094 100644 --- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts +++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts @@ -316,32 +316,32 @@ * change the default environment, unless you know * what you are doing. */ - partition@00000000 { /* u-boot */ + partition@0 { /* u-boot */ label = "RedBoot"; reg = <0x00000000 0x000c0000>; /* 768KB */ }; - partition@000c0000 { /* uImage */ + partition@c0000 { /* uImage */ label = "zImage"; reg = <0x000c0000 0x002d0000>; /* 2880KB */ }; - partition@00390000 { /* uInitramfs */ + partition@390000 { /* uInitramfs */ label = "rd.gz"; reg = <0x00390000 0x00440000>; /* 4250KB */ }; - partition@007d0000 { /* MAC address and serial number */ + partition@7d0000 { /* MAC address and serial number */ label = "vendor"; reg = <0x007d0000 0x00010000>; /* 64KB */ }; - partition@007e0000 { + partition@7e0000 { label = "RedBoot config"; reg = <0x007e0000 0x00010000>; /* 64KB */ }; - partition@007f0000 { + partition@7f0000 { label = "FIS directory"; reg = <0x007f0000 0x00010000>; /* 64KB */ }; diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/armada-385-synology-ds116.dts index 31510eb56f10..36ad571e76f3 100644 --- a/arch/arm/boot/dts/armada-385-synology-ds116.dts +++ b/arch/arm/boot/dts/armada-385-synology-ds116.dts @@ -267,35 +267,35 @@ * enumerated. The MAC address and the serial number are listed * in the "vendor" partition. */ - partition@00000000 { + partition@0 { label = "RedBoot"; reg = <0x00000000 0x000f0000>; read-only; }; - partition@000c0000 { + partition@c0000 { label = "zImage"; reg = <0x000f0000 0x002d0000>; }; - partition@00390000 { + partition@390000 { label = "rd.gz"; reg = <0x003c0000 0x00410000>; }; - partition@007d0000 { + partition@7d0000 { label = "vendor"; reg = <0x007d0000 0x00010000>; read-only; }; - partition@007e0000 { + partition@7e0000 { label = "RedBoot config"; reg = <0x007e0000 0x00010000>; read-only; }; - partition@007f0000 { + partition@7f0000 { label = "FIS directory"; reg = <0x007f0000 0x00010000>; read-only; diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts index d8e05bab0cee..d7228a5461c8 100644 --- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts +++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts @@ -332,32 +332,32 @@ * change the default environment, unless you know * what you are doing. */ - partition@00000000 { /* u-boot */ + partition@0 { /* u-boot */ label = "RedBoot"; reg = <0x00000000 0x000d0000>; /* 832KB */ }; - partition@000c0000 { /* uImage */ + partition@c0000 { /* uImage */ label = "zImage"; reg = <0x000d0000 0x002d0000>; /* 2880KB */ }; - partition@003a0000 { /* uInitramfs */ + partition@3a0000 { /* uInitramfs */ label = "rd.gz"; reg = <0x003a0000 0x00430000>; /* 4250KB */ }; - partition@007d0000 { /* MAC address and serial number */ + partition@7d0000 { /* MAC address and serial number */ label = "vendor"; reg = <0x007d0000 0x00010000>; /* 64KB */ }; - partition@007e0000 { + partition@7e0000 { label = "RedBoot config"; reg = <0x007e0000 0x00010000>; /* 64KB */ }; - partition@007f0000 { + partition@7f0000 { label = "FIS directory"; reg = <0x007f0000 0x00010000>; /* 64KB */ }; diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi index 767cbe8d8557..2ed11773048d 100644 --- a/arch/arm/boot/dts/artpec6.dtsi +++ b/arch/arm/boot/dts/artpec6.dtsi @@ -151,7 +151,6 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; - interrupt-parent = <&intc>; }; pcie: pcie@f8050000 { @@ -185,7 +184,6 @@ compatible = "simple-bus"; #address-cells = <0x1>; #size-cells = <0x1>; - interrupt-parent = <&intc>; ranges; dma-ranges = <0x80000000 0x00000000 0x40000000>; dma-coherent; @@ -195,7 +193,6 @@ clocks = <ð_phy_ref_clk>, <&clkctrl ARTPEC6_CLK_ETH_ACLK>; compatible = "snps,dwc-qos-ethernet-4.10"; - interrupt-parent = <&intc>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf8010000 0x4000>; diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index f53e89d63477..602bc10fdaf4 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -60,3 +60,22 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; }; + +&i2c3 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c7 { + status = "okay"; + + lm75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index e1b523bd5b8b..c786bc2f2919 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -7,10 +7,6 @@ model = "Palmetto BMC"; compatible = "tyan,palmetto-bmc", "aspeed,ast2400"; - aliases { - serial4 = &uart5; - }; - chosen { stdout-path = &uart5; bootargs = "console=ttyS4,115200 earlyprintk"; @@ -62,3 +58,55 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; }; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + }; + + rtc@68 { + compatible = "dallas,ds3231"; + reg = <0x68>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + tmp423@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 6dd77cba191c..8067793129ea 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -80,3 +80,61 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; }; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + /* PCIe slot 1 (x8) */ + status = "okay"; +}; + +&i2c7 { + /* PCIe slot 2 (x16) */ + status = "okay"; +}; + +&i2c8 { + /* PCIe slot 3 (x16) */ + status = "okay"; +}; + +&i2c9 { + /* PCIe slot 4 (x16) */ + status = "okay"; +}; + +&i2c10 { + /* PCIe slot 5 (x8) */ + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index fcc5efbd0879..45d815a86d42 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -8,6 +8,29 @@ #size-cells = <1>; interrupt-parent = <&vic>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &vuart; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -110,7 +133,7 @@ clock-frequency = <192000000>; }; - clk_apb: clk_apb@08 { + clk_apb: clk_apb@8 { #clock-cells = <0>; compatible = "aspeed,g4-apb-clock", "fixed-clock"; reg = <0x08>; @@ -127,750 +150,17 @@ pinctrl: pinctrl { compatible = "aspeed,g4-pinctrl"; - - pinctrl_acpi_default: acpi_default { - function = "ACPI"; - groups = "ACPI"; - }; - - pinctrl_adc0_default: adc0_default { - function = "ADC0"; - groups = "ADC0"; - }; - - pinctrl_adc1_default: adc1_default { - function = "ADC1"; - groups = "ADC1"; - }; - - pinctrl_adc10_default: adc10_default { - function = "ADC10"; - groups = "ADC10"; - }; - - pinctrl_adc11_default: adc11_default { - function = "ADC11"; - groups = "ADC11"; - }; - - pinctrl_adc12_default: adc12_default { - function = "ADC12"; - groups = "ADC12"; - }; - - pinctrl_adc13_default: adc13_default { - function = "ADC13"; - groups = "ADC13"; - }; - - pinctrl_adc14_default: adc14_default { - function = "ADC14"; - groups = "ADC14"; - }; - - pinctrl_adc15_default: adc15_default { - function = "ADC15"; - groups = "ADC15"; - }; - - pinctrl_adc2_default: adc2_default { - function = "ADC2"; - groups = "ADC2"; - }; - - pinctrl_adc3_default: adc3_default { - function = "ADC3"; - groups = "ADC3"; - }; - - pinctrl_adc4_default: adc4_default { - function = "ADC4"; - groups = "ADC4"; - }; - - pinctrl_adc5_default: adc5_default { - function = "ADC5"; - groups = "ADC5"; - }; - - pinctrl_adc6_default: adc6_default { - function = "ADC6"; - groups = "ADC6"; - }; - - pinctrl_adc7_default: adc7_default { - function = "ADC7"; - groups = "ADC7"; - }; - - pinctrl_adc8_default: adc8_default { - function = "ADC8"; - groups = "ADC8"; - }; - - pinctrl_adc9_default: adc9_default { - function = "ADC9"; - groups = "ADC9"; - }; - - pinctrl_bmcint_default: bmcint_default { - function = "BMCINT"; - groups = "BMCINT"; - }; - - pinctrl_ddcclk_default: ddcclk_default { - function = "DDCCLK"; - groups = "DDCCLK"; - }; - - pinctrl_ddcdat_default: ddcdat_default { - function = "DDCDAT"; - groups = "DDCDAT"; - }; - - pinctrl_extrst_default: extrst_default { - function = "EXTRST"; - groups = "EXTRST"; - }; - - pinctrl_flack_default: flack_default { - function = "FLACK"; - groups = "FLACK"; - }; - - pinctrl_flbusy_default: flbusy_default { - function = "FLBUSY"; - groups = "FLBUSY"; - }; - - pinctrl_flwp_default: flwp_default { - function = "FLWP"; - groups = "FLWP"; - }; - - pinctrl_gpid_default: gpid_default { - function = "GPID"; - groups = "GPID"; - }; - - pinctrl_gpid0_default: gpid0_default { - function = "GPID0"; - groups = "GPID0"; - }; - - pinctrl_gpid2_default: gpid2_default { - function = "GPID2"; - groups = "GPID2"; - }; - - pinctrl_gpid4_default: gpid4_default { - function = "GPID4"; - groups = "GPID4"; - }; - - pinctrl_gpid6_default: gpid6_default { - function = "GPID6"; - groups = "GPID6"; - }; - - pinctrl_gpie0_default: gpie0_default { - function = "GPIE0"; - groups = "GPIE0"; - }; - - pinctrl_gpie2_default: gpie2_default { - function = "GPIE2"; - groups = "GPIE2"; - }; - - pinctrl_gpie4_default: gpie4_default { - function = "GPIE4"; - groups = "GPIE4"; - }; - - pinctrl_gpie6_default: gpie6_default { - function = "GPIE6"; - groups = "GPIE6"; - }; - - pinctrl_i2c10_default: i2c10_default { - function = "I2C10"; - groups = "I2C10"; - }; - - pinctrl_i2c11_default: i2c11_default { - function = "I2C11"; - groups = "I2C11"; - }; - - pinctrl_i2c12_default: i2c12_default { - function = "I2C12"; - groups = "I2C12"; - }; - - pinctrl_i2c13_default: i2c13_default { - function = "I2C13"; - groups = "I2C13"; - }; - - pinctrl_i2c14_default: i2c14_default { - function = "I2C14"; - groups = "I2C14"; - }; - - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; - - pinctrl_i2c4_default: i2c4_default { - function = "I2C4"; - groups = "I2C4"; - }; - - pinctrl_i2c5_default: i2c5_default { - function = "I2C5"; - groups = "I2C5"; - }; - - pinctrl_i2c6_default: i2c6_default { - function = "I2C6"; - groups = "I2C6"; - }; - - pinctrl_i2c7_default: i2c7_default { - function = "I2C7"; - groups = "I2C7"; - }; - - pinctrl_i2c8_default: i2c8_default { - function = "I2C8"; - groups = "I2C8"; - }; - - pinctrl_i2c9_default: i2c9_default { - function = "I2C9"; - groups = "I2C9"; - }; - - pinctrl_lpcpd_default: lpcpd_default { - function = "LPCPD"; - groups = "LPCPD"; - }; - - pinctrl_lpcpme_default: lpcpme_default { - function = "LPCPME"; - groups = "LPCPME"; - }; - - pinctrl_lpcrst_default: lpcrst_default { - function = "LPCRST"; - groups = "LPCRST"; - }; - - pinctrl_lpcsmi_default: lpcsmi_default { - function = "LPCSMI"; - groups = "LPCSMI"; - }; - - pinctrl_mac1link_default: mac1link_default { - function = "MAC1LINK"; - groups = "MAC1LINK"; - }; - - pinctrl_mac2link_default: mac2link_default { - function = "MAC2LINK"; - groups = "MAC2LINK"; - }; - - pinctrl_mdio1_default: mdio1_default { - function = "MDIO1"; - groups = "MDIO1"; - }; - - pinctrl_mdio2_default: mdio2_default { - function = "MDIO2"; - groups = "MDIO2"; - }; - - pinctrl_ncts1_default: ncts1_default { - function = "NCTS1"; - groups = "NCTS1"; - }; - - pinctrl_ncts2_default: ncts2_default { - function = "NCTS2"; - groups = "NCTS2"; - }; - - pinctrl_ncts3_default: ncts3_default { - function = "NCTS3"; - groups = "NCTS3"; - }; - - pinctrl_ncts4_default: ncts4_default { - function = "NCTS4"; - groups = "NCTS4"; - }; - - pinctrl_ndcd1_default: ndcd1_default { - function = "NDCD1"; - groups = "NDCD1"; - }; - - pinctrl_ndcd2_default: ndcd2_default { - function = "NDCD2"; - groups = "NDCD2"; - }; - - pinctrl_ndcd3_default: ndcd3_default { - function = "NDCD3"; - groups = "NDCD3"; - }; - - pinctrl_ndcd4_default: ndcd4_default { - function = "NDCD4"; - groups = "NDCD4"; - }; - - pinctrl_ndsr1_default: ndsr1_default { - function = "NDSR1"; - groups = "NDSR1"; - }; - - pinctrl_ndsr2_default: ndsr2_default { - function = "NDSR2"; - groups = "NDSR2"; - }; - - pinctrl_ndsr3_default: ndsr3_default { - function = "NDSR3"; - groups = "NDSR3"; - }; - - pinctrl_ndsr4_default: ndsr4_default { - function = "NDSR4"; - groups = "NDSR4"; - }; - - pinctrl_ndtr1_default: ndtr1_default { - function = "NDTR1"; - groups = "NDTR1"; - }; - - pinctrl_ndtr2_default: ndtr2_default { - function = "NDTR2"; - groups = "NDTR2"; - }; - - pinctrl_ndtr3_default: ndtr3_default { - function = "NDTR3"; - groups = "NDTR3"; - }; - - pinctrl_ndtr4_default: ndtr4_default { - function = "NDTR4"; - groups = "NDTR4"; - }; - - pinctrl_ndts4_default: ndts4_default { - function = "NDTS4"; - groups = "NDTS4"; - }; - - pinctrl_nri1_default: nri1_default { - function = "NRI1"; - groups = "NRI1"; - }; - - pinctrl_nri2_default: nri2_default { - function = "NRI2"; - groups = "NRI2"; - }; - - pinctrl_nri3_default: nri3_default { - function = "NRI3"; - groups = "NRI3"; - }; - - pinctrl_nri4_default: nri4_default { - function = "NRI4"; - groups = "NRI4"; - }; - - pinctrl_nrts1_default: nrts1_default { - function = "NRTS1"; - groups = "NRTS1"; - }; - - pinctrl_nrts2_default: nrts2_default { - function = "NRTS2"; - groups = "NRTS2"; - }; - - pinctrl_nrts3_default: nrts3_default { - function = "NRTS3"; - groups = "NRTS3"; - }; - - pinctrl_oscclk_default: oscclk_default { - function = "OSCCLK"; - groups = "OSCCLK"; - }; - - pinctrl_pwm0_default: pwm0_default { - function = "PWM0"; - groups = "PWM0"; - }; - - pinctrl_pwm1_default: pwm1_default { - function = "PWM1"; - groups = "PWM1"; - }; - - pinctrl_pwm2_default: pwm2_default { - function = "PWM2"; - groups = "PWM2"; - }; - - pinctrl_pwm3_default: pwm3_default { - function = "PWM3"; - groups = "PWM3"; - }; - - pinctrl_pwm4_default: pwm4_default { - function = "PWM4"; - groups = "PWM4"; - }; - - pinctrl_pwm5_default: pwm5_default { - function = "PWM5"; - groups = "PWM5"; - }; - - pinctrl_pwm6_default: pwm6_default { - function = "PWM6"; - groups = "PWM6"; - }; - - pinctrl_pwm7_default: pwm7_default { - function = "PWM7"; - groups = "PWM7"; - }; - - pinctrl_rgmii1_default: rgmii1_default { - function = "RGMII1"; - groups = "RGMII1"; - }; - - pinctrl_rgmii2_default: rgmii2_default { - function = "RGMII2"; - groups = "RGMII2"; - }; - - pinctrl_rmii1_default: rmii1_default { - function = "RMII1"; - groups = "RMII1"; - }; - - pinctrl_rmii2_default: rmii2_default { - function = "RMII2"; - groups = "RMII2"; - }; - - pinctrl_rom16_default: rom16_default { - function = "ROM16"; - groups = "ROM16"; - }; - - pinctrl_rom8_default: rom8_default { - function = "ROM8"; - groups = "ROM8"; - }; - - pinctrl_romcs1_default: romcs1_default { - function = "ROMCS1"; - groups = "ROMCS1"; - }; - - pinctrl_romcs2_default: romcs2_default { - function = "ROMCS2"; - groups = "ROMCS2"; - }; - - pinctrl_romcs3_default: romcs3_default { - function = "ROMCS3"; - groups = "ROMCS3"; - }; - - pinctrl_romcs4_default: romcs4_default { - function = "ROMCS4"; - groups = "ROMCS4"; - }; - - pinctrl_rxd1_default: rxd1_default { - function = "RXD1"; - groups = "RXD1"; - }; - - pinctrl_rxd2_default: rxd2_default { - function = "RXD2"; - groups = "RXD2"; - }; - - pinctrl_rxd3_default: rxd3_default { - function = "RXD3"; - groups = "RXD3"; - }; - - pinctrl_rxd4_default: rxd4_default { - function = "RXD4"; - groups = "RXD4"; - }; - - pinctrl_salt1_default: salt1_default { - function = "SALT1"; - groups = "SALT1"; - }; - - pinctrl_salt2_default: salt2_default { - function = "SALT2"; - groups = "SALT2"; - }; - - pinctrl_salt3_default: salt3_default { - function = "SALT3"; - groups = "SALT3"; - }; - - pinctrl_salt4_default: salt4_default { - function = "SALT4"; - groups = "SALT4"; - }; - - pinctrl_sd1_default: sd1_default { - function = "SD1"; - groups = "SD1"; - }; - - pinctrl_sd2_default: sd2_default { - function = "SD2"; - groups = "SD2"; - }; - - pinctrl_sgpmck_default: sgpmck_default { - function = "SGPMCK"; - groups = "SGPMCK"; - }; - - pinctrl_sgpmi_default: sgpmi_default { - function = "SGPMI"; - groups = "SGPMI"; - }; - - pinctrl_sgpmld_default: sgpmld_default { - function = "SGPMLD"; - groups = "SGPMLD"; - }; - - pinctrl_sgpmo_default: sgpmo_default { - function = "SGPMO"; - groups = "SGPMO"; - }; - - pinctrl_sgpsck_default: sgpsck_default { - function = "SGPSCK"; - groups = "SGPSCK"; - }; - - pinctrl_sgpsi0_default: sgpsi0_default { - function = "SGPSI0"; - groups = "SGPSI0"; - }; - - pinctrl_sgpsi1_default: sgpsi1_default { - function = "SGPSI1"; - groups = "SGPSI1"; - }; - - pinctrl_sgpsld_default: sgpsld_default { - function = "SGPSLD"; - groups = "SGPSLD"; - }; - - pinctrl_sioonctrl_default: sioonctrl_default { - function = "SIOONCTRL"; - groups = "SIOONCTRL"; - }; - - pinctrl_siopbi_default: siopbi_default { - function = "SIOPBI"; - groups = "SIOPBI"; - }; - - pinctrl_siopbo_default: siopbo_default { - function = "SIOPBO"; - groups = "SIOPBO"; - }; - - pinctrl_siopwreq_default: siopwreq_default { - function = "SIOPWREQ"; - groups = "SIOPWREQ"; - }; - - pinctrl_siopwrgd_default: siopwrgd_default { - function = "SIOPWRGD"; - groups = "SIOPWRGD"; - }; - - pinctrl_sios3_default: sios3_default { - function = "SIOS3"; - groups = "SIOS3"; - }; - - pinctrl_sios5_default: sios5_default { - function = "SIOS5"; - groups = "SIOS5"; - }; - - pinctrl_siosci_default: siosci_default { - function = "SIOSCI"; - groups = "SIOSCI"; - }; - - pinctrl_spi1_default: spi1_default { - function = "SPI1"; - groups = "SPI1"; - }; - - pinctrl_spi1debug_default: spi1debug_default { - function = "SPI1DEBUG"; - groups = "SPI1DEBUG"; - }; - - pinctrl_spi1passthru_default: spi1passthru_default { - function = "SPI1PASSTHRU"; - groups = "SPI1PASSTHRU"; - }; - - pinctrl_spics1_default: spics1_default { - function = "SPICS1"; - groups = "SPICS1"; - }; - - pinctrl_timer3_default: timer3_default { - function = "TIMER3"; - groups = "TIMER3"; - }; - - pinctrl_timer4_default: timer4_default { - function = "TIMER4"; - groups = "TIMER4"; - }; - - pinctrl_timer5_default: timer5_default { - function = "TIMER5"; - groups = "TIMER5"; - }; - - pinctrl_timer6_default: timer6_default { - function = "TIMER6"; - groups = "TIMER6"; - }; - - pinctrl_timer7_default: timer7_default { - function = "TIMER7"; - groups = "TIMER7"; - }; - - pinctrl_timer8_default: timer8_default { - function = "TIMER8"; - groups = "TIMER8"; - }; - - pinctrl_txd1_default: txd1_default { - function = "TXD1"; - groups = "TXD1"; - }; - - pinctrl_txd2_default: txd2_default { - function = "TXD2"; - groups = "TXD2"; - }; - - pinctrl_txd3_default: txd3_default { - function = "TXD3"; - groups = "TXD3"; - }; - - pinctrl_txd4_default: txd4_default { - function = "TXD4"; - groups = "TXD4"; - }; - - pinctrl_uart6_default: uart6_default { - function = "UART6"; - groups = "UART6"; - }; - - pinctrl_usbcki_default: usbcki_default { - function = "USBCKI"; - groups = "USBCKI"; - }; - - pinctrl_vgabios_rom_default: vgabios_rom_default { - function = "VGABIOS_ROM"; - groups = "VGABIOS_ROM"; - }; - - pinctrl_vgahs_default: vgahs_default { - function = "VGAHS"; - groups = "VGAHS"; - }; - - pinctrl_vgavs_default: vgavs_default { - function = "VGAVS"; - groups = "VGAVS"; - }; - - pinctrl_vpi18_default: vpi18_default { - function = "VPI18"; - groups = "VPI18"; - }; - - pinctrl_vpi24_default: vpi24_default { - function = "VPI24"; - groups = "VPI24"; - }; - - pinctrl_vpi30_default: vpi30_default { - function = "VPI30"; - groups = "VPI30"; - }; - - pinctrl_vpo12_default: vpo12_default { - function = "VPO12"; - groups = "VPO12"; - }; - - pinctrl_vpo24_default: vpo24_default { - function = "VPO24"; - groups = "VPO24"; - }; - - pinctrl_wdtrst1_default: wdtrst1_default { - function = "WDTRST1"; - groups = "WDTRST1"; - }; - - pinctrl_wdtrst2_default: wdtrst2_default { - function = "WDTRST2"; - groups = "WDTRST2"; - }; - }; }; + adc: adc@1e6e9000 { + compatible = "aspeed,ast2400-adc"; + reg = <0x1e6e9000 0xb0>; + clocks = <&clk_apb>; + #io-channel-cells = <1>; + status = "disabled"; + }; + sram@1e720000 { compatible = "mmio-sram"; reg = <0x1e720000 0x8000>; // 32K @@ -895,23 +185,9 @@ clock-names = "PCLK"; }; - wdt1: wdt@1e785000 { - compatible = "aspeed,ast2400-wdt"; - reg = <0x1e785000 0x1c>; - interrupts = <27>; - }; - - wdt2: wdt@1e785020 { - compatible = "aspeed,ast2400-wdt"; - reg = <0x1e785020 0x1c>; - interrupts = <27>; - clocks = <&clk_apb>; - status = "disabled"; - }; - uart1: serial@1e783000 { compatible = "ns16550a"; - reg = <0x1e783000 0x1000>; + reg = <0x1e783000 0x20>; reg-shift = <2>; interrupts = <9>; clocks = <&clk_uart>; @@ -919,64 +195,1046 @@ status = "disabled"; }; - uart2: serial@1e78d000 { + uart5: serial@1e784000 { compatible = "ns16550a"; - reg = <0x1e78d000 0x1000>; + reg = <0x1e784000 0x20>; reg-shift = <2>; - interrupts = <32>; + interrupts = <10>; clocks = <&clk_uart>; no-loopback-test; status = "disabled"; }; - uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x1000>; + wdt1: watchdog@1e785000 { + compatible = "aspeed,ast2400-wdt"; + reg = <0x1e785000 0x1c>; + }; + + wdt2: watchdog@1e785020 { + compatible = "aspeed,ast2400-wdt"; + reg = <0x1e785020 0x1c>; + }; + + vuart: serial@1e787000 { + compatible = "aspeed,ast2400-vuart"; + reg = <0x1e787000 0x40>; reg-shift = <2>; - interrupts = <33>; + interrupts = <10>; clocks = <&clk_uart>; no-loopback-test; status = "disabled"; }; - uart4: serial@1e78f000 { + uart2: serial@1e78d000 { compatible = "ns16550a"; - reg = <0x1e78f000 0x1000>; + reg = <0x1e78d000 0x20>; reg-shift = <2>; - interrupts = <34>; + interrupts = <32>; clocks = <&clk_uart>; no-loopback-test; status = "disabled"; }; - uart5: serial@1e784000 { + uart3: serial@1e78e000 { compatible = "ns16550a"; - reg = <0x1e784000 0x1000>; + reg = <0x1e78e000 0x20>; reg-shift = <2>; - interrupts = <10>; + interrupts = <33>; clocks = <&clk_uart>; - current-speed = <38400>; no-loopback-test; status = "disabled"; }; - uart6: serial@1e787000 { + uart4: serial@1e78f000 { compatible = "ns16550a"; - reg = <0x1e787000 0x1000>; + reg = <0x1e78f000 0x20>; reg-shift = <2>; - interrupts = <10>; + interrupts = <34>; clocks = <&clk_uart>; no-loopback-test; status = "disabled"; }; - adc: adc@1e6e9000 { - compatible = "aspeed,ast2400-adc"; - reg = <0x1e6e9000 0xb0>; - clocks = <&clk_apb>; - #io-channel-cells = <1>; - status = "disabled"; + i2c: i2c@1e78a000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e78a000 0x1000>; }; }; }; }; + +&i2c { + i2c_ic: interrupt-controller@0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2400-i2c-ic"; + reg = <0x0 0x40>; + interrupts = <12>; + interrupt-controller; + }; + + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x40 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <0>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; + + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x80 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <1>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; + + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0xc0 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <2>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + }; + + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x100 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <3>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + }; + + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x140 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <4>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + }; + + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x180 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <5>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + }; + + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x1c0 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <6>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + }; + + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x300 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <7>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + }; + + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x340 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <8>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + }; + + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x380 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <9>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + }; + + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x3c0 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <10>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + }; + + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x400 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <11>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + }; + + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x440 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <12>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + }; + + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x480 0x40>; + compatible = "aspeed,ast2400-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <13>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; +}; + +&pinctrl { + pinctrl_acpi_default: acpi_default { + function = "ACPI"; + groups = "ACPI"; + }; + + pinctrl_adc0_default: adc0_default { + function = "ADC0"; + groups = "ADC0"; + }; + + pinctrl_adc1_default: adc1_default { + function = "ADC1"; + groups = "ADC1"; + }; + + pinctrl_adc10_default: adc10_default { + function = "ADC10"; + groups = "ADC10"; + }; + + pinctrl_adc11_default: adc11_default { + function = "ADC11"; + groups = "ADC11"; + }; + + pinctrl_adc12_default: adc12_default { + function = "ADC12"; + groups = "ADC12"; + }; + + pinctrl_adc13_default: adc13_default { + function = "ADC13"; + groups = "ADC13"; + }; + + pinctrl_adc14_default: adc14_default { + function = "ADC14"; + groups = "ADC14"; + }; + + pinctrl_adc15_default: adc15_default { + function = "ADC15"; + groups = "ADC15"; + }; + + pinctrl_adc2_default: adc2_default { + function = "ADC2"; + groups = "ADC2"; + }; + + pinctrl_adc3_default: adc3_default { + function = "ADC3"; + groups = "ADC3"; + }; + + pinctrl_adc4_default: adc4_default { + function = "ADC4"; + groups = "ADC4"; + }; + + pinctrl_adc5_default: adc5_default { + function = "ADC5"; + groups = "ADC5"; + }; + + pinctrl_adc6_default: adc6_default { + function = "ADC6"; + groups = "ADC6"; + }; + + pinctrl_adc7_default: adc7_default { + function = "ADC7"; + groups = "ADC7"; + }; + + pinctrl_adc8_default: adc8_default { + function = "ADC8"; + groups = "ADC8"; + }; + + pinctrl_adc9_default: adc9_default { + function = "ADC9"; + groups = "ADC9"; + }; + + pinctrl_bmcint_default: bmcint_default { + function = "BMCINT"; + groups = "BMCINT"; + }; + + pinctrl_ddcclk_default: ddcclk_default { + function = "DDCCLK"; + groups = "DDCCLK"; + }; + + pinctrl_ddcdat_default: ddcdat_default { + function = "DDCDAT"; + groups = "DDCDAT"; + }; + + pinctrl_extrst_default: extrst_default { + function = "EXTRST"; + groups = "EXTRST"; + }; + + pinctrl_flack_default: flack_default { + function = "FLACK"; + groups = "FLACK"; + }; + + pinctrl_flbusy_default: flbusy_default { + function = "FLBUSY"; + groups = "FLBUSY"; + }; + + pinctrl_flwp_default: flwp_default { + function = "FLWP"; + groups = "FLWP"; + }; + + pinctrl_gpid_default: gpid_default { + function = "GPID"; + groups = "GPID"; + }; + + pinctrl_gpid0_default: gpid0_default { + function = "GPID0"; + groups = "GPID0"; + }; + + pinctrl_gpid2_default: gpid2_default { + function = "GPID2"; + groups = "GPID2"; + }; + + pinctrl_gpid4_default: gpid4_default { + function = "GPID4"; + groups = "GPID4"; + }; + + pinctrl_gpid6_default: gpid6_default { + function = "GPID6"; + groups = "GPID6"; + }; + + pinctrl_gpie0_default: gpie0_default { + function = "GPIE0"; + groups = "GPIE0"; + }; + + pinctrl_gpie2_default: gpie2_default { + function = "GPIE2"; + groups = "GPIE2"; + }; + + pinctrl_gpie4_default: gpie4_default { + function = "GPIE4"; + groups = "GPIE4"; + }; + + pinctrl_gpie6_default: gpie6_default { + function = "GPIE6"; + groups = "GPIE6"; + }; + + pinctrl_i2c10_default: i2c10_default { + function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default: i2c11_default { + function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default: i2c12_default { + function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default: i2c13_default { + function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_i2c14_default: i2c14_default { + function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default: i2c4_default { + function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c5_default: i2c5_default { + function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default: i2c6_default { + function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default: i2c7_default { + function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default: i2c8_default { + function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_i2c9_default: i2c9_default { + function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_lpcpd_default: lpcpd_default { + function = "LPCPD"; + groups = "LPCPD"; + }; + + pinctrl_lpcpme_default: lpcpme_default { + function = "LPCPME"; + groups = "LPCPME"; + }; + + pinctrl_lpcrst_default: lpcrst_default { + function = "LPCRST"; + groups = "LPCRST"; + }; + + pinctrl_lpcsmi_default: lpcsmi_default { + function = "LPCSMI"; + groups = "LPCSMI"; + }; + + pinctrl_mac1link_default: mac1link_default { + function = "MAC1LINK"; + groups = "MAC1LINK"; + }; + + pinctrl_mac2link_default: mac2link_default { + function = "MAC2LINK"; + groups = "MAC2LINK"; + }; + + pinctrl_mdio1_default: mdio1_default { + function = "MDIO1"; + groups = "MDIO1"; + }; + + pinctrl_mdio2_default: mdio2_default { + function = "MDIO2"; + groups = "MDIO2"; + }; + + pinctrl_ncts1_default: ncts1_default { + function = "NCTS1"; + groups = "NCTS1"; + }; + + pinctrl_ncts2_default: ncts2_default { + function = "NCTS2"; + groups = "NCTS2"; + }; + + pinctrl_ncts3_default: ncts3_default { + function = "NCTS3"; + groups = "NCTS3"; + }; + + pinctrl_ncts4_default: ncts4_default { + function = "NCTS4"; + groups = "NCTS4"; + }; + + pinctrl_ndcd1_default: ndcd1_default { + function = "NDCD1"; + groups = "NDCD1"; + }; + + pinctrl_ndcd2_default: ndcd2_default { + function = "NDCD2"; + groups = "NDCD2"; + }; + + pinctrl_ndcd3_default: ndcd3_default { + function = "NDCD3"; + groups = "NDCD3"; + }; + + pinctrl_ndcd4_default: ndcd4_default { + function = "NDCD4"; + groups = "NDCD4"; + }; + + pinctrl_ndsr1_default: ndsr1_default { + function = "NDSR1"; + groups = "NDSR1"; + }; + + pinctrl_ndsr2_default: ndsr2_default { + function = "NDSR2"; + groups = "NDSR2"; + }; + + pinctrl_ndsr3_default: ndsr3_default { + function = "NDSR3"; + groups = "NDSR3"; + }; + + pinctrl_ndsr4_default: ndsr4_default { + function = "NDSR4"; + groups = "NDSR4"; + }; + + pinctrl_ndtr1_default: ndtr1_default { + function = "NDTR1"; + groups = "NDTR1"; + }; + + pinctrl_ndtr2_default: ndtr2_default { + function = "NDTR2"; + groups = "NDTR2"; + }; + + pinctrl_ndtr3_default: ndtr3_default { + function = "NDTR3"; + groups = "NDTR3"; + }; + + pinctrl_ndtr4_default: ndtr4_default { + function = "NDTR4"; + groups = "NDTR4"; + }; + + pinctrl_ndts4_default: ndts4_default { + function = "NDTS4"; + groups = "NDTS4"; + }; + + pinctrl_nri1_default: nri1_default { + function = "NRI1"; + groups = "NRI1"; + }; + + pinctrl_nri2_default: nri2_default { + function = "NRI2"; + groups = "NRI2"; + }; + + pinctrl_nri3_default: nri3_default { + function = "NRI3"; + groups = "NRI3"; + }; + + pinctrl_nri4_default: nri4_default { + function = "NRI4"; + groups = "NRI4"; + }; + + pinctrl_nrts1_default: nrts1_default { + function = "NRTS1"; + groups = "NRTS1"; + }; + + pinctrl_nrts2_default: nrts2_default { + function = "NRTS2"; + groups = "NRTS2"; + }; + + pinctrl_nrts3_default: nrts3_default { + function = "NRTS3"; + groups = "NRTS3"; + }; + + pinctrl_oscclk_default: oscclk_default { + function = "OSCCLK"; + groups = "OSCCLK"; + }; + + pinctrl_pwm0_default: pwm0_default { + function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default: pwm1_default { + function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm2_default: pwm2_default { + function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default: pwm3_default { + function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default: pwm4_default { + function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default: pwm5_default { + function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default: pwm6_default { + function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default: pwm7_default { + function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rgmii2_default: rgmii2_default { + function = "RGMII2"; + groups = "RGMII2"; + }; + + pinctrl_rmii1_default: rmii1_default { + function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rmii2_default: rmii2_default { + function = "RMII2"; + groups = "RMII2"; + }; + + pinctrl_rom16_default: rom16_default { + function = "ROM16"; + groups = "ROM16"; + }; + + pinctrl_rom8_default: rom8_default { + function = "ROM8"; + groups = "ROM8"; + }; + + pinctrl_romcs1_default: romcs1_default { + function = "ROMCS1"; + groups = "ROMCS1"; + }; + + pinctrl_romcs2_default: romcs2_default { + function = "ROMCS2"; + groups = "ROMCS2"; + }; + + pinctrl_romcs3_default: romcs3_default { + function = "ROMCS3"; + groups = "ROMCS3"; + }; + + pinctrl_romcs4_default: romcs4_default { + function = "ROMCS4"; + groups = "ROMCS4"; + }; + + pinctrl_rxd1_default: rxd1_default { + function = "RXD1"; + groups = "RXD1"; + }; + + pinctrl_rxd2_default: rxd2_default { + function = "RXD2"; + groups = "RXD2"; + }; + + pinctrl_rxd3_default: rxd3_default { + function = "RXD3"; + groups = "RXD3"; + }; + + pinctrl_rxd4_default: rxd4_default { + function = "RXD4"; + groups = "RXD4"; + }; + + pinctrl_salt1_default: salt1_default { + function = "SALT1"; + groups = "SALT1"; + }; + + pinctrl_salt2_default: salt2_default { + function = "SALT2"; + groups = "SALT2"; + }; + + pinctrl_salt3_default: salt3_default { + function = "SALT3"; + groups = "SALT3"; + }; + + pinctrl_salt4_default: salt4_default { + function = "SALT4"; + groups = "SALT4"; + }; + + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; + + pinctrl_sd2_default: sd2_default { + function = "SD2"; + groups = "SD2"; + }; + + pinctrl_sgpmck_default: sgpmck_default { + function = "SGPMCK"; + groups = "SGPMCK"; + }; + + pinctrl_sgpmi_default: sgpmi_default { + function = "SGPMI"; + groups = "SGPMI"; + }; + + pinctrl_sgpmld_default: sgpmld_default { + function = "SGPMLD"; + groups = "SGPMLD"; + }; + + pinctrl_sgpmo_default: sgpmo_default { + function = "SGPMO"; + groups = "SGPMO"; + }; + + pinctrl_sgpsck_default: sgpsck_default { + function = "SGPSCK"; + groups = "SGPSCK"; + }; + + pinctrl_sgpsi0_default: sgpsi0_default { + function = "SGPSI0"; + groups = "SGPSI0"; + }; + + pinctrl_sgpsi1_default: sgpsi1_default { + function = "SGPSI1"; + groups = "SGPSI1"; + }; + + pinctrl_sgpsld_default: sgpsld_default { + function = "SGPSLD"; + groups = "SGPSLD"; + }; + + pinctrl_sioonctrl_default: sioonctrl_default { + function = "SIOONCTRL"; + groups = "SIOONCTRL"; + }; + + pinctrl_siopbi_default: siopbi_default { + function = "SIOPBI"; + groups = "SIOPBI"; + }; + + pinctrl_siopbo_default: siopbo_default { + function = "SIOPBO"; + groups = "SIOPBO"; + }; + + pinctrl_siopwreq_default: siopwreq_default { + function = "SIOPWREQ"; + groups = "SIOPWREQ"; + }; + + pinctrl_siopwrgd_default: siopwrgd_default { + function = "SIOPWRGD"; + groups = "SIOPWRGD"; + }; + + pinctrl_sios3_default: sios3_default { + function = "SIOS3"; + groups = "SIOS3"; + }; + + pinctrl_sios5_default: sios5_default { + function = "SIOS5"; + groups = "SIOS5"; + }; + + pinctrl_siosci_default: siosci_default { + function = "SIOSCI"; + groups = "SIOSCI"; + }; + + pinctrl_spi1_default: spi1_default { + function = "SPI1"; + groups = "SPI1"; + }; + + pinctrl_spi1debug_default: spi1debug_default { + function = "SPI1DEBUG"; + groups = "SPI1DEBUG"; + }; + + pinctrl_spi1passthru_default: spi1passthru_default { + function = "SPI1PASSTHRU"; + groups = "SPI1PASSTHRU"; + }; + + pinctrl_spics1_default: spics1_default { + function = "SPICS1"; + groups = "SPICS1"; + }; + + pinctrl_timer3_default: timer3_default { + function = "TIMER3"; + groups = "TIMER3"; + }; + + pinctrl_timer4_default: timer4_default { + function = "TIMER4"; + groups = "TIMER4"; + }; + + pinctrl_timer5_default: timer5_default { + function = "TIMER5"; + groups = "TIMER5"; + }; + + pinctrl_timer6_default: timer6_default { + function = "TIMER6"; + groups = "TIMER6"; + }; + + pinctrl_timer7_default: timer7_default { + function = "TIMER7"; + groups = "TIMER7"; + }; + + pinctrl_timer8_default: timer8_default { + function = "TIMER8"; + groups = "TIMER8"; + }; + + pinctrl_txd1_default: txd1_default { + function = "TXD1"; + groups = "TXD1"; + }; + + pinctrl_txd2_default: txd2_default { + function = "TXD2"; + groups = "TXD2"; + }; + + pinctrl_txd3_default: txd3_default { + function = "TXD3"; + groups = "TXD3"; + }; + + pinctrl_txd4_default: txd4_default { + function = "TXD4"; + groups = "TXD4"; + }; + + pinctrl_uart6_default: uart6_default { + function = "UART6"; + groups = "UART6"; + }; + + pinctrl_usbcki_default: usbcki_default { + function = "USBCKI"; + groups = "USBCKI"; + }; + + pinctrl_vgabios_rom_default: vgabios_rom_default { + function = "VGABIOS_ROM"; + groups = "VGABIOS_ROM"; + }; + + pinctrl_vgahs_default: vgahs_default { + function = "VGAHS"; + groups = "VGAHS"; + }; + + pinctrl_vgavs_default: vgavs_default { + function = "VGAVS"; + groups = "VGAVS"; + }; + + pinctrl_vpi18_default: vpi18_default { + function = "VPI18"; + groups = "VPI18"; + }; + + pinctrl_vpi24_default: vpi24_default { + function = "VPI24"; + groups = "VPI24"; + }; + + pinctrl_vpi30_default: vpi30_default { + function = "VPI30"; + groups = "VPI30"; + }; + + pinctrl_vpo12_default: vpo12_default { + function = "VPO12"; + groups = "VPO12"; + }; + + pinctrl_vpo24_default: vpo24_default { + function = "VPO24"; + groups = "VPO24"; + }; + + pinctrl_wdtrst1_default: wdtrst1_default { + function = "WDTRST1"; + groups = "WDTRST1"; + }; + + pinctrl_wdtrst2_default: wdtrst2_default { + function = "WDTRST2"; + groups = "WDTRST2"; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index eab8f549a6fe..5c4ecdba3a6b 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -8,6 +8,29 @@ #size-cells = <1>; interrupt-parent = <&vic>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &vuart; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -145,7 +168,7 @@ clock-frequency = <198000000>; }; - clk_apb: clk_apb@08 { + clk_apb: clk_apb@8 { #clock-cells = <0>; compatible = "aspeed,g5-apb-clock", "fixed-clock"; reg = <0x08>; @@ -164,962 +187,1199 @@ compatible = "aspeed,g5-pinctrl"; aspeed,external-nodes = <&gfx &lhc>; - pinctrl_acpi_default: acpi_default { - function = "ACPI"; - groups = "ACPI"; - }; + }; - pinctrl_adc0_default: adc0_default { - function = "ADC0"; - groups = "ADC0"; - }; + }; - pinctrl_adc1_default: adc1_default { - function = "ADC1"; - groups = "ADC1"; - }; + gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + }; - pinctrl_adc10_default: adc10_default { - function = "ADC10"; - groups = "ADC10"; - }; + adc: adc@1e6e9000 { + compatible = "aspeed,ast2500-adc"; + reg = <0x1e6e9000 0xb0>; + clocks = <&clk_apb>; + #io-channel-cells = <1>; + status = "disabled"; + }; - pinctrl_adc11_default: adc11_default { - function = "ADC11"; - groups = "ADC11"; - }; + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + }; - pinctrl_adc12_default: adc12_default { - function = "ADC12"; - groups = "ADC12"; - }; + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 220>; + interrupt-controller; + }; - pinctrl_adc13_default: adc13_default { - function = "ADC13"; - groups = "ADC13"; - }; + timer: timer@1e782000 { + /* This timer is a Faraday FTTMR010 derivative */ + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + interrupts = <16 17 18 35 36 37 38 39>; + clocks = <&clk_apb>; + clock-names = "PCLK"; + }; - pinctrl_adc14_default: adc14_default { - function = "ADC14"; - groups = "ADC14"; - }; + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x20>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_adc15_default: adc15_default { - function = "ADC15"; - groups = "ADC15"; - }; + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x20>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_adc2_default: adc2_default { - function = "ADC2"; - groups = "ADC2"; - }; + wdt1: watchdog@1e785000 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785000 0x20>; + }; - pinctrl_adc3_default: adc3_default { - function = "ADC3"; - groups = "ADC3"; - }; + wdt2: watchdog@1e785020 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785020 0x20>; + }; - pinctrl_adc4_default: adc4_default { - function = "ADC4"; - groups = "ADC4"; - }; + wdt3: watchdog@1e785040 { + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785040 0x20>; + status = "disabled"; + }; - pinctrl_adc5_default: adc5_default { - function = "ADC5"; - groups = "ADC5"; - }; + lpc: lpc@1e789000 { + compatible = "aspeed,ast2500-lpc", "simple-mfd"; + reg = <0x1e789000 0x1000>; - pinctrl_adc6_default: adc6_default { - function = "ADC6"; - groups = "ADC6"; - }; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e789000 0x1000>; - pinctrl_adc7_default: adc7_default { - function = "ADC7"; - groups = "ADC7"; - }; + lpc_bmc: lpc-bmc@0 { + compatible = "aspeed,ast2500-lpc-bmc"; + reg = <0x0 0x80>; + }; - pinctrl_adc8_default: adc8_default { - function = "ADC8"; - groups = "ADC8"; - }; + lpc_host: lpc-host@80 { + compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; + reg = <0x80 0x1e0>; - pinctrl_adc9_default: adc9_default { - function = "ADC9"; - groups = "ADC9"; - }; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x80 0x1e0>; - pinctrl_bmcint_default: bmcint_default { - function = "BMCINT"; - groups = "BMCINT"; - }; + reg-io-width = <4>; - pinctrl_ddcclk_default: ddcclk_default { - function = "DDCCLK"; - groups = "DDCCLK"; + lhc: lhc@20 { + compatible = "aspeed,ast2500-lhc"; + reg = <0x20 0x24 0x48 0x8>; }; + }; + }; - pinctrl_ddcdat_default: ddcdat_default { - function = "DDCDAT"; - groups = "DDCDAT"; - }; + vuart: serial@1e787000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e787000 0x40>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_espi_default: espi_default { - function = "ESPI"; - groups = "ESPI"; - }; + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x20>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_fwspics1_default: fwspics1_default { - function = "FWSPICS1"; - groups = "FWSPICS1"; - }; + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x20>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_fwspics2_default: fwspics2_default { - function = "FWSPICS2"; - groups = "FWSPICS2"; - }; + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x20>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; - pinctrl_gpid0_default: gpid0_default { - function = "GPID0"; - groups = "GPID0"; - }; + i2c: i2c@1e78a000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e78a000 0x1000>; + }; + }; + }; +}; - pinctrl_gpid2_default: gpid2_default { - function = "GPID2"; - groups = "GPID2"; - }; +&i2c { + i2c_ic: interrupt-controller@0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-i2c-ic"; + reg = <0x0 0x40>; + interrupts = <12>; + interrupt-controller; + }; - pinctrl_gpid4_default: gpid4_default { - function = "GPID4"; - groups = "GPID4"; - }; + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x40 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <0>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; - pinctrl_gpid6_default: gpid6_default { - function = "GPID6"; - groups = "GPID6"; - }; + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x80 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <1>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; - pinctrl_gpie0_default: gpie0_default { - function = "GPIE0"; - groups = "GPIE0"; - }; + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0xc0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <2>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + }; - pinctrl_gpie2_default: gpie2_default { - function = "GPIE2"; - groups = "GPIE2"; - }; + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x100 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <3>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + }; - pinctrl_gpie4_default: gpie4_default { - function = "GPIE4"; - groups = "GPIE4"; - }; + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x140 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <4>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + }; - pinctrl_gpie6_default: gpie6_default { - function = "GPIE6"; - groups = "GPIE6"; - }; + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x180 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <5>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + }; - pinctrl_i2c10_default: i2c10_default { - function = "I2C10"; - groups = "I2C10"; - }; + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x1c0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <6>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + }; - pinctrl_i2c11_default: i2c11_default { - function = "I2C11"; - groups = "I2C11"; - }; + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x300 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <7>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + }; - pinctrl_i2c12_default: i2c12_default { - function = "I2C12"; - groups = "I2C12"; - }; + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x340 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <8>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + }; - pinctrl_i2c13_default: i2c13_default { - function = "I2C13"; - groups = "I2C13"; - }; + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x380 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <9>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + }; - pinctrl_i2c14_default: i2c14_default { - function = "I2C14"; - groups = "I2C14"; - }; + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x3c0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <10>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + }; - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x400 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <11>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + }; - pinctrl_i2c4_default: i2c4_default { - function = "I2C4"; - groups = "I2C4"; - }; + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x440 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <12>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + }; - pinctrl_i2c5_default: i2c5_default { - function = "I2C5"; - groups = "I2C5"; - }; + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x480 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + clocks = <&clk_apb>; + bus-frequency = <100000>; + interrupts = <13>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; +}; - pinctrl_i2c6_default: i2c6_default { - function = "I2C6"; - groups = "I2C6"; - }; +&pinctrl { + pinctrl_acpi_default: acpi_default { + function = "ACPI"; + groups = "ACPI"; + }; - pinctrl_i2c7_default: i2c7_default { - function = "I2C7"; - groups = "I2C7"; - }; + pinctrl_adc0_default: adc0_default { + function = "ADC0"; + groups = "ADC0"; + }; - pinctrl_i2c8_default: i2c8_default { - function = "I2C8"; - groups = "I2C8"; - }; + pinctrl_adc1_default: adc1_default { + function = "ADC1"; + groups = "ADC1"; + }; - pinctrl_i2c9_default: i2c9_default { - function = "I2C9"; - groups = "I2C9"; - }; + pinctrl_adc10_default: adc10_default { + function = "ADC10"; + groups = "ADC10"; + }; - pinctrl_lad0_default: lad0_default { - function = "LAD0"; - groups = "LAD0"; - }; - pinctrl_lad1_default: lad1_default { - function = "LAD1"; - groups = "LAD1"; - }; + pinctrl_adc11_default: adc11_default { + function = "ADC11"; + groups = "ADC11"; + }; - pinctrl_lad2_default: lad2_default { - function = "LAD2"; - groups = "LAD2"; - }; + pinctrl_adc12_default: adc12_default { + function = "ADC12"; + groups = "ADC12"; + }; - pinctrl_lad3_default: lad3_default { - function = "LAD3"; - groups = "LAD3"; - }; + pinctrl_adc13_default: adc13_default { + function = "ADC13"; + groups = "ADC13"; + }; - pinctrl_lclk_default: lclk_default { - function = "LCLK"; - groups = "LCLK"; - }; + pinctrl_adc14_default: adc14_default { + function = "ADC14"; + groups = "ADC14"; + }; - pinctrl_lframe_default: lframe_default { - function = "LFRAME"; - groups = "LFRAME"; - }; + pinctrl_adc15_default: adc15_default { + function = "ADC15"; + groups = "ADC15"; + }; - pinctrl_lpchc_default: lpchc_default { - function = "LPCHC"; - groups = "LPCHC"; - }; + pinctrl_adc2_default: adc2_default { + function = "ADC2"; + groups = "ADC2"; + }; - pinctrl_lpcpd_default: lpcpd_default { - function = "LPCPD"; - groups = "LPCPD"; - }; + pinctrl_adc3_default: adc3_default { + function = "ADC3"; + groups = "ADC3"; + }; - pinctrl_lpcplus_default: lpcplus_default { - function = "LPCPLUS"; - groups = "LPCPLUS"; - }; + pinctrl_adc4_default: adc4_default { + function = "ADC4"; + groups = "ADC4"; + }; - pinctrl_lpcpme_default: lpcpme_default { - function = "LPCPME"; - groups = "LPCPME"; - }; + pinctrl_adc5_default: adc5_default { + function = "ADC5"; + groups = "ADC5"; + }; - pinctrl_lpcrst_default: lpcrst_default { - function = "LPCRST"; - groups = "LPCRST"; - }; + pinctrl_adc6_default: adc6_default { + function = "ADC6"; + groups = "ADC6"; + }; - pinctrl_lpcsmi_default: lpcsmi_default { - function = "LPCSMI"; - groups = "LPCSMI"; - }; + pinctrl_adc7_default: adc7_default { + function = "ADC7"; + groups = "ADC7"; + }; - pinctrl_lsirq_default: lsirq_default { - function = "LSIRQ"; - groups = "LSIRQ"; - }; + pinctrl_adc8_default: adc8_default { + function = "ADC8"; + groups = "ADC8"; + }; - pinctrl_mac1link_default: mac1link_default { - function = "MAC1LINK"; - groups = "MAC1LINK"; - }; + pinctrl_adc9_default: adc9_default { + function = "ADC9"; + groups = "ADC9"; + }; - pinctrl_mac2link_default: mac2link_default { - function = "MAC2LINK"; - groups = "MAC2LINK"; - }; + pinctrl_bmcint_default: bmcint_default { + function = "BMCINT"; + groups = "BMCINT"; + }; - pinctrl_mdio1_default: mdio1_default { - function = "MDIO1"; - groups = "MDIO1"; - }; + pinctrl_ddcclk_default: ddcclk_default { + function = "DDCCLK"; + groups = "DDCCLK"; + }; - pinctrl_mdio2_default: mdio2_default { - function = "MDIO2"; - groups = "MDIO2"; - }; + pinctrl_ddcdat_default: ddcdat_default { + function = "DDCDAT"; + groups = "DDCDAT"; + }; - pinctrl_ncts1_default: ncts1_default { - function = "NCTS1"; - groups = "NCTS1"; - }; + pinctrl_espi_default: espi_default { + function = "ESPI"; + groups = "ESPI"; + }; - pinctrl_ncts2_default: ncts2_default { - function = "NCTS2"; - groups = "NCTS2"; - }; + pinctrl_fwspics1_default: fwspics1_default { + function = "FWSPICS1"; + groups = "FWSPICS1"; + }; - pinctrl_ncts3_default: ncts3_default { - function = "NCTS3"; - groups = "NCTS3"; - }; + pinctrl_fwspics2_default: fwspics2_default { + function = "FWSPICS2"; + groups = "FWSPICS2"; + }; - pinctrl_ncts4_default: ncts4_default { - function = "NCTS4"; - groups = "NCTS4"; - }; + pinctrl_gpid0_default: gpid0_default { + function = "GPID0"; + groups = "GPID0"; + }; - pinctrl_ndcd1_default: ndcd1_default { - function = "NDCD1"; - groups = "NDCD1"; - }; + pinctrl_gpid2_default: gpid2_default { + function = "GPID2"; + groups = "GPID2"; + }; - pinctrl_ndcd2_default: ndcd2_default { - function = "NDCD2"; - groups = "NDCD2"; - }; + pinctrl_gpid4_default: gpid4_default { + function = "GPID4"; + groups = "GPID4"; + }; - pinctrl_ndcd3_default: ndcd3_default { - function = "NDCD3"; - groups = "NDCD3"; - }; + pinctrl_gpid6_default: gpid6_default { + function = "GPID6"; + groups = "GPID6"; + }; - pinctrl_ndcd4_default: ndcd4_default { - function = "NDCD4"; - groups = "NDCD4"; - }; + pinctrl_gpie0_default: gpie0_default { + function = "GPIE0"; + groups = "GPIE0"; + }; - pinctrl_ndsr1_default: ndsr1_default { - function = "NDSR1"; - groups = "NDSR1"; - }; + pinctrl_gpie2_default: gpie2_default { + function = "GPIE2"; + groups = "GPIE2"; + }; - pinctrl_ndsr2_default: ndsr2_default { - function = "NDSR2"; - groups = "NDSR2"; - }; + pinctrl_gpie4_default: gpie4_default { + function = "GPIE4"; + groups = "GPIE4"; + }; - pinctrl_ndsr3_default: ndsr3_default { - function = "NDSR3"; - groups = "NDSR3"; - }; + pinctrl_gpie6_default: gpie6_default { + function = "GPIE6"; + groups = "GPIE6"; + }; - pinctrl_ndsr4_default: ndsr4_default { - function = "NDSR4"; - groups = "NDSR4"; - }; + pinctrl_i2c10_default: i2c10_default { + function = "I2C10"; + groups = "I2C10"; + }; - pinctrl_ndtr1_default: ndtr1_default { - function = "NDTR1"; - groups = "NDTR1"; - }; + pinctrl_i2c11_default: i2c11_default { + function = "I2C11"; + groups = "I2C11"; + }; - pinctrl_ndtr2_default: ndtr2_default { - function = "NDTR2"; - groups = "NDTR2"; - }; + pinctrl_i2c12_default: i2c12_default { + function = "I2C12"; + groups = "I2C12"; + }; - pinctrl_ndtr3_default: ndtr3_default { - function = "NDTR3"; - groups = "NDTR3"; - }; + pinctrl_i2c13_default: i2c13_default { + function = "I2C13"; + groups = "I2C13"; + }; - pinctrl_ndtr4_default: ndtr4_default { - function = "NDTR4"; - groups = "NDTR4"; - }; + pinctrl_i2c14_default: i2c14_default { + function = "I2C14"; + groups = "I2C14"; + }; - pinctrl_nri1_default: nri1_default { - function = "NRI1"; - groups = "NRI1"; - }; + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; - pinctrl_nri2_default: nri2_default { - function = "NRI2"; - groups = "NRI2"; - }; + pinctrl_i2c4_default: i2c4_default { + function = "I2C4"; + groups = "I2C4"; + }; - pinctrl_nri3_default: nri3_default { - function = "NRI3"; - groups = "NRI3"; - }; + pinctrl_i2c5_default: i2c5_default { + function = "I2C5"; + groups = "I2C5"; + }; - pinctrl_nri4_default: nri4_default { - function = "NRI4"; - groups = "NRI4"; - }; + pinctrl_i2c6_default: i2c6_default { + function = "I2C6"; + groups = "I2C6"; + }; - pinctrl_nrts1_default: nrts1_default { - function = "NRTS1"; - groups = "NRTS1"; - }; + pinctrl_i2c7_default: i2c7_default { + function = "I2C7"; + groups = "I2C7"; + }; - pinctrl_nrts2_default: nrts2_default { - function = "NRTS2"; - groups = "NRTS2"; - }; + pinctrl_i2c8_default: i2c8_default { + function = "I2C8"; + groups = "I2C8"; + }; - pinctrl_nrts3_default: nrts3_default { - function = "NRTS3"; - groups = "NRTS3"; - }; + pinctrl_i2c9_default: i2c9_default { + function = "I2C9"; + groups = "I2C9"; + }; - pinctrl_nrts4_default: nrts4_default { - function = "NRTS4"; - groups = "NRTS4"; - }; + pinctrl_lad0_default: lad0_default { + function = "LAD0"; + groups = "LAD0"; + }; - pinctrl_oscclk_default: oscclk_default { - function = "OSCCLK"; - groups = "OSCCLK"; - }; + pinctrl_lad1_default: lad1_default { + function = "LAD1"; + groups = "LAD1"; + }; - pinctrl_pewake_default: pewake_default { - function = "PEWAKE"; - groups = "PEWAKE"; - }; + pinctrl_lad2_default: lad2_default { + function = "LAD2"; + groups = "LAD2"; + }; - pinctrl_pnor_default: pnor_default { - function = "PNOR"; - groups = "PNOR"; - }; + pinctrl_lad3_default: lad3_default { + function = "LAD3"; + groups = "LAD3"; + }; - pinctrl_pwm0_default: pwm0_default { - function = "PWM0"; - groups = "PWM0"; - }; + pinctrl_lclk_default: lclk_default { + function = "LCLK"; + groups = "LCLK"; + }; - pinctrl_pwm1_default: pwm1_default { - function = "PWM1"; - groups = "PWM1"; - }; + pinctrl_lframe_default: lframe_default { + function = "LFRAME"; + groups = "LFRAME"; + }; - pinctrl_pwm2_default: pwm2_default { - function = "PWM2"; - groups = "PWM2"; - }; + pinctrl_lpchc_default: lpchc_default { + function = "LPCHC"; + groups = "LPCHC"; + }; - pinctrl_pwm3_default: pwm3_default { - function = "PWM3"; - groups = "PWM3"; - }; + pinctrl_lpcpd_default: lpcpd_default { + function = "LPCPD"; + groups = "LPCPD"; + }; - pinctrl_pwm4_default: pwm4_default { - function = "PWM4"; - groups = "PWM4"; - }; + pinctrl_lpcplus_default: lpcplus_default { + function = "LPCPLUS"; + groups = "LPCPLUS"; + }; - pinctrl_pwm5_default: pwm5_default { - function = "PWM5"; - groups = "PWM5"; - }; + pinctrl_lpcpme_default: lpcpme_default { + function = "LPCPME"; + groups = "LPCPME"; + }; - pinctrl_pwm6_default: pwm6_default { - function = "PWM6"; - groups = "PWM6"; - }; + pinctrl_lpcrst_default: lpcrst_default { + function = "LPCRST"; + groups = "LPCRST"; + }; - pinctrl_pwm7_default: pwm7_default { - function = "PWM7"; - groups = "PWM7"; - }; + pinctrl_lpcsmi_default: lpcsmi_default { + function = "LPCSMI"; + groups = "LPCSMI"; + }; - pinctrl_rgmii1_default: rgmii1_default { - function = "RGMII1"; - groups = "RGMII1"; - }; + pinctrl_lsirq_default: lsirq_default { + function = "LSIRQ"; + groups = "LSIRQ"; + }; - pinctrl_rgmii2_default: rgmii2_default { - function = "RGMII2"; - groups = "RGMII2"; - }; + pinctrl_mac1link_default: mac1link_default { + function = "MAC1LINK"; + groups = "MAC1LINK"; + }; - pinctrl_rmii1_default: rmii1_default { - function = "RMII1"; - groups = "RMII1"; - }; + pinctrl_mac2link_default: mac2link_default { + function = "MAC2LINK"; + groups = "MAC2LINK"; + }; - pinctrl_rmii2_default: rmii2_default { - function = "RMII2"; - groups = "RMII2"; - }; + pinctrl_mdio1_default: mdio1_default { + function = "MDIO1"; + groups = "MDIO1"; + }; - pinctrl_rxd1_default: rxd1_default { - function = "RXD1"; - groups = "RXD1"; - }; + pinctrl_mdio2_default: mdio2_default { + function = "MDIO2"; + groups = "MDIO2"; + }; - pinctrl_rxd2_default: rxd2_default { - function = "RXD2"; - groups = "RXD2"; - }; + pinctrl_ncts1_default: ncts1_default { + function = "NCTS1"; + groups = "NCTS1"; + }; - pinctrl_rxd3_default: rxd3_default { - function = "RXD3"; - groups = "RXD3"; - }; + pinctrl_ncts2_default: ncts2_default { + function = "NCTS2"; + groups = "NCTS2"; + }; - pinctrl_rxd4_default: rxd4_default { - function = "RXD4"; - groups = "RXD4"; - }; + pinctrl_ncts3_default: ncts3_default { + function = "NCTS3"; + groups = "NCTS3"; + }; - pinctrl_salt1_default: salt1_default { - function = "SALT1"; - groups = "SALT1"; - }; + pinctrl_ncts4_default: ncts4_default { + function = "NCTS4"; + groups = "NCTS4"; + }; - pinctrl_salt10_default: salt10_default { - function = "SALT10"; - groups = "SALT10"; - }; + pinctrl_ndcd1_default: ndcd1_default { + function = "NDCD1"; + groups = "NDCD1"; + }; - pinctrl_salt11_default: salt11_default { - function = "SALT11"; - groups = "SALT11"; - }; + pinctrl_ndcd2_default: ndcd2_default { + function = "NDCD2"; + groups = "NDCD2"; + }; - pinctrl_salt12_default: salt12_default { - function = "SALT12"; - groups = "SALT12"; - }; + pinctrl_ndcd3_default: ndcd3_default { + function = "NDCD3"; + groups = "NDCD3"; + }; - pinctrl_salt13_default: salt13_default { - function = "SALT13"; - groups = "SALT13"; - }; + pinctrl_ndcd4_default: ndcd4_default { + function = "NDCD4"; + groups = "NDCD4"; + }; - pinctrl_salt14_default: salt14_default { - function = "SALT14"; - groups = "SALT14"; - }; + pinctrl_ndsr1_default: ndsr1_default { + function = "NDSR1"; + groups = "NDSR1"; + }; - pinctrl_salt2_default: salt2_default { - function = "SALT2"; - groups = "SALT2"; - }; + pinctrl_ndsr2_default: ndsr2_default { + function = "NDSR2"; + groups = "NDSR2"; + }; - pinctrl_salt3_default: salt3_default { - function = "SALT3"; - groups = "SALT3"; - }; + pinctrl_ndsr3_default: ndsr3_default { + function = "NDSR3"; + groups = "NDSR3"; + }; - pinctrl_salt4_default: salt4_default { - function = "SALT4"; - groups = "SALT4"; - }; + pinctrl_ndsr4_default: ndsr4_default { + function = "NDSR4"; + groups = "NDSR4"; + }; - pinctrl_salt5_default: salt5_default { - function = "SALT5"; - groups = "SALT5"; - }; + pinctrl_ndtr1_default: ndtr1_default { + function = "NDTR1"; + groups = "NDTR1"; + }; - pinctrl_salt6_default: salt6_default { - function = "SALT6"; - groups = "SALT6"; - }; + pinctrl_ndtr2_default: ndtr2_default { + function = "NDTR2"; + groups = "NDTR2"; + }; - pinctrl_salt7_default: salt7_default { - function = "SALT7"; - groups = "SALT7"; - }; + pinctrl_ndtr3_default: ndtr3_default { + function = "NDTR3"; + groups = "NDTR3"; + }; - pinctrl_salt8_default: salt8_default { - function = "SALT8"; - groups = "SALT8"; - }; + pinctrl_ndtr4_default: ndtr4_default { + function = "NDTR4"; + groups = "NDTR4"; + }; - pinctrl_salt9_default: salt9_default { - function = "SALT9"; - groups = "SALT9"; - }; + pinctrl_nri1_default: nri1_default { + function = "NRI1"; + groups = "NRI1"; + }; - pinctrl_scl1_default: scl1_default { - function = "SCL1"; - groups = "SCL1"; - }; + pinctrl_nri2_default: nri2_default { + function = "NRI2"; + groups = "NRI2"; + }; - pinctrl_scl2_default: scl2_default { - function = "SCL2"; - groups = "SCL2"; - }; + pinctrl_nri3_default: nri3_default { + function = "NRI3"; + groups = "NRI3"; + }; - pinctrl_sd1_default: sd1_default { - function = "SD1"; - groups = "SD1"; - }; + pinctrl_nri4_default: nri4_default { + function = "NRI4"; + groups = "NRI4"; + }; - pinctrl_sd2_default: sd2_default { - function = "SD2"; - groups = "SD2"; - }; + pinctrl_nrts1_default: nrts1_default { + function = "NRTS1"; + groups = "NRTS1"; + }; - pinctrl_sda1_default: sda1_default { - function = "SDA1"; - groups = "SDA1"; - }; + pinctrl_nrts2_default: nrts2_default { + function = "NRTS2"; + groups = "NRTS2"; + }; - pinctrl_sda2_default: sda2_default { - function = "SDA2"; - groups = "SDA2"; - }; + pinctrl_nrts3_default: nrts3_default { + function = "NRTS3"; + groups = "NRTS3"; + }; - pinctrl_sgps1_default: sgps1_default { - function = "SGPS1"; - groups = "SGPS1"; - }; + pinctrl_nrts4_default: nrts4_default { + function = "NRTS4"; + groups = "NRTS4"; + }; - pinctrl_sgps2_default: sgps2_default { - function = "SGPS2"; - groups = "SGPS2"; - }; + pinctrl_oscclk_default: oscclk_default { + function = "OSCCLK"; + groups = "OSCCLK"; + }; - pinctrl_sioonctrl_default: sioonctrl_default { - function = "SIOONCTRL"; - groups = "SIOONCTRL"; - }; + pinctrl_pewake_default: pewake_default { + function = "PEWAKE"; + groups = "PEWAKE"; + }; - pinctrl_siopbi_default: siopbi_default { - function = "SIOPBI"; - groups = "SIOPBI"; - }; + pinctrl_pnor_default: pnor_default { + function = "PNOR"; + groups = "PNOR"; + }; - pinctrl_siopbo_default: siopbo_default { - function = "SIOPBO"; - groups = "SIOPBO"; - }; + pinctrl_pwm0_default: pwm0_default { + function = "PWM0"; + groups = "PWM0"; + }; - pinctrl_siopwreq_default: siopwreq_default { - function = "SIOPWREQ"; - groups = "SIOPWREQ"; - }; + pinctrl_pwm1_default: pwm1_default { + function = "PWM1"; + groups = "PWM1"; + }; - pinctrl_siopwrgd_default: siopwrgd_default { - function = "SIOPWRGD"; - groups = "SIOPWRGD"; - }; + pinctrl_pwm2_default: pwm2_default { + function = "PWM2"; + groups = "PWM2"; + }; - pinctrl_sios3_default: sios3_default { - function = "SIOS3"; - groups = "SIOS3"; - }; + pinctrl_pwm3_default: pwm3_default { + function = "PWM3"; + groups = "PWM3"; + }; - pinctrl_sios5_default: sios5_default { - function = "SIOS5"; - groups = "SIOS5"; - }; + pinctrl_pwm4_default: pwm4_default { + function = "PWM4"; + groups = "PWM4"; + }; - pinctrl_siosci_default: siosci_default { - function = "SIOSCI"; - groups = "SIOSCI"; - }; + pinctrl_pwm5_default: pwm5_default { + function = "PWM5"; + groups = "PWM5"; + }; - pinctrl_spi1_default: spi1_default { - function = "SPI1"; - groups = "SPI1"; - }; + pinctrl_pwm6_default: pwm6_default { + function = "PWM6"; + groups = "PWM6"; + }; - pinctrl_spi1cs1_default: spi1cs1_default { - function = "SPI1CS1"; - groups = "SPI1CS1"; - }; + pinctrl_pwm7_default: pwm7_default { + function = "PWM7"; + groups = "PWM7"; + }; - pinctrl_spi1debug_default: spi1debug_default { - function = "SPI1DEBUG"; - groups = "SPI1DEBUG"; - }; + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; + }; - pinctrl_spi1passthru_default: spi1passthru_default { - function = "SPI1PASSTHRU"; - groups = "SPI1PASSTHRU"; - }; + pinctrl_rgmii2_default: rgmii2_default { + function = "RGMII2"; + groups = "RGMII2"; + }; - pinctrl_spi2ck_default: spi2ck_default { - function = "SPI2CK"; - groups = "SPI2CK"; - }; + pinctrl_rmii1_default: rmii1_default { + function = "RMII1"; + groups = "RMII1"; + }; - pinctrl_spi2cs0_default: spi2cs0_default { - function = "SPI2CS0"; - groups = "SPI2CS0"; - }; + pinctrl_rmii2_default: rmii2_default { + function = "RMII2"; + groups = "RMII2"; + }; - pinctrl_spi2cs1_default: spi2cs1_default { - function = "SPI2CS1"; - groups = "SPI2CS1"; - }; + pinctrl_rxd1_default: rxd1_default { + function = "RXD1"; + groups = "RXD1"; + }; - pinctrl_spi2miso_default: spi2miso_default { - function = "SPI2MISO"; - groups = "SPI2MISO"; - }; + pinctrl_rxd2_default: rxd2_default { + function = "RXD2"; + groups = "RXD2"; + }; - pinctrl_spi2mosi_default: spi2mosi_default { - function = "SPI2MOSI"; - groups = "SPI2MOSI"; - }; + pinctrl_rxd3_default: rxd3_default { + function = "RXD3"; + groups = "RXD3"; + }; - pinctrl_timer3_default: timer3_default { - function = "TIMER3"; - groups = "TIMER3"; - }; + pinctrl_rxd4_default: rxd4_default { + function = "RXD4"; + groups = "RXD4"; + }; - pinctrl_timer4_default: timer4_default { - function = "TIMER4"; - groups = "TIMER4"; - }; + pinctrl_salt1_default: salt1_default { + function = "SALT1"; + groups = "SALT1"; + }; - pinctrl_timer5_default: timer5_default { - function = "TIMER5"; - groups = "TIMER5"; - }; + pinctrl_salt10_default: salt10_default { + function = "SALT10"; + groups = "SALT10"; + }; - pinctrl_timer6_default: timer6_default { - function = "TIMER6"; - groups = "TIMER6"; - }; + pinctrl_salt11_default: salt11_default { + function = "SALT11"; + groups = "SALT11"; + }; - pinctrl_timer7_default: timer7_default { - function = "TIMER7"; - groups = "TIMER7"; - }; + pinctrl_salt12_default: salt12_default { + function = "SALT12"; + groups = "SALT12"; + }; - pinctrl_timer8_default: timer8_default { - function = "TIMER8"; - groups = "TIMER8"; - }; + pinctrl_salt13_default: salt13_default { + function = "SALT13"; + groups = "SALT13"; + }; - pinctrl_txd1_default: txd1_default { - function = "TXD1"; - groups = "TXD1"; - }; + pinctrl_salt14_default: salt14_default { + function = "SALT14"; + groups = "SALT14"; + }; - pinctrl_txd2_default: txd2_default { - function = "TXD2"; - groups = "TXD2"; - }; + pinctrl_salt2_default: salt2_default { + function = "SALT2"; + groups = "SALT2"; + }; - pinctrl_txd3_default: txd3_default { - function = "TXD3"; - groups = "TXD3"; - }; + pinctrl_salt3_default: salt3_default { + function = "SALT3"; + groups = "SALT3"; + }; - pinctrl_txd4_default: txd4_default { - function = "TXD4"; - groups = "TXD4"; - }; + pinctrl_salt4_default: salt4_default { + function = "SALT4"; + groups = "SALT4"; + }; - pinctrl_uart6_default: uart6_default { - function = "UART6"; - groups = "UART6"; - }; + pinctrl_salt5_default: salt5_default { + function = "SALT5"; + groups = "SALT5"; + }; - pinctrl_usbcki_default: usbcki_default { - function = "USBCKI"; - groups = "USBCKI"; - }; + pinctrl_salt6_default: salt6_default { + function = "SALT6"; + groups = "SALT6"; + }; - pinctrl_vgabiosrom_default: vgabiosrom_default { - function = "VGABIOSROM"; - groups = "VGABIOSROM"; - }; + pinctrl_salt7_default: salt7_default { + function = "SALT7"; + groups = "SALT7"; + }; - pinctrl_vgahs_default: vgahs_default { - function = "VGAHS"; - groups = "VGAHS"; - }; + pinctrl_salt8_default: salt8_default { + function = "SALT8"; + groups = "SALT8"; + }; - pinctrl_vgavs_default: vgavs_default { - function = "VGAVS"; - groups = "VGAVS"; - }; + pinctrl_salt9_default: salt9_default { + function = "SALT9"; + groups = "SALT9"; + }; - pinctrl_vpi24_default: vpi24_default { - function = "VPI24"; - groups = "VPI24"; - }; + pinctrl_scl1_default: scl1_default { + function = "SCL1"; + groups = "SCL1"; + }; - pinctrl_vpo_default: vpo_default { - function = "VPO"; - groups = "VPO"; - }; + pinctrl_scl2_default: scl2_default { + function = "SCL2"; + groups = "SCL2"; + }; - pinctrl_wdtrst1_default: wdtrst1_default { - function = "WDTRST1"; - groups = "WDTRST1"; - }; + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; - pinctrl_wdtrst2_default: wdtrst2_default { - function = "WDTRST2"; - groups = "WDTRST2"; - }; + pinctrl_sd2_default: sd2_default { + function = "SD2"; + groups = "SD2"; + }; - }; + pinctrl_sda1_default: sda1_default { + function = "SDA1"; + groups = "SDA1"; + }; - }; + pinctrl_sda2_default: sda2_default { + function = "SDA2"; + groups = "SDA2"; + }; - gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; - reg-io-width = <4>; - }; + pinctrl_sgps1_default: sgps1_default { + function = "SGPS1"; + groups = "SGPS1"; + }; - sram@1e720000 { - compatible = "mmio-sram"; - reg = <0x1e720000 0x9000>; // 36K - }; + pinctrl_sgps2_default: sgps2_default { + function = "SGPS2"; + groups = "SGPS2"; + }; - gpio: gpio@1e780000 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2500-gpio"; - reg = <0x1e780000 0x1000>; - interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 220>; - interrupt-controller; - }; + pinctrl_sioonctrl_default: sioonctrl_default { + function = "SIOONCTRL"; + groups = "SIOONCTRL"; + }; - timer: timer@1e782000 { - /* This timer is a Faraday FTTMR010 derivative */ - compatible = "aspeed,ast2400-timer"; - reg = <0x1e782000 0x90>; - interrupts = <16 17 18 35 36 37 38 39>; - clocks = <&clk_apb>; - clock-names = "PCLK"; - }; + pinctrl_siopbi_default: siopbi_default { + function = "SIOPBI"; + groups = "SIOPBI"; + }; + pinctrl_siopbo_default: siopbo_default { + function = "SIOPBO"; + groups = "SIOPBO"; + }; - wdt1: wdt@1e785000 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785000 0x20>; - interrupts = <27>; - }; + pinctrl_siopwreq_default: siopwreq_default { + function = "SIOPWREQ"; + groups = "SIOPWREQ"; + }; - wdt2: wdt@1e785020 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785020 0x20>; - interrupts = <27>; - status = "disabled"; - }; + pinctrl_siopwrgd_default: siopwrgd_default { + function = "SIOPWRGD"; + groups = "SIOPWRGD"; + }; - wdt3: wdt@1e785040 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785040 0x20>; - status = "disabled"; - }; + pinctrl_sios3_default: sios3_default { + function = "SIOS3"; + groups = "SIOS3"; + }; - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x1000>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_sios5_default: sios5_default { + function = "SIOS5"; + groups = "SIOS5"; + }; - lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc", "simple-mfd"; - reg = <0x1e789000 0x1000>; + pinctrl_siosci_default: siosci_default { + function = "SIOSCI"; + groups = "SIOSCI"; + }; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e789000 0x1000>; + pinctrl_spi1_default: spi1_default { + function = "SPI1"; + groups = "SPI1"; + }; - lpc_bmc: lpc-bmc@0 { - compatible = "aspeed,ast2500-lpc-bmc"; - reg = <0x0 0x80>; - }; + pinctrl_spi1cs1_default: spi1cs1_default { + function = "SPI1CS1"; + groups = "SPI1CS1"; + }; - lpc_host: lpc-host@80 { - compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; - reg = <0x80 0x1e0>; + pinctrl_spi1debug_default: spi1debug_default { + function = "SPI1DEBUG"; + groups = "SPI1DEBUG"; + }; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x80 0x1e0>; + pinctrl_spi1passthru_default: spi1passthru_default { + function = "SPI1PASSTHRU"; + groups = "SPI1PASSTHRU"; + }; - reg-io-width = <4>; + pinctrl_spi2ck_default: spi2ck_default { + function = "SPI2CK"; + groups = "SPI2CK"; + }; - lhc: lhc@20 { - compatible = "aspeed,ast2500-lhc"; - reg = <0x20 0x24 0x48 0x8>; - }; - }; - }; + pinctrl_spi2cs0_default: spi2cs0_default { + function = "SPI2CS0"; + groups = "SPI2CS0"; + }; - uart2: serial@1e78d000 { - compatible = "ns16550a"; - reg = <0x1e78d000 0x1000>; - reg-shift = <2>; - interrupts = <32>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_spi2cs1_default: spi2cs1_default { + function = "SPI2CS1"; + groups = "SPI2CS1"; + }; - uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x1000>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_spi2miso_default: spi2miso_default { + function = "SPI2MISO"; + groups = "SPI2MISO"; + }; - uart4: serial@1e78f000 { - compatible = "ns16550a"; - reg = <0x1e78f000 0x1000>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_spi2mosi_default: spi2mosi_default { + function = "SPI2MOSI"; + groups = "SPI2MOSI"; + }; - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - current-speed = <38400>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_timer3_default: timer3_default { + function = "TIMER3"; + groups = "TIMER3"; + }; - uart6: serial@1e787000 { - compatible = "ns16550a"; - reg = <0x1e787000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_timer4_default: timer4_default { + function = "TIMER4"; + groups = "TIMER4"; + }; - adc: adc@1e6e9000 { - compatible = "aspeed,ast2500-adc"; - reg = <0x1e6e9000 0xb0>; - clocks = <&clk_apb>; - #io-channel-cells = <1>; - status = "disabled"; - }; - }; + pinctrl_timer5_default: timer5_default { + function = "TIMER5"; + groups = "TIMER5"; + }; + + pinctrl_timer6_default: timer6_default { + function = "TIMER6"; + groups = "TIMER6"; + }; + + pinctrl_timer7_default: timer7_default { + function = "TIMER7"; + groups = "TIMER7"; + }; + + pinctrl_timer8_default: timer8_default { + function = "TIMER8"; + groups = "TIMER8"; + }; + + pinctrl_txd1_default: txd1_default { + function = "TXD1"; + groups = "TXD1"; + }; + + pinctrl_txd2_default: txd2_default { + function = "TXD2"; + groups = "TXD2"; + }; + + pinctrl_txd3_default: txd3_default { + function = "TXD3"; + groups = "TXD3"; + }; + + pinctrl_txd4_default: txd4_default { + function = "TXD4"; + groups = "TXD4"; + }; + + pinctrl_uart6_default: uart6_default { + function = "UART6"; + groups = "UART6"; + }; + + pinctrl_usbcki_default: usbcki_default { + function = "USBCKI"; + groups = "USBCKI"; + }; + + pinctrl_vgabiosrom_default: vgabiosrom_default { + function = "VGABIOSROM"; + groups = "VGABIOSROM"; + }; + + pinctrl_vgahs_default: vgahs_default { + function = "VGAHS"; + groups = "VGAHS"; + }; + + pinctrl_vgavs_default: vgavs_default { + function = "VGAVS"; + groups = "VGAVS"; + }; + + pinctrl_vpi24_default: vpi24_default { + function = "VPI24"; + groups = "VPI24"; + }; + + pinctrl_vpo_default: vpo_default { + function = "VPO"; + groups = "VPO"; + }; + + pinctrl_wdtrst1_default: wdtrst1_default { + function = "WDTRST1"; + groups = "WDTRST1"; + }; + + pinctrl_wdtrst2_default: wdtrst2_default { + function = "WDTRST2"; + groups = "WDTRST2"; }; }; diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts index 4da011a7a698..1c86537a42a0 100644 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ b/arch/arm/boot/dts/at91-ariag25.dts @@ -147,12 +147,12 @@ }; }; - usb0: ohci@00600000 { + usb0: ohci@600000 { status = "okay"; num-ports = <3>; }; - usb1: ehci@00700000 { + usb1: ehci@700000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91-ariettag25.dts b/arch/arm/boot/dts/at91-ariettag25.dts index 21c5b56c92e0..f877f3430bcc 100644 --- a/arch/arm/boot/dts/at91-ariettag25.dts +++ b/arch/arm/boot/dts/at91-ariettag25.dts @@ -59,12 +59,12 @@ }; }; - usb0: ohci@00600000 { + usb0: ohci@600000 { status = "okay"; num-ports = <3>; }; - usb1: ehci@00700000 { + usb1: ehci@700000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts index 27ebb0f722fd..c452654b843a 100644 --- a/arch/arm/boot/dts/at91-cosino_mega2560.dts +++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts @@ -62,7 +62,7 @@ }; }; - usb0: ohci@00600000 { + usb0: ohci@600000 { status = "okay"; num-ports = <3>; atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */ @@ -71,7 +71,7 @@ >; }; - usb1: ehci@00700000 { + usb1: ehci@700000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91-kizbox2.dts b/arch/arm/boot/dts/at91-kizbox2.dts index 4372c0287c1c..ec6c28c521a5 100644 --- a/arch/arm/boot/dts/at91-kizbox2.dts +++ b/arch/arm/boot/dts/at91-kizbox2.dts @@ -133,11 +133,11 @@ }; }; - usb1: ohci@00600000 { + usb1: ohci@600000 { status = "okay"; }; - usb2: ehci@00700000 { + usb2: ehci@700000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-kizboxmini.dts b/arch/arm/boot/dts/at91-kizboxmini.dts index 33238fcb6d0b..fe1bc0a59a98 100644 --- a/arch/arm/boot/dts/at91-kizboxmini.dts +++ b/arch/arm/boot/dts/at91-kizboxmini.dts @@ -59,12 +59,12 @@ }; }; - usb0: ohci@00600000 { + usb0: ohci@600000 { num-ports = <1>; status = "okay"; }; - usb1: ehci@00700000 { + usb1: ehci@700000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 60cb084a8d92..6d87b4eb6c41 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -53,19 +53,27 @@ model = "Atmel SAMA5D27 SOM1 EK"; compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + aliases { + serial0 = &uart1; /* DBGU */ + serial1 = &uart4; /* mikro BUS 1 */ + serial2 = &uart2; /* mikro BUS 2 */ + i2c1 = &i2c1; + i2c2 = &i2c2; + }; + chosen { stdout-path = "serial0:115200n8"; }; ahb { - usb0: gadget@00300000 { + usb0: gadget@300000 { atmel,vbus-gpio = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00400000 { + usb1: ohci@400000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioA PIN_PD20 GPIO_ACTIVE_HIGH */ &pioA PIN_PA27 GPIO_ACTIVE_HIGH @@ -76,7 +84,7 @@ status = "okay"; }; - usb2: ehci@00500000 { + usb2: ehci@500000 { status = "okay"; }; @@ -128,12 +136,14 @@ }; pwm0: pwm@f802c000 { - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_pwm &pinctrl_mikrobus2_pwm>; + status = "disabled"; /* Conflict with leds. */ }; flx1: flexcom@f8038000 { atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; - status = "disabled"; + status = "okay"; i2c2: i2c@600 { compatible = "atmel,sama5d2-i2c"; @@ -147,7 +157,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_i2c>; atmel,fifo-size = <16>; - status = "disabled"; + status = "okay"; }; }; @@ -165,17 +175,12 @@ status = "okay"; }; - can0: can@f8054000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_default>; - }; - uart3: serial@fc008000 { atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_default>; - status = "disabled"; + status = "disabled"; /* Conflict with isc. */ }; uart4: serial@fc00c000 { @@ -199,7 +204,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; atmel,fifo-size = <32>; - status = "disabled"; + status = "disabled"; /* Conflict with isc. */ }; spi2: spi@400 { @@ -211,7 +216,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; atmel,fifo-size = <16>; - status = "disabled"; + status = "disabled"; /* Conflict with isc. */ }; }; @@ -228,7 +233,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; atmel,fifo-size = <32>; - status = "disabled"; + status = "disabled"; /* Conflict with spi3 and i2c3. */ }; spi3: spi@400 { @@ -240,7 +245,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; atmel,fifo-size = <16>; - status = "okay"; + status = "okay"; /* Conflict with uart6 and i2c3. */ }; i2c3: i2c@600 { @@ -255,7 +260,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; atmel,fifo-size = <16>; - status = "disabled"; + status = "disabled"; /* Conflict with uart6 and spi3. */ }; }; @@ -268,12 +273,6 @@ pinctrl@fc038000 { - pinctrl_can0_default: can0_default { - pinmux = <PIN_PC10__CANTX0>, - <PIN_PC11__CANRX0>; - bias-disable; - }; - pinctrl_can1_default: can1_default { pinmux = <PIN_PC26__CANTX1>, <PIN_PC27__CANRX1>; @@ -350,7 +349,7 @@ <PIN_PA7__SDMMC0_DAT5>, <PIN_PA8__SDMMC0_DAT6>, <PIN_PA9__SDMMC0_DAT7>; - bias-pull-up; + bias-disable; }; ck_cd_vddsel { @@ -368,7 +367,7 @@ <PIN_PA19__SDMMC1_DAT1>, <PIN_PA20__SDMMC1_DAT2>, <PIN_PA21__SDMMC1_DAT3>; - bias-pull-up; + bias-disable; }; conf-ck_cd { @@ -512,6 +511,7 @@ label = "USER"; gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; linux,code = <0x104>; + wakeup-source; }; }; @@ -519,7 +519,7 @@ compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; + status = "okay"; /* Conflict with pwm0. */ red { label = "red"; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index cbc26001247b..56de21de2779 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -67,14 +67,14 @@ }; ahb { - usb0: gadget@00300000 { + usb0: gadget@300000 { atmel,vbus-gpio = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00400000 { + usb1: ohci@400000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioA PIN_PB9 GPIO_ACTIVE_HIGH */ &pioA PIN_PB10 GPIO_ACTIVE_HIGH @@ -85,7 +85,7 @@ status = "okay"; }; - usb2: ehci@00500000 { + usb2: ehci@500000 { status = "okay"; }; @@ -103,6 +103,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc1_default>; status = "okay"; /* conflict with qspi0 */ + vqmmc-supply = <&vdd_3v3_reg>; + vmmc-supply = <&vdd_3v3_reg>; }; apb { @@ -160,14 +162,6 @@ compatible = "active-semi,act8945a"; reg = <0x5b>; active-semi,vsel-high; - active-semi,chglev-gpios = <&pioA PIN_PA12 GPIO_ACTIVE_HIGH>; - active-semi,lbo-gpios = <&pioA PIN_PC8 GPIO_ACTIVE_LOW>; - active-semi,irq_gpios = <&pioA PIN_PB13 GPIO_ACTIVE_LOW>; - active-semi,input-voltage-threshold-microvolt = <6600>; - active-semi,precondition-timeout = <40>; - active-semi,total-timeout = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; status = "okay"; regulators { @@ -220,11 +214,28 @@ regulator-always-on; }; }; + + charger { + compatible = "active-semi,act8945a-charger"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; + interrupt-parent = <&pioA>; + interrupts = <PIN_PB13 GPIO_ACTIVE_LOW>; + + active-semi,chglev-gpios = <&pioA PIN_PA12 GPIO_ACTIVE_HIGH>; + active-semi,lbo-gpios = <&pioA PIN_PC8 GPIO_ACTIVE_LOW>; + active-semi,input-voltage-threshold-microvolt = <6600>; + active-semi,precondition-timeout = <40>; + active-semi,total-timeout = <3>; + status = "okay"; + }; }; }; pwm0: pwm@f802c000 { - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm2_default>; + status = "disabled"; /* conflict with leds */ }; flx0: flexcom@f8034000 { @@ -449,7 +460,7 @@ <PIN_PA7__SDMMC0_DAT5>, <PIN_PA8__SDMMC0_DAT6>, <PIN_PA9__SDMMC0_DAT7>; - bias-pull-up; + bias-disable; }; ck_cd_rstn_vddsel { @@ -468,7 +479,7 @@ <PIN_PA19__SDMMC1_DAT1>, <PIN_PA20__SDMMC1_DAT2>, <PIN_PA21__SDMMC1_DAT3>; - bias-pull-up; + bias-disable; }; conf-ck_cd { @@ -508,6 +519,11 @@ bias-disable; }; + pinctrl_pwm0_pwm2_default: pwm0_pwm2_default { + pinmux = <PIN_PB5__PWMH2>, + <PIN_PB6__PWML2>; + bias-pull-up; + }; }; classd: classd@fc048000 { @@ -536,6 +552,7 @@ label = "PB_USER"; gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>; linux,code = <0x104>; + wakeup-source; }; }; @@ -543,7 +560,7 @@ compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; + status = "okay"; /* conflict with pwm0 */ red { label = "red"; diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index 3af088d2cba7..40879aded680 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -235,14 +235,14 @@ }; }; - usb0: gadget@00500000 { + usb0: gadget@500000 { atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00600000 { + usb1: ohci@600000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 3 GPIO_ACTIVE_LOW @@ -251,7 +251,7 @@ status = "okay"; }; - usb2: ehci@00700000 { + usb2: ehci@700000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts index 84be29f38dae..fe05aaa7ac87 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts @@ -21,14 +21,14 @@ }; ahb { - usb0: gadget@00400000 { + usb0: gadget@400000 { atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00500000 { + usb1: ohci@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_LOW @@ -37,7 +37,7 @@ status = "okay"; }; - usb2: ehci@00600000 { + usb2: ehci@600000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index cf712444b2c2..29ab17a97f9a 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -170,14 +170,14 @@ }; }; - usb0: gadget@00400000 { + usb0: gadget@400000 { atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00500000 { + usb1: ohci@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_HIGH @@ -186,7 +186,7 @@ status = "okay"; }; - usb2: ehci@00600000 { + usb2: ehci@600000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index bae5248f126e..5b7ee92e32a7 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -216,14 +216,14 @@ }; }; - usb0: gadget@00400000 { + usb0: gadget@400000 { atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00500000 { + usb1: ohci@500000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */ &pioE 11 GPIO_ACTIVE_LOW @@ -232,7 +232,7 @@ status = "okay"; }; - usb2: ehci@00600000 { + usb2: ehci@600000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts index e0c0b2897a49..9f6005708ea8 100644 --- a/arch/arm/boot/dts/at91-vinco.dts +++ b/arch/arm/boot/dts/at91-vinco.dts @@ -180,14 +180,14 @@ }; }; - usb0: gadget@00400000 { + usb0: gadget@400000 { atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "disable"; }; - usb1: ohci@00500000 { + usb1: ohci@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_LOW @@ -196,7 +196,7 @@ status = "disable"; }; - usb2: ehci@00600000 { + usb2: ehci@600000 { /* 4G Modem */ status = "okay"; }; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index f057e0b15a6f..da622bf45b4a 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -66,7 +66,7 @@ }; }; - sram: sram@00200000 { + sram: sram@200000 { compatible = "mmio-sram"; reg = <0x00200000 0x4000>; }; @@ -938,7 +938,7 @@ status = "disabled"; }; - usb0: ohci@00300000 { + usb0: ohci@300000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00300000 0x100000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index f90e1c2d3caa..33192d0cefee 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -78,7 +78,7 @@ }; }; - usb0: ohci@00300000 { + usb0: ohci@300000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 6582f3cca929..bc655e7332d6 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -69,7 +69,7 @@ }; }; - sram0: sram@002ff000 { + sram0: sram@2ff000 { compatible = "mmio-sram"; reg = <0x002ff000 0x2000>; }; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index a05353f96151..66876019101d 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -60,7 +60,7 @@ }; }; - sram: sram@00300000 { + sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x28000>; }; @@ -71,7 +71,7 @@ #size-cells = <1>; ranges; - usb0: ohci@00500000 { + usb0: ohci@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts index 157e1493e6eb..960d6940ebf6 100644 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ b/arch/arm/boot/dts/at91sam9261ek.dts @@ -32,7 +32,7 @@ }; ahb { - usb0: ohci@00500000 { + usb0: ohci@500000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index ed4b564f8de5..e54f14d36b6f 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -62,12 +62,12 @@ }; }; - sram0: sram@00300000 { + sram0: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x14000>; }; - sram1: sram@00500000 { + sram1: sram@500000 { compatible = "mmio-sram"; reg = <0x00500000 0x4000>; }; @@ -1010,7 +1010,7 @@ status = "disabled"; }; - usb0: ohci@00a00000 { + usb0: ohci@a00000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00a00000 0x100000>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 10a0925da10e..5a2e1af793f5 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -191,7 +191,7 @@ }; }; - usb0: ohci@00a00000 { + usb0: ohci@a00000 { num-ports = <2>; status = "okay"; atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index f59301618163..90705ee6008b 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -16,11 +16,11 @@ reg = <0x20000000 0x08000000>; }; - sram0: sram@002ff000 { + sram0: sram@2ff000 { status = "disabled"; }; - sram1: sram@002fc000 { + sram1: sram@2fc000 { compatible = "mmio-sram"; reg = <0x002fc000 0x8000>; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 64fa3f9a39d3..2b127ca7aaa0 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -74,7 +74,7 @@ }; }; - sram: sram@00300000 { + sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x10000>; }; @@ -1313,7 +1313,7 @@ status = "disabled"; }; - usb0: ohci@00700000 { + usb0: ohci@700000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; @@ -1322,7 +1322,7 @@ status = "disabled"; }; - usb1: ehci@00800000 { + usb1: ehci@800000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 94c52c555f83..e922552a04cb 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -290,14 +290,14 @@ }; }; - usb0: ohci@00700000 { + usb0: ohci@700000 { status = "okay"; num-ports = <2>; atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW &pioD 3 GPIO_ACTIVE_LOW>; }; - usb1: ehci@00800000 { + usb1: ehci@800000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 06516d02d351..e0ac824e0785 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -64,7 +64,7 @@ }; }; - sram: sram@00300000 { + sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x8000>; }; @@ -1018,7 +1018,7 @@ }; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x00100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 5bea8c59b115..212562aedf5e 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -169,7 +169,7 @@ }; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { num-ports = <1>; atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 7768342a6638..52f0e9ef8f67 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -70,7 +70,7 @@ }; }; - sram: sram@00300000 { + sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x10000>; }; @@ -81,7 +81,7 @@ #size-cells = <1>; ranges; - fb0: fb@00500000 { + fb0: fb@500000 { compatible = "atmel,at91sam9rl-lcdc"; reg = <0x00500000 0x1000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index 9047c168298a..ea6ed98960c9 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -32,7 +32,7 @@ }; ahb { - fb0: fb@00500000 { + fb0: fb@500000 { display = <&display0>; status = "okay"; diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts index 494864836e83..f705a3165656 100644 --- a/arch/arm/boot/dts/at91sam9x25ek.dts +++ b/arch/arm/boot/dts/at91sam9x25ek.dts @@ -16,6 +16,10 @@ ahb { apb { + can1: can@f8004000 { + status = "okay"; + }; + macb0: ethernet@f802c000 { phy-mode = "rmii"; status = "okay"; @@ -25,6 +29,12 @@ phy-mode = "rmii"; status = "okay"; }; + + pwm0: pwm@f8034000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm0_1>; + status = "okay"; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 57f307541d2e..ad779a7dfefd 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -72,7 +72,7 @@ }; }; - sram: sram@00300000 { + sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x8000>; }; @@ -1231,7 +1231,7 @@ }; }; - usb0: ohci@00600000 { + usb0: ohci@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; @@ -1240,7 +1240,7 @@ status = "disabled"; }; - usb1: ehci@00700000 { + usb1: ehci@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index 9d2bbc41a7b0..4a2e13c8bf00 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi @@ -50,6 +50,8 @@ }; usart0: serial@f801c000 { + atmel,use-dma-rx; + atmel,use-dma-tx; status = "okay"; }; @@ -134,7 +136,7 @@ }; }; - usb0: ohci@00600000 { + usb0: ohci@600000 { status = "okay"; num-ports = <3>; atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */ @@ -143,7 +145,7 @@ >; }; - usb1: ehci@00700000 { + usb1: ehci@700000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91sam9xe.dtsi b/arch/arm/boot/dts/at91sam9xe.dtsi index 0278f63b2daf..1304452f0fae 100644 --- a/arch/arm/boot/dts/at91sam9xe.dtsi +++ b/arch/arm/boot/dts/at91sam9xe.dtsi @@ -49,11 +49,11 @@ model = "Atmel AT91SAM9XE family SoC"; compatible = "atmel,at91sam9xe", "atmel,at91sam9260"; - sram0: sram@002ff000 { + sram0: sram@2ff000 { status = "disabled"; }; - sram1: sram@00300000 { + sram1: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x4000>; }; diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi index 3c8fa26e87b7..897103e0a79b 100644 --- a/arch/arm/boot/dts/axp209.dtsi +++ b/arch/arm/boot/dts/axp209.dtsi @@ -107,7 +107,7 @@ }; }; - usb_power_supply: usb_power_supply { + usb_power_supply: usb-power-supply { compatible = "x-powers,axp202-usb-power-supply"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi new file mode 100644 index 000000000000..73b761f850c5 --- /dev/null +++ b/arch/arm/boot/dts/axp81x.dtsi @@ -0,0 +1,139 @@ +/* + * Copyright 2017 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* AXP813/818 Integrated Power Management Chip */ + +&axp81x { + interrupt-controller; + #interrupt-cells = <1>; + + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <3000>; + + reg_dcdc1: dcdc1 { + }; + + reg_dcdc2: dcdc2 { + }; + + reg_dcdc3: dcdc3 { + }; + + reg_dcdc4: dcdc4 { + }; + + reg_dcdc5: dcdc5 { + }; + + reg_dcdc6: dcdc6 { + }; + + reg_dcdc7: dcdc7 { + }; + + reg_aldo1: aldo1 { + }; + + reg_aldo2: aldo2 { + }; + + reg_aldo3: aldo3 { + }; + + reg_dldo1: dldo1 { + }; + + reg_dldo2: dldo2 { + }; + + reg_dldo3: dldo3 { + }; + + reg_dldo4: dldo4 { + }; + + reg_eldo1: eldo1 { + }; + + reg_eldo2: eldo2 { + }; + + reg_eldo3: eldo3 { + }; + + reg_fldo1: fldo1 { + }; + + reg_fldo2: fldo2 { + }; + + reg_fldo3: fldo3 { + }; + + reg_ldo_io0: ldo-io0 { + /* Disable by default to avoid conflicts with GPIO */ + status = "disabled"; + }; + + reg_ldo_io1: ldo-io1 { + /* Disable by default to avoid conflicts with GPIO */ + status = "disabled"; + }; + + reg_rtc_ldo: rtc-ldo { + /* RTC_LDO is a fixed, always-on regulator */ + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_sw: sw { + }; + + reg_drivevbus: drivevbus { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 7c957ea06c66..699fdf94d139 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -96,14 +96,14 @@ #address-cells = <1>; #size-cells = <1>; - otp: otp@0301c800 { + otp: otp@301c800 { compatible = "brcm,ocotp"; reg = <0x0301c800 0x2c>; brcm,ocotp-size = <2048>; status = "disabled"; }; - pcie_phy: phy@0301d0a0 { + pcie_phy: phy@301d0a0 { compatible = "brcm,cygnus-pcie-phy"; reg = <0x0301d0a0 0x14>; #address-cells = <1>; @@ -120,7 +120,7 @@ }; }; - pinctrl: pinctrl@0301d0c8 { + pinctrl: pinctrl@301d0c8 { compatible = "brcm,cygnus-pinmux"; reg = <0x0301d0c8 0x30>, <0x0301d24c 0x2c>; @@ -141,7 +141,7 @@ }; }; - mailbox: mailbox@03024024 { + mailbox: mailbox@3024024 { compatible = "brcm,iproc-mailbox"; reg = <0x03024024 0x40>; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; @@ -150,7 +150,7 @@ #mbox-cells = <1>; }; - gpio_crmu: gpio@03024800 { + gpio_crmu: gpio@3024800 { compatible = "brcm,cygnus-crmu-gpio"; reg = <0x03024800 0x50>, <0x03024008 0x18>; @@ -473,6 +473,16 @@ status = "disabled"; }; + clcd: clcd@180a0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x180a0000 0x1000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "combined"; + clocks = <&axi41_clk>, <&apb_clk>; + clock-names = "clcdclk", "apb_pclk"; + status = "disabled"; + }; + v3d: v3d@180a2000 { compatible = "brcm,cygnus-v3d"; reg = <0x180a2000 0x1000>; @@ -575,6 +585,14 @@ status = "disabled"; }; + pwm: pwm@180aa500 { + compatible = "brcm,kona-pwm"; + reg = <0x180aa500 0xc4>; + #pwm-cells = <3>; + clocks = <&asiu_clks BCM_CYGNUS_ASIU_PWM_CLK>; + status = "disabled"; + }; + keypad: keypad@180ac000 { compatible = "brcm,bcm-keypad"; reg = <0x180ac000 0x14c>; diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi new file mode 100644 index 000000000000..3f9cedd8011f --- /dev/null +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -0,0 +1,368 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2017 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,hr2"; + model = "Broadcom Hurricane 2 SoC"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + }; + + mpcore@19000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x19000000 0x00023000>; + #address-cells = <1>; + #size-cells = <1>; + + a9pll: arm_clk@0 { + #clock-cells = <0>; + compatible = "brcm,hr2-armpll"; + clocks = <&osc>; + reg = <0x0 0x1000>; + }; + + timer@20200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20200 0x100>; + interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + }; + + twd-timer@20600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&periph_clk>; + }; + + twd-watchdog@20620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x20620 0x20>; + interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21000 0x1000>, + <0x20100 0x100>; + }; + + L2: l2-cache@22000 { + compatible = "arm,pl310-cache"; + reg = <0x22000 0x1000>; + cache-unified; + cache-level = <2>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + + axi@18000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x18000000 0x0011c40c>; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@300 { + compatible = "ns16550a"; + reg = <0x0300 0x100>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + status = "disabled"; + }; + + uart1: serial@400 { + compatible = "ns16550a"; + reg = <0x0400 0x100>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + status = "disabled"; + }; + + dma@20000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20000 0x1000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + status = "disabled"; + }; + + amac0: ethernet@22000 { + compatible = "brcm,nsp-amac"; + reg = <0x22000 0x1000>, + <0x110000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + nand: nand@26000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x26000 0x600>, + <0x11b408 0x600>, + <0x026f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; + + gpiob: gpio@30000 { + compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio"; + reg = <0x30000 0x50>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <4>; + interrupt-controller; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + }; + + pwm: pwm@31000 { + compatible = "brcm,iproc-pwm"; + reg = <0x31000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + + rng: rng@33000 { + compatible = "brcm,bcm-nsp-rng"; + reg = <0x33000 0x14>; + }; + + qspi: qspi@27200 { + compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; + reg = <0x027200 0x184>, + <0x027000 0x124>, + <0x11c408 0x004>, + <0x0273a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", + "intr_status_reg"; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overhead", + "mspi_done", + "mspi_halted"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* partitions defined in board DTS */ + }; + + ccbtimer0: timer@34000 { + compatible = "arm,sp804"; + reg = <0x34000 0x1000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + }; + + ccbtimer1: timer@35000 { + compatible = "arm,sp804"; + reg = <0x35000 0x1000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + }; + + i2c0: i2c@38000 { + compatible = "brcm,iproc-i2c"; + reg = <0x38000 0x50>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 95 IRQ_TYPE_NONE>; + clock-frequency = <100000>; + }; + + watchdog@39000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x39000 0x1000>; + interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; + }; + + i2c1: i2c@3b000 { + compatible = "brcm,iproc-i2c"; + reg = <0x3b000 0x50>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>; + clock-frequency = <100000>; + }; + }; + + pflash: nor@20000000 { + compatible = "cfi-flash", "jedec-flash"; + reg = <0x20000000 0x04000000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + + /* partitions defined in board DTS */ + }; + + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_NONE>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; + + status = "disabled"; + + msi-parent = <&msi0>; + msi0: msi-controller { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 182 IRQ_TYPE_NONE>, + <GIC_SPI 183 IRQ_TYPE_NONE>, + <GIC_SPI 184 IRQ_TYPE_NONE>, + <GIC_SPI 185 IRQ_TYPE_NONE>; + brcm,pcie-msi-inten; + }; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_NONE>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; + + status = "disabled"; + + msi-parent = <&msi1>; + msi1: msi-controller { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>, + <GIC_SPI 189 IRQ_TYPE_NONE>, + <GIC_SPI 190 IRQ_TYPE_NONE>, + <GIC_SPI 191 IRQ_TYPE_NONE>; + brcm,pcie-msi-inten; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index dff66974feed..528b9e3bc1da 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -75,7 +75,7 @@ #address-cells = <1>; #size-cells = <1>; - a9pll: arm_clk@00000 { + a9pll: arm_clk@0 { #clock-cells = <0>; compatible = "brcm,nsp-armpll"; clocks = <&osc>; @@ -164,7 +164,7 @@ #address-cells = <1>; #size-cells = <1>; - gpioa: gpio@0020 { + gpioa: gpio@20 { compatible = "brcm,nsp-gpio-a"; reg = <0x0020 0x70>, <0x3f1c4 0x1c>; @@ -176,7 +176,7 @@ gpio-ranges = <&pinctrl 0 0 32>; }; - uart0: serial@0300 { + uart0: serial@300 { compatible = "ns16550a"; reg = <0x0300 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -184,7 +184,7 @@ status = "disabled"; }; - uart1: serial@0400 { + uart1: serial@400 { compatible = "ns16550a"; reg = <0x0400 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index eb1a28da57e3..a8844d033b3f 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -30,6 +30,11 @@ pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + }; }; /* uart1 is mapped to the pin header */ diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index c544ab302012..ba1c19b1b3eb 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -57,7 +57,8 @@ usb { label = "bcm53xx:green:usb"; gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + linux,default-trigger = "usbport"; }; status { diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts new file mode 100644 index 000000000000..ecd22a246746 --- /dev/null +++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2017 Luxul Inc. + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "luxul,abr-4500-v1", "brcm,bcm47094", "brcm,bcm4708"; + model = "Luxul ABR-4500 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000 + 0x88000000 0x18000000>; + }; + + leds { + compatible = "gpio-leds"; + + status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3 { + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts new file mode 100644 index 000000000000..15ffb1abc440 --- /dev/null +++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2017 Luxul Inc. + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "luxul,xbr-4500-v1", "brcm,bcm47094", "brcm,bcm4708"; + model = "Luxul XBR-4500 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000 + 0x88000000 0x18000000>; + }; + + leds { + compatible = "gpio-leds"; + + status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + + usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3 { + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts new file mode 100644 index 000000000000..74c83b0ca54e --- /dev/null +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2017 Luxul Inc. + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm53573.dtsi" + +/ { + compatible = "luxul,xap-1440-v1", "brcm,bcm47189", "brcm,bcm53573"; + model = "Luxul XAP-1440 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + wlan { + label = "bcm53xx:blue:wlan"; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + system { + label = "bcm53xx:green:system"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts new file mode 100644 index 000000000000..214df18f3a75 --- /dev/null +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts @@ -0,0 +1,87 @@ +/* + * Copyright 2017 Luxul Inc. + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm53573.dtsi" + +/ { + compatible = "luxul,xap-810-v1", "brcm,bcm47189", "brcm,bcm53573"; + model = "Luxul XAP-810 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + 5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + system { + label = "bcm53xx:green:system"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + }; + + pcie0_leds { + compatible = "gpio-leds"; + + 2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pcie0 { + ranges = <0x00000000 0 0 0 0 0x00100000>; + #address-cells = <3>; + #size-cells = <2>; + + bridge@0,0,0 { + reg = <0x0000 0 0 0 0>; + ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,1,0 { + reg = <0x0000 0 0 0 0>; + ranges = <0x00000000 0 0 0 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + pcie0_chipcommon: chipcommon@0 { + reg = <0 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 045b9bb857f9..9a076c409f4e 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -24,7 +24,7 @@ #address-cells = <1>; #size-cells = <1>; - uart0: serial@0300 { + uart0: serial@300 { compatible = "ns16550"; reg = <0x0300 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -32,7 +32,7 @@ status = "disabled"; }; - uart1: serial@0400 { + uart1: serial@400 { compatible = "ns16550"; reg = <0x0400 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -47,7 +47,7 @@ #address-cells = <1>; #size-cells = <1>; - a9pll: arm_clk@00000 { + a9pll: arm_clk@0 { #clock-cells = <0>; compatible = "brcm,nsp-armpll"; clocks = <&osc>; diff --git a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts new file mode 100644 index 000000000000..431cda514230 --- /dev/null +++ b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts @@ -0,0 +1,85 @@ +/* + * DTS for Unifi Switch 8 port + * + * Copyright (C) 2017 Florian Fainelli <f.fainelli@gmail.com> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm-hr2.dtsi" + +/ { + compatible = "ubnt,unifi-switch8", "brcm,bcm53342", "brcm,hr2"; + model = "Ubiquiti UniFi Switch 8 (BCM53342)"; + + /* Hurricane 2 designs use the second UART */ + chosen { + bootargs = "console=ttyS1,115200 earlyprintk"; + }; + + memory@0 { + reg = <0x00000000 0x08000000>, + <0x68000000 0x08000000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&qspi { + status = "okay"; + bspi-sel = <0>; + + flash: m25p80@0 { + compatible = "m25p80"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <12500000>; + spi-cpol; + spi-cpha; + + partition@0 { + label = "u-boot"; + reg = <0x0 0xc0000>; + }; + + partition@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x10000>; + }; + + partition@d0000 { + label = "shmoo"; + reg = <0xd0000 0x10000>; + }; + + partition@e0000 { + label = "kernel0"; + reg = <0xe0000 0xf00000>; + }; + + partition@fe0000 { + label = "kernel1"; + reg = <0xfe0000 0xf10000>; + }; + + partition@1ef0000 { + label = "cfg"; + reg = <0x1ef0000 0x100000>; + }; + + partition@1ff0000 { + label = "EEPROM"; + reg = <0x1ff0000 0x10000>; + }; + }; +}; + +&pcie0 { + /* Attaches to the internal switch */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index c698a565b8ae..16007d72c346 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -107,7 +107,7 @@ gpio-controller; #gpio-cells = <2>; - uart0: serial@0300 { + uart0: serial@300 { compatible = "ns16550a"; reg = <0x0300 0x100>; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 425c48971abe..d575823c5750 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -202,7 +202,7 @@ ranges = <0 0xe80000 0x10000>; interrupt-parent = <&aic>; - gpio0: gpio@0400 { + gpio0: gpio@400 { compatible = "snps,dw-apb-gpio"; reg = <0x0400 0x400>; #address-cells = <1>; @@ -220,7 +220,7 @@ }; }; - gpio1: gpio@0800 { + gpio1: gpio@800 { compatible = "snps,dw-apb-gpio"; reg = <0x0800 0x400>; #address-cells = <1>; @@ -238,7 +238,7 @@ }; }; - gpio2: gpio@0c00 { + gpio2: gpio@c00 { compatible = "snps,dw-apb-gpio"; reg = <0x0c00 0x400>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index 4fe1574d08c3..501c59d97eae 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -182,7 +182,7 @@ ranges = <0 0xe80000 0x10000>; interrupt-parent = <&aic>; - gpio0: gpio@0400 { + gpio0: gpio@400 { compatible = "snps,dw-apb-gpio"; reg = <0x0400 0x400>; #address-cells = <1>; @@ -200,7 +200,7 @@ }; }; - gpio1: gpio@0800 { + gpio1: gpio@800 { compatible = "snps,dw-apb-gpio"; reg = <0x0800 0x400>; #address-cells = <1>; @@ -218,7 +218,7 @@ }; }; - gpio2: gpio@0c00 { + gpio2: gpio@c00 { compatible = "snps,dw-apb-gpio"; reg = <0x0c00 0x400>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index e548229697fc..bf3a6c9a1d34 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -234,7 +234,7 @@ ranges = <0 0xe80000 0x10000>; interrupt-parent = <&aic>; - gpio0: gpio@0400 { + gpio0: gpio@400 { compatible = "snps,dw-apb-gpio"; reg = <0x0400 0x400>; #address-cells = <1>; @@ -252,7 +252,7 @@ }; }; - gpio1: gpio@0800 { + gpio1: gpio@800 { compatible = "snps,dw-apb-gpio"; reg = <0x0800 0x400>; #address-cells = <1>; @@ -270,7 +270,7 @@ }; }; - gpio2: gpio@0c00 { + gpio2: gpio@c00 { compatible = "snps,dw-apb-gpio"; reg = <0x0c00 0x400>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts index a0f0916156e6..eed89e659143 100644 --- a/arch/arm/boot/dts/da850-lcdk.dts +++ b/arch/arm/boot/dts/da850-lcdk.dts @@ -26,6 +26,19 @@ reg = <0xc0000000 0x08000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dsp_memory_region: dsp-memory@c3000000 { + compatible = "shared-dma-pool"; + reg = <0xc3000000 0x1000000>; + reusable; + status = "okay"; + }; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "DA850/OMAP-L138 LCDK"; @@ -319,3 +332,8 @@ pinctrl-0 = <&vpif_capture_pins>; status = "okay"; }; + +&dsp { + memory-region = <&dsp_memory_region>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index af68ef7b0caa..c66cf7895363 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -23,6 +23,18 @@ reg = <0xfffee000 0x2000>; }; }; + dsp: dsp@11800000 { + compatible = "ti,da850-dsp"; + reg = <0x11800000 0x40000>, + <0x11e00000 0x8000>, + <0x11f00000 0x8000>, + <0x01c14044 0x4>, + <0x01c14174 0x8>; + reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; + interrupt-parent = <&intc>; + interrupts = <28>; + status = "disabled"; + }; soc@1c00000 { compatible = "simple-bus"; model = "da850"; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index f4a07bb7c3a2..4a0a5115b298 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -457,25 +457,25 @@ }; }; - thermal: thermal-diode@001c { + thermal: thermal-diode@1c { compatible = "marvell,dove-thermal"; reg = <0x001c 0x0c>, <0x005c 0x08>; }; - gate_clk: clock-gating-ctrl@0038 { + gate_clk: clock-gating-ctrl@38 { compatible = "marvell,dove-gating-clock"; reg = <0x0038 0x4>; clocks = <&core_clk 0>; #clock-cells = <1>; }; - divider_clk: core-clock@0064 { + divider_clk: core-clock@64 { compatible = "marvell,dove-divider-clock"; reg = <0x0064 0x8>; #clock-cells = <1>; }; - pinctrl: pin-ctrl@0200 { + pinctrl: pin-ctrl@200 { compatible = "marvell,dove-pinctrl"; reg = <0x0200 0x14>, <0x0440 0x04>; @@ -719,13 +719,13 @@ }; }; - core_clk: core-clocks@0214 { + core_clk: core-clocks@214 { compatible = "marvell,dove-core-clock"; reg = <0x0214 0x4>; #clock-cells = <1>; }; - gpio0: gpio-ctrl@0400 { + gpio0: gpio-ctrl@400 { compatible = "marvell,orion-gpio"; #gpio-cells = <2>; gpio-controller; @@ -737,7 +737,7 @@ interrupts = <12>, <13>, <14>, <60>; }; - gpio1: gpio-ctrl@0420 { + gpio1: gpio-ctrl@420 { compatible = "marvell,orion-gpio"; #gpio-cells = <2>; gpio-controller; diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi index 343e95f9a001..e088bb93636a 100644 --- a/arch/arm/boot/dts/dra7-evm-common.dtsi +++ b/arch/arm/boot/dts/dra7-evm-common.dtsi @@ -256,3 +256,7 @@ status = "okay"; }; }; + +&pcie1_rc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index aa426dabb6c3..ef9c90daa74b 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -497,7 +497,3 @@ pinctrl-1 = <&dcan1_pins_sleep>; pinctrl-2 = <&dcan1_pins_default>; }; - -&pcie1_rc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 92b5cb40a9d5..ac9216293b7c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -170,7 +170,7 @@ pbias_mmc_reg: pbias_mmc_omap5 { regulator-name = "pbias_mmc_omap5"; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; }; }; diff --git a/arch/arm/boot/dts/ep7211-edb7211.dts b/arch/arm/boot/dts/ep7211-edb7211.dts index 9a134ed271eb..bc9d5b697452 100644 --- a/arch/arm/boot/dts/ep7211-edb7211.dts +++ b/arch/arm/boot/dts/ep7211-edb7211.dts @@ -75,7 +75,7 @@ }; &bus { - flash: nor@00000000 { + flash: nor@0 { compatible = "cfi-flash"; reg = <0 0x00000000 0x02000000>; bank-width = <2>; diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index 639c2e605f3c..152e0291d0da 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -29,7 +29,7 @@ reg = <0x40000000 0x1ff00000>; }; - firmware@0205f000 { + firmware@205f000 { compatible = "samsung,secure-firmware"; reg = <0x0205f000 0x1000>; }; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index bbdfcbc6e7d2..029eb18590cf 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -32,7 +32,7 @@ reg = <0x40000000 0x1ff00000>; }; - firmware@0205F000 { + firmware@205f000 { compatible = "samsung,secure-firmware"; reg = <0x0205F000 0x1000>; }; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 0b45467d77a8..3743df4de390 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -32,7 +32,7 @@ reg = <0x40000000 0x1ff00000>; }; - firmware@0205F000 { + firmware@205f000 { compatible = "samsung,secure-firmware"; reg = <0x0205F000 0x1000>; }; @@ -227,28 +227,6 @@ vci-supply = <&ldo20_reg>; reset-gpios = <&gpe0 1 GPIO_ACTIVE_LOW>; te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; - power-on-delay= <30>; - power-off-delay= <120>; - reset-delay = <5>; - init-delay = <100>; - flip-horizontal; - flip-vertical; - panel-width-mm = <29>; - panel-height-mm = <29>; - - display-timings { - timing-0 { - clock-frequency = <4600000>; - hactive = <320>; - vactive = <320>; - hfront-porch = <1>; - hback-porch = <1>; - hsync-len = <1>; - vfront-porch = <150>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; }; }; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 590ee442d0ae..2bd3872221a1 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -122,7 +122,7 @@ }; }; - sysram@02020000 { + sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x40000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 5739389f5bb8..4768b086ed67 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -55,7 +55,7 @@ serial3 = &serial_3; }; - clock_audss: clock-controller@03810000 { + clock_audss: clock-controller@3810000 { compatible = "samsung,exynos4210-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; @@ -64,7 +64,7 @@ clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; - i2s0: i2s@03830000 { + i2s0: i2s@3830000 { compatible = "samsung,s5pv210-i2s"; reg = <0x03830000 0x100>; clocks = <&clock_audss EXYNOS_I2S_BUS>, diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index f280954b260a..82c32d4d83d8 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -843,7 +843,7 @@ }; }; - pinctrl@03860000 { + pinctrl@3860000 { gpz: gpz { gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 0c89ea99de54..acd2b2286ccb 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -31,7 +31,7 @@ stdout-path = &serial_2; }; - sysram@02020000 { + sysram@2020000 { smp-sysram@0 { status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 768fb075b1fd..03dd61f64809 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -64,7 +64,7 @@ }; }; - sysram: sysram@02020000 { + sysram: sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x20000>; #address-cells = <1>; @@ -151,7 +151,7 @@ }; }; - pinctrl_2: pinctrl@03860000 { + pinctrl_2: pinctrl@3860000 { compatible = "samsung,exynos4210-pinctrl"; reg = <0x03860000 0x1000>; }; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index 14ce2c69bc0b..bda49b232f7b 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -26,7 +26,7 @@ reg = <0x40000000 0x40000000>; }; - firmware@0203F000 { + firmware@203f000 { compatible = "samsung,secure-firmware"; reg = <0x0203F000 0x1000>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 102acd78be15..a21be71000c1 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -20,7 +20,7 @@ stdout-path = &serial_1; }; - firmware@0204F000 { + firmware@204f000 { compatible = "samsung,secure-firmware"; reg = <0x0204F000 0x1000>; }; @@ -31,8 +31,6 @@ pinctrl-0 = <&gpio_power_key>; power_key { - interrupt-parent = <&gpx1>; - interrupts = <3 IRQ_TYPE_NONE>; gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "power key"; @@ -253,7 +251,7 @@ samsung,i2c-max-bus-freq = <400000>; status = "okay"; - usb3503: usb3503@08 { + usb3503: usb3503@8 { compatible = "smsc,usb3503"; reg = <0x08>; @@ -263,7 +261,7 @@ initial-mode = <1>; }; - max77686: pmic@09 { + max77686: pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&gpx3>; interrupts = <2 IRQ_TYPE_NONE>; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 97882267ef09..acf48a018e5e 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -43,8 +43,6 @@ pinctrl-0 = <&gpio_power_key &gpio_home_key>; home_key { - interrupt-parent = <&gpx2>; - interrupts = <2 IRQ_TYPE_NONE>; gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; linux,code = <KEY_HOME>; label = "home key"; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 8a89eb893d64..b0b5ec7903a5 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -32,7 +32,7 @@ stdout-path = &serial_2; }; - firmware@0203F000 { + firmware@203f000 { compatible = "samsung,secure-firmware"; reg = <0x0203F000 0x1000>; }; diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi index 1d27c28564e4..4eebd4721a5f 100644 --- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi @@ -899,7 +899,7 @@ }; }; - pinctrl_2: pinctrl@03860000 { + pinctrl_2: pinctrl@3860000 { gpz: gpz { gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index bceb919ac637..220cdf109405 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -18,6 +18,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/clock/maxim,max77686.h> +#include <dt-bindings/pinctrl/samsung.h> / { model = "Samsung Trats 2 based on Exynos4412"; @@ -40,7 +41,7 @@ stdout-path = &serial_2; }; - firmware@0204F000 { + firmware@204f000 { compatible = "samsung,secure-firmware"; reg = <0x0204F000 0x1000>; }; @@ -97,6 +98,34 @@ gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + vsil12: voltage-regulator-6 { + compatible = "regulator-fixed"; + regulator-name = "VSIL_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&buck7_reg>; + }; + + vcc33mhl: voltage-regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3.3_MHL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc18mhl: voltage-regulator-8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1.8_MHL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; gpio-keys { @@ -206,7 +235,7 @@ #size-cells = <0>; status = "okay"; - ak8975@0c { + ak8975@c { compatible = "asahi-kasei,ak8975"; reg = <0x0c>; gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; @@ -229,6 +258,36 @@ }; }; + i2c-mhl { + compatible = "i2c-gpio"; + gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <100>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&i2c_mhl_bus>; + pinctrl-names = "default"; + status = "okay"; + + sii9234: hdmi-bridge@39 { + compatible = "sil,sii9234"; + avcc33-supply = <&vcc33mhl>; + iovcc18-supply = <&vcc18mhl>; + avcc12-supply = <&vsil12>; + cvcc12-supply = <&vsil12>; + reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpf3>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x39>; + + port { + mhl_to_hdmi: endpoint { + remote-endpoint = <&hdmi_to_mhl>; + }; + }; + }; + }; + camera: camera { pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; pinctrl-names = "default"; @@ -501,6 +560,29 @@ status = "okay"; }; +&hdmi { + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd>; + vdd-supply = <&ldo3_reg>; + vdd_osc-supply = <&ldo4_reg>; + vdd_pll-supply = <&ldo3_reg>; + ddc = <&i2c_5>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + hdmi_to_mhl: endpoint { + remote-endpoint = <&mhl_to_hdmi>; + }; + }; + }; +}; + &hsotg { vusb_d-supply = <&ldo15_reg>; vusb_a-supply = <&ldo12_reg>; @@ -579,6 +661,10 @@ }; }; +&i2c_5 { + status = "okay"; +}; + &i2c_7 { samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; @@ -587,7 +673,7 @@ pinctrl-names = "default"; status = "okay"; - max77686: max77686_pmic@09 { + max77686: max77686_pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&gpx0>; interrupts = <7 IRQ_TYPE_NONE>; @@ -873,12 +959,20 @@ }; }; +&i2c_8 { + status = "okay"; +}; + &i2s0 { pinctrl-0 = <&i2s0_bus>; pinctrl-names = "default"; status = "okay"; }; +&mixer { + status = "okay"; +}; + &mshc_0 { broken-cd; non-removable; @@ -904,6 +998,18 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep0>; + mhl_int: mhl-int { + samsung,pins = "gpf3-5"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + i2c_mhl_bus: i2c-mhl-bus { + samsung,pins = "gpf0-4", "gpf0-6"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + sleep0: sleep-states { PIN_SLP(gpa0-0, INPUT, NONE); PIN_SLP(gpa0-1, OUT0, NONE); @@ -1007,6 +1113,11 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep1>; + hdmi_hpd: hdmi-hpd { + samsung,pins = "gpx3-7"; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + sleep1: sleep-states { PIN_SLP(gpk0-0, PREV, NONE); PIN_SLP(gpk0-1, PREV, NONE); diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 7ff03a7e8fb9..b255ac55b1c1 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -150,7 +150,7 @@ }; }; - sysram@02020000 { + sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x40000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 18a7f396ac5f..0efd678b8251 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -152,6 +152,8 @@ }; &hdmi { + status = "okay"; + ddc = <&i2c_2>; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_LOW>; vdd_osc-supply = <&ldo10_reg>; vdd_pll-supply = <&ldo8_reg>; @@ -455,15 +457,9 @@ &i2c_2 { status = "okay"; - + /* used by HDMI DDC */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; }; &i2c_3 { @@ -489,15 +485,9 @@ &i2c_8 { status = "okay"; - + /* used by HDMI PHY */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x38>; - - hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; }; &i2c_9 { @@ -516,6 +506,10 @@ status = "okay"; }; +&mixer { + status = "okay"; +}; + &mmc_0 { status = "okay"; broken-cd; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 062cba4c2c31..1e3f9627766c 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -116,6 +116,8 @@ }; &hdmi { + status = "okay"; + ddc = <&i2c_2>; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; }; @@ -129,7 +131,7 @@ reg = <0x50>; }; - max77686@09 { + max77686@9 { compatible = "maxim,max77686"; reg = <0x09>; interrupt-parent = <&gpx3>; @@ -308,24 +310,16 @@ &i2c_2 { status = "okay"; + /* used by HDMI DDC */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; }; &i2c_8 { status = "okay"; + /* used by HDMI PHY */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; - - hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; }; &i2c_9 { @@ -344,6 +338,10 @@ status = "okay"; }; +&mixer { + status = "okay"; +}; + &mmc_0 { status = "okay"; broken-cd; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index 8788880e459d..2e7175d2b1b8 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -261,10 +261,10 @@ }; &hdmi { + status = "okay"; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; - phy = <&hdmiphy>; ddc = <&i2c_2>; hdmi-en-supply = <&tps65090_fet7>; vdd-supply = <&ldo8_reg>; @@ -281,7 +281,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - max77686: max77686@09 { + max77686: max77686@9 { compatible = "maxim,max77686"; interrupt-parent = <&gpx3>; interrupts = <2 IRQ_TYPE_NONE>; @@ -450,13 +450,9 @@ &i2c_2 { status = "okay"; + /* used by HDMI DDC */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; }; &i2c_3 { @@ -514,19 +510,19 @@ &i2c_8 { status = "okay"; + /* used by HDMI PHY */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - - hdmiphy: hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; }; &i2s0 { status = "okay"; }; +&mixer { + status = "okay"; +}; + /* eMMC flash */ &mmc_0 { status = "okay"; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index d53bfcbeb39c..47dbc50546c1 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -91,10 +91,10 @@ }; &hdmi { + status = "okay"; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; - phy = <&hdmiphy>; ddc = <&i2c_2>; hdmi-en-supply = <&ldo8_reg>; vdd-supply = <&ldo8_reg>; @@ -362,13 +362,9 @@ &i2c_2 { status = "okay"; + /* used by HDMI DDC */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; }; &i2c_3 { @@ -412,19 +408,19 @@ &i2c_8 { status = "okay"; + /* used by HDMI PHY */ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - - hdmiphy: hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; }; &i2s0 { status = "okay"; }; +&mixer { + status = "okay"; +}; + &mmc_0 { status = "okay"; broken-cd; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 8dbeb873e99c..5286084e1032 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -93,7 +93,7 @@ }; soc: soc { - sysram@02020000 { + sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x30000>; #address-cells = <1>; @@ -219,7 +219,7 @@ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; }; - pinctrl_3: pinctrl@03860000 { + pinctrl_3: pinctrl@3860000 { compatible = "samsung,exynos5250-pinctrl"; reg = <0x03860000 0x1000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; @@ -367,6 +367,11 @@ clocks = <&clock CLK_I2C_HDMI>; clock-names = "i2c"; status = "disabled"; + + hdmiphy: hdmiphy@38 { + compatible = "samsung,exynos4212-hdmiphy"; + reg = <0x38>; + }; }; i2c_9: i2c@121D0000 { @@ -475,7 +480,7 @@ status = "disabled"; }; - i2s0: i2s@03830000 { + i2s0: i2s@3830000 { compatible = "samsung,s5pv210-i2s"; status = "disabled"; reg = <0x03830000 0x100>; @@ -637,7 +642,7 @@ }; gsc_0: gsc@13e00000 { - compatible = "samsung,exynos5-gsc"; + compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_gsc>; @@ -647,7 +652,7 @@ }; gsc_1: gsc@13e10000 { - compatible = "samsung,exynos5-gsc"; + compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_gsc>; @@ -657,7 +662,7 @@ }; gsc_2: gsc@13e20000 { - compatible = "samsung,exynos5-gsc"; + compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e20000 0x1000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_gsc>; @@ -667,7 +672,7 @@ }; gsc_3: gsc@13e30000 { - compatible = "samsung,exynos5-gsc"; + compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e30000 0x1000>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_gsc>; @@ -687,6 +692,8 @@ clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"; samsung,syscon-phandle = <&pmu_system_controller>; + phy = <&hdmiphy>; + status = "disabled"; }; hdmicec: cec@101B0000 { @@ -702,7 +709,7 @@ status = "disabled"; }; - mixer@14450000 { + mixer: mixer@14450000 { compatible = "samsung,exynos5250-mixer"; reg = <0x14450000 0x10000>; power-domains = <&pd_disp1>; @@ -711,6 +718,7 @@ <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "hdmi", "sclk_hdmi"; iommus = <&sysmmu_tv>; + status = "disabled"; }; dp_phy: video-phy { diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index c4de1353e5df..a45eaae33f8f 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -54,7 +54,7 @@ #clock-cells = <0>; }; - firmware@02073000 { + firmware@2073000 { compatible = "samsung,secure-firmware"; reg = <0x02073000 0x1000>; }; @@ -164,7 +164,7 @@ samsung,i2c-max-bus-freq = <400000>; status = "okay"; - usb3503: usb-hub@08 { + usb3503: usb-hub@8 { compatible = "smsc,usb3503"; reg = <0x08>; @@ -178,7 +178,7 @@ refclk-frequency = <24000000>; }; - max77802: pmic@09 { + max77802: pmic@9 { compatible = "maxim,max77802"; reg = <0x9>; interrupt-parent = <&gpx0>; diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 9cb7726ef8d0..25f21e9e7d58 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -32,7 +32,7 @@ #clock-cells = <0>; }; - firmware@02037000 { + firmware@2037000 { compatible = "samsung,secure-firmware"; reg = <0x02037000 0x1000>; }; diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 7eab4bc07cec..06713ec86f0d 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -187,7 +187,7 @@ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; }; - pinctrl_3: pinctrl@03860000 { + pinctrl_3: pinctrl@3860000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x03860000 0x1000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; @@ -223,7 +223,7 @@ }; }; - audi2s0: i2s@03830000 { + audi2s0: i2s@3830000 { compatible = "samsung,exynos5420-i2s"; reg = <0x03830000 0x100>; dmas = <&pdma0 10 diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index ee1bb9b8b366..bc78575d8a4d 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -30,7 +30,7 @@ bootargs = "console=ttySAC3,115200"; }; - firmware@02073000 { + firmware@2073000 { compatible = "samsung,secure-firmware"; reg = <0x02073000 0x1000>; }; @@ -360,6 +360,10 @@ status = "okay"; }; +&mixer { + status = "okay"; +}; + &mmc_0 { status = "okay"; broken-cd; diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi index 5c052d7ff554..d7d703aa1699 100644 --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi @@ -36,6 +36,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu1: cpu@1 { @@ -48,6 +49,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu2: cpu@2 { @@ -60,6 +62,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu3: cpu@3 { @@ -72,6 +75,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu4: cpu@100 { @@ -85,6 +89,7 @@ cooling-min-level = <0>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu5: cpu@101 { @@ -97,6 +102,7 @@ cooling-min-level = <0>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu6: cpu@102 { @@ -109,6 +115,7 @@ cooling-min-level = <0>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu7: cpu@103 { @@ -121,6 +128,7 @@ cooling-min-level = <0>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; }; }; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 683a4cfb4a23..38af8769711c 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -696,6 +696,10 @@ status = "okay"; }; +&mixer { + status = "okay"; +}; + /* eMMC flash */ &mmc_0 { status = "okay"; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 08c8ab173e87..310d8637ce9f 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -130,6 +130,7 @@ &hdmi { status = "okay"; + ddc = <&i2c_2>; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; @@ -347,12 +348,12 @@ &i2c_2 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + /* used by HDMI DDC */ status = "okay"; +}; - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; +&mixer { + status = "okay"; }; &mmc_0 { diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 02d2f898efa6..8aa2cc7aa125 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -352,7 +352,7 @@ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; }; - pinctrl_4: pinctrl@03860000 { + pinctrl_4: pinctrl@3860000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x03860000 0x1000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; @@ -365,7 +365,7 @@ interrupt-parent = <&gic>; ranges; - adma: adma@03880000 { + adma: adma@3880000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x03880000 0x1000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; @@ -429,7 +429,7 @@ }; }; - i2s0: i2s@03830000 { + i2s0: i2s@3830000 { compatible = "samsung,exynos5420-i2s"; reg = <0x03830000 0x100>; dmas = <&adma 0 @@ -646,6 +646,7 @@ clock-names = "mixer", "hdmi", "sclk_hdmi"; power-domains = <&disp_pd>; iommus = <&sysmmu_tv>; + status = "disabled"; }; rotator: rotator@11C00000 { @@ -658,7 +659,7 @@ }; gsc_0: video-scaler@13e00000 { - compatible = "samsung,exynos5-gsc"; + compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_GSCL0>; @@ -668,7 +669,7 @@ }; gsc_1: video-scaler@13e10000 { - compatible = "samsung,exynos5-gsc"; + compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_GSCL1>; diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index bf3c6f1ec4ee..ec01d8020c2d 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -35,6 +35,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu1: cpu@101 { @@ -47,6 +48,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu2: cpu@102 { @@ -59,6 +61,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu3: cpu@103 { @@ -71,6 +74,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu4: cpu@0 { @@ -84,6 +88,7 @@ cooling-min-level = <0>; cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu5: cpu@1 { @@ -96,6 +101,7 @@ cooling-min-level = <0>; cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu6: cpu@2 { @@ -108,6 +114,7 @@ cooling-min-level = <0>; cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu7: cpu@3 { @@ -120,6 +127,7 @@ cooling-min-level = <0>; cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi new file mode 100644 index 000000000000..a5b8d0f0877e --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -0,0 +1,443 @@ +/* + * Hardkernel Odroid XU3/XU4/HC1 boards core device tree source + * + * Copyright (c) 2017 Marek Szyprowski + * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <dt-bindings/clock/samsung,s2mps11.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include "exynos5800.dtsi" +#include "exynos5422-cpus.dtsi" + +/ { + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x7EA00000>; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + firmware@02073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; +}; + +&bus_wcore { + devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, + <&nocp_mem1_0>, <&nocp_mem1_1>; + vdd-supply = <&buck3_reg>; + exynos,saturation-ratio = <100>; + status = "okay"; +}; + +&bus_noc { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_fsys_apb { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_fsys2 { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_gen { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_g2d { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_g2d_acp { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_jpeg { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_jpeg_apb { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_disp1_fimd { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_disp1 { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_gscl_scaler { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&bus_mscl { + devfreq = <&bus_wcore>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&buck6_reg>; +}; + +&cpu4 { + cpu-supply = <&buck2_reg>; +}; + +&hsi2c_4 { + status = "okay"; + + s2mps11_pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + samsung,s2mps11-acokb-ground; + + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + + s2mps11_osc: clocks { + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", + "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "vddq_mmc0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo4_reg: LDO4 { + regulator-name = "vdd_adc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_ldo6"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "vddq_mmc2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "vdd_ldo16"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "tsp_avdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo18_reg: LDO18 { + regulator-name = "vdd_emmc_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo24_reg: LDO24 { + regulator-name = "tsp_io"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo26_reg: LDO26 { + regulator-name = "vdd_ldo26"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_mem"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1.0v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_1.8v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2.8v_ldo"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3750000>; + regulator-always-on; + regulator-boot-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_vmem"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&mmc_2 { + status = "okay"; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + bus-width = <4>; + cap-sd-highspeed; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>; +}; + +&nocp_mem0_0 { + status = "okay"; +}; + +&nocp_mem0_1 { + status = "okay"; +}; + +&nocp_mem1_0 { + status = "okay"; +}; + +&nocp_mem1_1 { + status = "okay"; +}; + +&pinctrl_0 { + s2mps11_irq: s2mps11-irq { + samsung,pins = "gpx0-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; +}; + +&tmu_cpu0 { + vtmu-supply = <&ldo7_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo7_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo7_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo7_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo7_reg>; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +/* usbdrd_dwc3_1 mode customized in each board */ + +&usbdrd3_0 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; + +&usbdrd3_1 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts new file mode 100644 index 000000000000..fb8e8ae776e9 --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -0,0 +1,213 @@ +/* + * Hardkernel Odroid HC1 board device tree source + * + * Copyright (c) 2017 Marek Szyprowski + * Copyright (c) 2017 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos5422-odroid-core.dtsi" + +/ { + model = "Hardkernel Odroid HC1"; + compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \ + "samsung,exynos5"; + + pwmleds { + compatible = "pwm-leds"; + + blueled { + label = "blue:heartbeat"; + pwms = <&pwm 2 2000000 0>; + pwm-names = "pwm2"; + max_brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + thermal-sensors = <&tmu_cpu0 0>; + trips { + cpu0_alert0: cpu-alert-0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + cpu0_alert1: cpu-alert-1 { + temperature = <85000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + cpu0_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* + * When reaching cpu0_alert0, reduce CPU + * by 2 steps. On Exynos5422/5800 that would + * be: 1600 MHz and 1100 MHz. + */ + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&cpu0 0 2>; + }; + map1 { + trip = <&cpu0_alert0>; + cooling-device = <&cpu4 0 2>; + }; + /* + * When reaching cpu0_alert1, reduce CPU + * further, down to 600 MHz (12 steps for big, + * 7 steps for LITTLE). + */ + map2 { + trip = <&cpu0_alert1>; + cooling-device = <&cpu0 3 7>; + }; + map3 { + trip = <&cpu0_alert1>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + cpu1_thermal: cpu1-thermal { + thermal-sensors = <&tmu_cpu1 0>; + trips { + cpu1_alert0: cpu-alert-0 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + cpu1_alert1: cpu-alert-1 { + temperature = <85000>; + hysteresis = <10000>; + type = "active"; + }; + cpu1_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&cpu0 0 2>; + }; + map1 { + trip = <&cpu1_alert0>; + cooling-device = <&cpu4 0 2>; + }; + map2 { + trip = <&cpu1_alert1>; + cooling-device = <&cpu0 3 7>; + }; + map3 { + trip = <&cpu1_alert1>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + cpu2_thermal: cpu2-thermal { + thermal-sensors = <&tmu_cpu2 0>; + trips { + cpu2_alert0: cpu-alert-0 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + cpu2_alert1: cpu-alert-1 { + temperature = <85000>; + hysteresis = <10000>; + type = "active"; + }; + cpu2_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&cpu0 0 2>; + }; + map1 { + trip = <&cpu2_alert0>; + cooling-device = <&cpu4 0 2>; + }; + map2 { + trip = <&cpu2_alert1>; + cooling-device = <&cpu0 3 7>; + }; + map3 { + trip = <&cpu2_alert1>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + cpu3_thermal: cpu3-thermal { + thermal-sensors = <&tmu_cpu3 0>; + trips { + cpu3_alert0: cpu-alert-0 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + cpu3_alert1: cpu-alert-1 { + temperature = <85000>; + hysteresis = <10000>; + type = "active"; + }; + cpu3_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&cpu0 0 2>; + }; + map1 { + trip = <&cpu3_alert0>; + cooling-device = <&cpu4 0 2>; + }; + map2 { + trip = <&cpu3_alert1>; + cooling-device = <&cpu0 3 7>; + }; + map3 { + trip = <&cpu3_alert1>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + }; + +}; + +&pwm { + /* + * PWM 2 -- Blue LED + */ + pinctrl-0 = <&pwm2_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <2>; + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi index c0b85981c6bf..da3141a307d5 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi @@ -11,6 +11,8 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/sound/samsung-i2s.h> + / { sound: sound { compatible = "simple-audio-card"; @@ -43,6 +45,17 @@ }; }; +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>; + assigned-clock-parents = <&clock CLK_FIN_PLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-rates = <0>, + <0>, + <19200000>; +}; + &hsi2c_5 { status = "okay"; max98090: max98090@10 { diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index a183b56283f8..445c6c5a1300 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -12,32 +12,28 @@ * published by the Free Software Foundation. */ -#include <dt-bindings/clock/samsung,s2mps11.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/sound/samsung-i2s.h> -#include "exynos5800.dtsi" -#include "exynos5422-cpus.dtsi" +#include <dt-bindings/input/input.h> +#include "exynos5422-odroid-core.dtsi" / { - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7EA00000>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - firmware@02073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&power_key>; + + power_key { + /* + * The power button (SW2) is connected to the PWRON + * pin (active high) of the S2MPS11 PMIC, which acts + * as a 16ms debouce filter and signal inverter with + * output on ONOB pin (active low). ONOB PMIC pin is + * then connected to XEINT3 SoC pin. + */ + gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + label = "power key"; + debounce-interval = <0>; + wakeup-source; }; }; @@ -63,22 +59,22 @@ polling-delay-passive = <250>; polling-delay = <0>; trips { - cpu_alert0: cpu-alert-0 { + cpu0_alert0: cpu-alert-0 { temperature = <50000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; - cpu_alert1: cpu-alert-1 { + cpu0_alert1: cpu-alert-1 { temperature = <60000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; - cpu_alert2: cpu-alert-2 { + cpu0_alert2: cpu-alert-2 { temperature = <70000>; /* millicelsius */ hysteresis = <5000>; /* millicelsius */ type = "active"; }; - cpu_crit0: cpu-crit-0 { + cpu0_crit0: cpu-crit-0 { temperature = <120000>; /* millicelsius */ hysteresis = <0>; /* millicelsius */ type = "critical"; @@ -87,59 +83,258 @@ * Exynos542x supports only 4 trip-points * so for these polling mode is required. * Start polling at temperature level of last - * interrupt-driven trip: cpu_alert2 + * interrupt-driven trip: cpu0_alert2 */ - cpu_alert3: cpu-alert-3 { + cpu0_alert3: cpu-alert-3 { temperature = <70000>; /* millicelsius */ hysteresis = <10000>; /* millicelsius */ type = "passive"; }; - cpu_alert4: cpu-alert-4 { + cpu0_alert4: cpu-alert-4 { temperature = <85000>; /* millicelsius */ hysteresis = <10000>; /* millicelsius */ type = "passive"; }; - }; cooling-maps { map0 { - trip = <&cpu_alert0>; + trip = <&cpu0_alert0>; cooling-device = <&fan0 0 1>; }; map1 { - trip = <&cpu_alert1>; + trip = <&cpu0_alert1>; cooling-device = <&fan0 1 2>; }; map2 { - trip = <&cpu_alert2>; + trip = <&cpu0_alert2>; cooling-device = <&fan0 2 3>; }; /* - * When reaching cpu_alert3, reduce CPU + * When reaching cpu0_alert3, reduce CPU * by 2 steps. On Exynos5422/5800 that would * be: 1600 MHz and 1100 MHz. */ map3 { - trip = <&cpu_alert3>; + trip = <&cpu0_alert3>; cooling-device = <&cpu0 0 2>; }; map4 { - trip = <&cpu_alert3>; + trip = <&cpu0_alert3>; cooling-device = <&cpu4 0 2>; }; - /* - * When reaching cpu_alert4, reduce CPU - * further, down to 600 MHz (11 steps for big, + * When reaching cpu0_alert4, reduce CPU + * further, down to 600 MHz (12 steps for big, * 7 steps for LITTLE). */ map5 { - trip = <&cpu_alert4>; + trip = <&cpu0_alert4>; + cooling-device = <&cpu0 3 7>; + }; + map6 { + trip = <&cpu0_alert4>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + cpu1_thermal: cpu1-thermal { + thermal-sensors = <&tmu_cpu1 0>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + cpu1_alert0: cpu-alert-0 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + cpu1_alert1: cpu-alert-1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + cpu1_alert2: cpu-alert-2 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + cpu1_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + cpu1_alert3: cpu-alert-3 { + temperature = <70000>; + hysteresis = <10000>; + type = "passive"; + }; + cpu1_alert4: cpu-alert-4 { + temperature = <85000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu1_alert2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&cpu1_alert3>; + cooling-device = <&cpu0 0 2>; + }; + map4 { + trip = <&cpu1_alert3>; + cooling-device = <&cpu4 0 2>; + }; + map5 { + trip = <&cpu1_alert4>; + cooling-device = <&cpu0 3 7>; + }; + map6 { + trip = <&cpu1_alert4>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + cpu2_thermal: cpu2-thermal { + thermal-sensors = <&tmu_cpu2 0>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + cpu2_alert0: cpu-alert-0 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + cpu2_alert1: cpu-alert-1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + cpu2_alert2: cpu-alert-2 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + cpu2_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + cpu2_alert3: cpu-alert-3 { + temperature = <70000>; + hysteresis = <10000>; + type = "passive"; + }; + cpu2_alert4: cpu-alert-4 { + temperature = <85000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu2_alert2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&cpu2_alert3>; + cooling-device = <&cpu0 0 2>; + }; + map4 { + trip = <&cpu2_alert3>; + cooling-device = <&cpu4 0 2>; + }; + map5 { + trip = <&cpu2_alert4>; cooling-device = <&cpu0 3 7>; }; map6 { - trip = <&cpu_alert4>; - cooling-device = <&cpu4 3 11>; + trip = <&cpu2_alert4>; + cooling-device = <&cpu4 3 12>; + }; + }; + }; + cpu3_thermal: cpu3-thermal { + thermal-sensors = <&tmu_cpu3 0>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + cpu3_alert0: cpu-alert-0 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + cpu3_alert1: cpu-alert-1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + cpu3_alert2: cpu-alert-2 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + cpu3_crit0: cpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + cpu3_alert3: cpu-alert-3 { + temperature = <70000>; + hysteresis = <10000>; + type = "passive"; + }; + cpu3_alert4: cpu-alert-4 { + temperature = <85000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu3_alert2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&cpu3_alert3>; + cooling-device = <&cpu0 0 2>; + }; + map4 { + trip = <&cpu3_alert3>; + cooling-device = <&cpu4 0 2>; + }; + map5 { + trip = <&cpu3_alert4>; + cooling-device = <&cpu0 3 7>; + }; + map6 { + trip = <&cpu3_alert4>; + cooling-device = <&cpu4 3 12>; }; }; }; @@ -151,110 +346,9 @@ status = "okay"; }; -&bus_wcore { - devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, - <&nocp_mem1_0>, <&nocp_mem1_1>; - vdd-supply = <&buck3_reg>; - exynos,saturation-ratio = <100>; - status = "okay"; -}; - -&bus_noc { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys_apb { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys2 { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_gen { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_peri { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_g2d { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_g2d_acp { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_jpeg { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_jpeg_apb { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_disp1_fimd { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_disp1 { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_gscl_scaler { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_mscl { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>; - assigned-clock-parents = <&clock CLK_FIN_PLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-rates = <0>, - <0>, - <19200000>; -}; - -&cpu0 { - cpu-supply = <&buck6_reg>; -}; - -&cpu4 { - cpu-supply = <&buck2_reg>; -}; - &hdmi { status = "okay"; + ddc = <&i2c_2>; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; @@ -269,246 +363,15 @@ needs-hpd; }; -&hsi2c_4 { - status = "okay"; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - samsung,s2mps11-acokb-ground; - - interrupt-parent = <&gpx0>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&s2mps11_irq>; - - s2mps11_osc: clocks { - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "vdd_ldo1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "vddq_mmc0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo4_reg: LDO4 { - regulator-name = "vdd_adc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_ldo6"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "vddq_mmc2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "vdd_ldo16"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "tsp_avdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo18_reg: LDO18 { - regulator-name = "vdd_emmc_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo24_reg: LDO24 { - regulator-name = "tsp_io"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo26_reg: LDO26 { - regulator-name = "vdd_ldo26"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_mem"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1.0v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_1.8v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2.8v_ldo"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3750000>; - regulator-always-on; - regulator-boot-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_vmem"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - &i2c_2 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + /* used by HDMI DDC */ status = "okay"; +}; - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; +&mixer { + status = "okay"; }; &mmc_0 { @@ -530,48 +393,18 @@ vqmmc-supply = <&ldo3_reg>; }; -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - cap-sd-highspeed; - vmmc-supply = <&ldo19_reg>; - vqmmc-supply = <&ldo13_reg>; -}; - -&nocp_mem0_0 { - status = "okay"; -}; - -&nocp_mem0_1 { - status = "okay"; -}; - -&nocp_mem1_0 { - status = "okay"; -}; - -&nocp_mem1_1 { - status = "okay"; -}; - &pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; + power_key: power-key { + samsung,pins = "gpx0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - s2mps11_irq: s2mps11-irq { - samsung,pins = "gpx0-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; @@ -584,45 +417,3 @@ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; - -&tmu_cpu0 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_gpu { - vtmu-supply = <&ldo7_reg>; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -/* usbdrd_dwc3_1 mode customized in each board */ - -&usbdrd3_0 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; - -&usbdrd3_1 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts index 92bd2c6f7631..7eafad333bdb 100644 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts @@ -56,7 +56,7 @@ samsung,spi-feedback-delay = <0>; }; - partition@00000 { + partition@0 { label = "BootLoader"; reg = <0x60000 0x80000>; read-only; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 7a00be7ea6d7..9c3c75ae5e48 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -196,7 +196,7 @@ clock-names = "watchdog"; }; - gmac: ethernet@00230000 { + gmac: ethernet@230000 { compatible = "snps,dwmac-3.70a", "snps,dwmac"; reg = <0x00230000 0x8000>; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 0389e8a10d0b..a5007f182bc4 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -29,7 +29,7 @@ }; soc: soc { - sysram@02020000 { + sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x54000>; #address-cells = <1>; @@ -134,6 +134,7 @@ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; phy-names = "usb2-phy", "usb3-phy"; + snps,dis_u3_susphy_quirk; }; }; @@ -154,6 +155,7 @@ reg = <0x12400000 0x10000>; phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; phy-names = "usb2-phy", "usb3-phy"; + snps,dis_u3_susphy_quirk; }; }; diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi index 8613944ea5c5..6a9fdc0760f0 100644 --- a/arch/arm/boot/dts/ge863-pro3.dtsi +++ b/arch/arm/boot/dts/ge863-pro3.dtsi @@ -50,7 +50,7 @@ reg = <0x0 0x7c0000>; }; - root@07c0000 { + root@7c0000 { label = "root"; reg = <0x7c0000 0x7840000>; }; diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index b9b07d0895cf..cb5c925bd597 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -142,6 +142,12 @@ groups = "idegrp"; }; }; + tvc_default_pins: pinctrl-tvc { + mux { + function = "tvc"; + groups = "tvcgrp"; + }; + }; }; }; @@ -348,5 +354,20 @@ memcpy-bus-width = <32>; #dma-cells = <2>; }; + + display-controller@6a000000 { + compatible = "cortina,gemini-tvc", "faraday,tve200"; + reg = <0x6a000000 0x1000>; + interrupts = <13 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon GEMINI_RESET_TVC>; + clocks = <&syscon GEMINI_CLK_GATE_TVC>, + <&syscon GEMINI_CLK_TVC>; + clock-names = "PCLK", "TVE"; + pinctrl-names = "default"; + pinctrl-0 = <&tvc_default_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi index 9d5fd5cfefa6..f7cf4f53e764 100644 --- a/arch/arm/boot/dts/hip01.dtsi +++ b/arch/arm/boot/dts/hip01.dtsi @@ -91,14 +91,14 @@ reboot-offset = <0x4>; }; - global_timer@0a000200 { + global_timer@a000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x0a000200 0x100>; interrupts = <1 11 0xf04>; clocks = <&hisi_refclk144mhz>; }; - local_timer@0a000600 { + local_timer@a000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x0a000600 0x100>; interrupts = <1 13 0xf04>; diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts index 40a9e33c2654..ca48641d0f48 100644 --- a/arch/arm/boot/dts/hip04-d01.dts +++ b/arch/arm/boot/dts/hip04-d01.dts @@ -18,7 +18,7 @@ model = "Hisilicon D01 Development Board"; compatible = "hisilicon,hip04-d01"; - memory@00000000,10000000 { + memory@0,10000000 { device_type = "memory"; reg = <0x00000000 0x10000000 0x00000000 0xc0000000>, <0x00000004 0xc0000000 0x00000003 0x40000000>; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 6c712a97e1fe..50d3f8426da1 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -39,7 +39,7 @@ compatible = "simple-bus"; ranges; - timer0: timer@00002000 { + timer0: timer@2000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00002000 0x1000>; /* timer00 & timer01 */ @@ -48,7 +48,7 @@ status = "disabled"; }; - timer1: timer@00a29000 { + timer1: timer@a29000 { /* * Only used in NORMAL state, not available ins * SLOW or DOZE state. @@ -62,7 +62,7 @@ status = "disabled"; }; - timer2: timer@00a2a000 { + timer2: timer@a2a000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00a2a000 0x1000>; /* timer20 & timer21 */ @@ -71,7 +71,7 @@ status = "disabled"; }; - timer3: timer@00a2b000 { + timer3: timer@a2b000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00a2b000 0x1000>; /* timer30 & timer31 */ @@ -80,7 +80,7 @@ status = "disabled"; }; - timer4: timer@00a81000 { + timer4: timer@a81000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00a81000 0x1000>; /* timer30 & timer31 */ @@ -89,7 +89,7 @@ status = "disabled"; }; - uart0: uart@00b00000 { + uart0: uart@b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b00000 0x1000>; interrupts = <0 49 4>; @@ -98,7 +98,7 @@ status = "disabled"; }; - uart1: uart@00006000 { + uart1: uart@6000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00006000 0x1000>; interrupts = <0 50 4>; @@ -107,7 +107,7 @@ status = "disabled"; }; - uart2: uart@00b02000 { + uart2: uart@b02000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b02000 0x1000>; interrupts = <0 51 4>; @@ -116,7 +116,7 @@ status = "disabled"; }; - uart3: uart@00b03000 { + uart3: uart@b03000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b03000 0x1000>; interrupts = <0 52 4>; @@ -125,7 +125,7 @@ status = "disabled"; }; - uart4: uart@00b04000 { + uart4: uart@b04000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb04000 0x1000>; interrupts = <0 53 4>; @@ -199,7 +199,7 @@ status = "disabled"; }; - gpio5: gpio@004000 { + gpio5: gpio@4000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x004000 0x1000>; interrupts = <0 113 0x4>; @@ -378,7 +378,7 @@ }; }; - local_timer@00a00600 { + local_timer@a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; interrupts = <1 13 0xf01>; @@ -392,7 +392,7 @@ cache-level = <2>; }; - sysctrl: system-controller@00000000 { + sysctrl: system-controller@0 { compatible = "hisilicon,sysctrl", "syscon"; reg = <0x00000000 0x1000>; }; @@ -404,7 +404,7 @@ mask = <0xdeadbeef>; }; - cpuctrl@00a22000 { + cpuctrl@a22000 { compatible = "hisilicon,cpuctrl"; #address-cells = <1>; #size-cells = <1>; @@ -489,7 +489,7 @@ clocks = <&clock HIX5HD2_SATA_CLK>; }; - ir: ir@001000 { + ir: ir@1000 { compatible = "hisilicon,hix5hd2-ir"; reg = <0x001000 0x1000>; interrupts = <0 47 4>; diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi index 38d712be5685..20f6565c337d 100644 --- a/arch/arm/boot/dts/imx1.dtsi +++ b/arch/arm/boot/dts/imx1.dtsi @@ -40,7 +40,7 @@ spi1 = &cspi2; }; - aitc: aitc-interrupt-controller@00223000 { + aitc: aitc-interrupt-controller@223000 { compatible = "fsl,imx1-aitc", "fsl,avic"; interrupt-controller; #interrupt-cells = <1>; @@ -69,14 +69,14 @@ interrupt-parent = <&aitc>; ranges; - aipi@00200000 { + aipi@200000 { compatible = "fsl,aipi-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x00200000 0x10000>; ranges; - gpt1: timer@00202000 { + gpt1: timer@202000 { compatible = "fsl,imx1-gpt"; reg = <0x00202000 0x1000>; interrupts = <59>; @@ -85,7 +85,7 @@ clock-names = "ipg", "per"; }; - gpt2: timer@00203000 { + gpt2: timer@203000 { compatible = "fsl,imx1-gpt"; reg = <0x00203000 0x1000>; interrupts = <58>; @@ -94,7 +94,7 @@ clock-names = "ipg", "per"; }; - fb: fb@00205000 { + fb: fb@205000 { compatible = "fsl,imx1-fb"; reg = <0x00205000 0x1000>; interrupts = <14>; @@ -105,7 +105,7 @@ status = "disabled"; }; - uart1: serial@00206000 { + uart1: serial@206000 { compatible = "fsl,imx1-uart"; reg = <0x00206000 0x1000>; interrupts = <30 29 26>; @@ -115,7 +115,7 @@ status = "disabled"; }; - uart2: serial@00207000 { + uart2: serial@207000 { compatible = "fsl,imx1-uart"; reg = <0x00207000 0x1000>; interrupts = <24 23 20>; @@ -125,7 +125,7 @@ status = "disabled"; }; - pwm: pwm@00208000 { + pwm: pwm@208000 { #pwm-cells = <2>; compatible = "fsl,imx1-pwm"; reg = <0x00208000 0x1000>; @@ -135,7 +135,7 @@ clock-names = "ipg", "per"; }; - dma: dma@00209000 { + dma: dma@209000 { compatible = "fsl,imx1-dma"; reg = <0x00209000 0x1000>; interrupts = <61 60>; @@ -145,7 +145,7 @@ #dma-cells = <1>; }; - uart3: serial@0020a000 { + uart3: serial@20a000 { compatible = "fsl,imx1-uart"; reg = <0x0020a000 0x1000>; interrupts = <54 4 1>; @@ -156,14 +156,14 @@ }; }; - aipi@00210000 { + aipi@210000 { compatible = "fsl,aipi-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x00210000 0x10000>; ranges; - cspi1: cspi@00213000 { + cspi1: cspi@213000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx1-cspi"; @@ -175,7 +175,7 @@ status = "disabled"; }; - i2c: i2c@00217000 { + i2c: i2c@217000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx1-i2c"; @@ -185,7 +185,7 @@ status = "disabled"; }; - cspi2: cspi@00219000 { + cspi2: cspi@219000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx1-cspi"; @@ -197,20 +197,20 @@ status = "disabled"; }; - clks: ccm@0021b000 { + clks: ccm@21b000 { compatible = "fsl,imx1-ccm"; reg = <0x0021b000 0x1000>; #clock-cells = <1>; }; - iomuxc: iomuxc@0021c000 { + iomuxc: iomuxc@21c000 { compatible = "fsl,imx1-iomuxc"; reg = <0x0021c000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges; - gpio1: gpio@0021c000 { + gpio1: gpio@21c000 { compatible = "fsl,imx1-gpio"; reg = <0x0021c000 0x100>; interrupts = <11>; @@ -220,7 +220,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio@0021c100 { + gpio2: gpio@21c100 { compatible = "fsl,imx1-gpio"; reg = <0x0021c100 0x100>; interrupts = <12>; @@ -230,7 +230,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio@0021c200 { + gpio3: gpio@21c200 { compatible = "fsl,imx1-gpio"; reg = <0x0021c200 0x100>; interrupts = <13>; @@ -240,7 +240,7 @@ #interrupt-cells = <2>; }; - gpio4: gpio@0021c300 { + gpio4: gpio@21c300 { compatible = "fsl,imx1-gpio"; reg = <0x0021c300 0x100>; interrupts = <62>; @@ -252,7 +252,7 @@ }; }; - weim: weim@00220000 { + weim: weim@220000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx1-weim"; @@ -269,7 +269,7 @@ status = "disabled"; }; - esram: esram@00300000 { + esram: esram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x20000>; }; diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts index db39bd6b8e00..0f053721d80f 100644 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts @@ -64,7 +64,7 @@ &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 20>; + cd-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index c52692821fb1..2d15ce72d006 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -135,7 +135,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks 129>; @@ -295,6 +295,14 @@ status = "okay"; }; +&tsc { + status = "okay"; +}; + +&tscadc { + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index d2a91976e67f..ae078341fb60 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -143,7 +143,7 @@ pinctrl-0 = <&i2c0_pins_a>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi index 581e85f4fd4c..49ab40838e69 100644 --- a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi +++ b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi @@ -148,7 +148,7 @@ pinctrl-0 = <&i2c0_pins_a>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 5309bb90d7d5..7f5b80402c54 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -194,7 +194,7 @@ pinctrl-0 = <&i2c0_pins_a>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index dbfb8aab505f..22aa025cab1e 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -137,7 +137,7 @@ }; i2c0: i2c@80058000 { - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 0ebbc83852d0..152621ea37db 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -1,13 +1,43 @@ /* * Copyright 2012 Shawn Guo <shawn.guo@linaro.org> - * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -45,82 +75,69 @@ status = "disabled"; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_2p5v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; - reg_3p3v: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_can_xcvr: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_flexcan_xcvr_pins>; - }; + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&tx28_flexcan_xcvr_pins>; + }; - reg_lcd: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_lcd: regulator-lcd-power { + compatible = "regulator-fixed"; + regulator-name = "LCD POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_lcd_reset: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "LCD RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - startup-delay-us = <300000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; + reg_lcd_reset: regulator-lcd-reset { + compatible = "regulator-fixed"; + regulator-name = "LCD RESET"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; }; clocks { @@ -298,7 +315,7 @@ clock-frequency = <400000>; status = "okay"; - sgtl5000: sgtl5000@0a { + sgtl5000: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_2p5v>; @@ -312,7 +329,7 @@ pinctrl-names = "default"; pinctrl-0 = <&tx28_pca9554_pins>; interrupt-parent = <&gpio3>; - interrupts = <28 0>; + interrupts = <28 IRQ_TYPE_NONE>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -336,7 +353,7 @@ pinctrl-names = "default"; pinctrl-0 = <&tx28_tsc2007_pins>; interrupt-parent = <&gpio3>; - interrupts = <20 0>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; ti,x-plate-ohms = /bits/ 16 <660>; }; @@ -344,6 +361,8 @@ ds1339: rtc@68 { compatible = "mxim,ds1339"; reg = <0x68>; + trickle-resistor-ohms = <250>; + trickle-diode-disable; }; }; diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts index e9357131b026..ae98d6759074 100644 --- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts @@ -65,7 +65,7 @@ &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio3 24>; + cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 3747d80104f4..35955e63d6c5 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -52,7 +52,7 @@ }; }; - tzic: tz-interrupt-controller@0fffc000 { + tzic: tz-interrupt-controller@fffc000 { compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic"; interrupt-controller; #interrupt-cells = <1>; @@ -443,6 +443,7 @@ clocks = <&clks IMX5_CLK_SDMA_GATE>, <&clks IMX5_CLK_SDMA_GATE>; clock-names = "ipg", "ahb"; + #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; }; diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts index a5e6091c8729..3e1846a64d93 100644 --- a/arch/arm/boot/dts/imx51-apf51dev.dts +++ b/arch/arm/boot/dts/imx51-apf51dev.dts @@ -16,7 +16,7 @@ model = "Armadeus Systems APF51Dev docking/development board"; compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; - backlight@bl1{ + backlight { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; compatible = "gpio-backlight"; @@ -24,7 +24,7 @@ default-on; }; - display@di1 { + disp1 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "bgr666"; pinctrl-names = "default"; @@ -51,7 +51,7 @@ port { display_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; + remote-endpoint = <&ipu_di0_disp1>; }; }; }; @@ -120,7 +120,7 @@ pinctrl-0 = <&pinctrl_hog>; imx51-apf51dev { - pinctrl_backlight: bl1grp { + pinctrl_backlight: backlightgrp { fsl,pins = < MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5 >; @@ -218,6 +218,6 @@ }; }; -&ipu_di0_disp0 { +&ipu_di0_disp1 { remote-endpoint = <&display_in>; }; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 873cf242679c..2a694c5cc8ae 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -39,7 +39,7 @@ }; }; - display0: display@di0 { + display1: disp1 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "rgb24"; pinctrl-names = "default"; @@ -61,12 +61,12 @@ port { display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; + remote-endpoint = <&ipu_di0_disp1>; }; }; }; - display1: display@di1 { + display2: disp2 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "rgb565"; pinctrl-names = "default"; @@ -93,7 +93,7 @@ port { display1_in: endpoint { - remote-endpoint = <&ipu_di1_disp1>; + remote-endpoint = <&ipu_di1_disp2>; }; }; }; @@ -337,7 +337,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_clkcodec>; @@ -348,11 +348,11 @@ }; }; -&ipu_di0_disp0 { +&ipu_di0_disp1 { remote-endpoint = <&display0_in>; }; -&ipu_di1_disp1 { +&ipu_di1_disp2 { remote-endpoint = <&display1_in>; }; diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts index ca1cc5eca80f..564233e97412 100644 --- a/arch/arm/boot/dts/imx51-ts4800.dts +++ b/arch/arm/boot/dts/imx51-ts4800.dts @@ -50,7 +50,7 @@ power-supply = <&backlight_reg>; }; - display0: display@di0 { + display1: disp1 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "rgb24"; pinctrl-names = "default"; @@ -71,9 +71,9 @@ }; }; - port@0 { + port { display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; + remote-endpoint = <&ipu_di0_disp1>; }; }; }; @@ -107,7 +107,7 @@ }; }; -&ipu_di0_disp0 { +&ipu_di0_disp1 { remote-endpoint = <&display0_in>; }; diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts new file mode 100644 index 000000000000..49be0e1c812d --- /dev/null +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -0,0 +1,834 @@ +/* + * Copyright (C) 2017 Zodiac Inflight Innovations + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx51.dtsi" +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + model = "ZII RDU1 Board"; + compatible = "zii,imx51-rdu1", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + aliases { + mdio-gpio0 = &mdio_gpio; + rtc0 = &ds1341; + }; + + clk_26M_osc: 26M_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_26M_osc_gate: 26M_gate { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_clk26mhz>; + clocks = <&clk_26M_osc>; + #clock-cells = <0>; + enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + }; + + clk_26M_usb: usbhost_gate { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbgate26mhz>; + clocks = <&clk_26M_osc_gate>; + #clock-cells = <0>; + enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + }; + + clk_26M_snd: snd_gate { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sndgate26mhz>; + clocks = <&clk_26M_osc_gate>; + #clock-cells = <0>; + enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + }; + + reg_5p0v_main: regulator-5p0v-main { + compatible = "regulator-fixed"; + regulator-name = "5V_MAIN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + disp0 { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp1>; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu_di0_disp1>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel { + /* no compatible here, bootloader will patch in correct one */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + power-supply = <®_3p3v>; + enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + i2c_gpio: i2c-gpio { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swi2c>; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */ + <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,delay-us = <50>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clk_26M_snd>; + VDDA-supply = <&vdig_reg>; + VDDIO-supply = <&vvideo_reg>; + #sound-dai-cells = <0>; + }; + }; + + spi_gpio: spi-gpio { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiospi0>; + status = "okay"; + + gpio-sck = <&gpio4 15 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio4 12 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio4 11 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; + + eeprom@0 { + compatible = "eeprom-93xx46"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cs-high; + data-size = <8>; + }; + }; + + mdio_gpio: mdio-gpio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swmdio>; + gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */ + <&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */ + + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&fec>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "netaux"; + }; + + port@3 { + reg = <3>; + label = "netright"; + }; + + port@4 { + reg = <4>; + label = "netleft"; + }; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "RDU1 audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_codec>; + simple-audio-card,frame-master = <&sound_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT"; + simple-audio-card,aux-devs = <&tpa6130a2>; + + sound_cpu: simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + + sound_codec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clk_26M_snd>; + }; + }; + + usbh1phy: usbphy1 { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1phy>; + clocks = <&clk_26M_usb>; + clock-names = "main_clk"; + reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + vcc-supply = <&vusb_reg>; + }; + + usbh2phy: usbphy2 { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2phy>; + clocks = <&clk_26M_usb>; + clock-names = "main_clk"; + reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + vcc-supply = <&vusb_reg>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(2) | + IMX_AUDMUX_V2_PTCR_TCSEL(2) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + aud3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(1) + >; + }; +}; + +&cpu { + cpu-supply = <&sw1_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + spi-max-frequency = <6000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x0 0x0 0x3f83f8 0x0>; + + sysled0 { + reg = <3>; + label = "system:green:status"; + linux,default-trigger = "default-on"; + }; + + sysled1 { + reg = <4>; + label = "system:green:act"; + linux,default-trigger = "heartbeat"; + }; + }; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <25000000>; + reg = <1>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + phy-supply = <&vgen3_reg>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; + + tpa6130a2: amp@60 { + compatible = "ti,tpa6130a2"; + reg = <0x60>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ampgpio>; + power-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_3p3v>; + }; + + ds1341: rtc@68 { + compatible = "maxim,ds1341"; + reg = <0x68>; + }; + + /* touch nodes default disabled, bootloader will enable the right one */ + + touchscreen@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + }; + + touchscreen@4c { + compatible = "atmel,maxtouch"; + reg = <0x4c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + }; + + touchscreen@20 { + compatible = "syna,rmi4_i2c"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <2>; + }; + + rmi4-f11@11 { + reg = <0x11>; + touch-inverted-y; + touch-swapped-x-y; + syna,sensor-type = <1>; + }; + }; + +}; + +&ipu_di0_disp1 { + remote-endpoint = <&display_in>; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + dr_mode = "host"; + phy_type = "ulpi"; + fsl,usbphy = <&usbh1phy>; + disable-over-current; + vbus-supply = <®_5p0v_main>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2>; + dr_mode = "host"; + phy_type = "ulpi"; + fsl,usbphy = <&usbh2phy>; + disable-over-current; + vbus-supply = <®_5p0v_main>; + status = "okay"; +}; + +&usbphy0 { + vcc-supply = <&vusb_reg>; +}; + +&usbotg { + dr_mode = "host"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <®_5p0v_main>; + status = "okay"; +}; + +&iomuxc { + pinctrl_ampgpio: ampgpiogrp { + fsl,pins = < + MX51_PAD_GPIO1_9__GPIO1_9 0x5e + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5 + MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x85 + MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5 + MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x85 + >; + }; + + pinctrl_clk26mhz: clk26mhzgrp { + fsl,pins = < + MX51_PAD_DI1_PIN12__GPIO3_1 0x85 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5 + MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180 + MX51_PAD_EIM_EB3__FEC_RDATA1 0x180 + MX51_PAD_EIM_CS2__FEC_RDATA2 0x180 + MX51_PAD_EIM_CS3__FEC_RDATA3 0x180 + MX51_PAD_EIM_CS4__FEC_RX_ER 0x180 + MX51_PAD_NANDF_D11__FEC_RX_DV 0x2084 + MX51_PAD_EIM_CS5__FEC_CRS 0x180 + MX51_PAD_NANDF_RB2__FEC_COL 0x2180 + MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x2180 + MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004 + MX51_PAD_NANDF_CS3__FEC_MDC 0x2004 + MX51_PAD_NANDF_D8__FEC_TDATA0 0x2180 + MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004 + MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004 + MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 + MX51_PAD_EIM_A20__GPIO2_14 0x85 + >; + }; + + pinctrl_gpiospi0: gpiospi0grp { + fsl,pins = < + MX51_PAD_CSI2_D18__GPIO4_11 0x85 + MX51_PAD_CSI2_D19__GPIO4_12 0x85 + MX51_PAD_CSI2_HSYNC__GPIO4_14 0x85 + MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x85 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_ipu_disp1: ipudisp1grp { + fsl,pins = < + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 + MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX51_PAD_DI1_D0_CS__GPIO3_3 0x85 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_4__GPIO1_4 0x1e0 + MX51_PAD_GPIO1_8__GPIO1_8 0x21e2 + >; + }; + + pinctrl_sndgate26mhz: sndgate26mhzgrp { + fsl,pins = < + MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 + >; + }; + + pinctrl_swi2c: swi2cgrp { + fsl,pins = < + MX51_PAD_GPIO1_2__GPIO1_2 0xc5 + MX51_PAD_DI1_D1_CS__GPIO3_4 0x400001f5 + >; + }; + + pinctrl_swmdio: swmdiogrp { + fsl,pins = < + MX51_PAD_NANDF_D14__GPIO3_26 0x21e6 + MX51_PAD_NANDF_D15__GPIO3_25 0x21e6 + >; + }; + + pinctrl_ts: tsgrp { + fsl,pins = < + MX51_PAD_CSI1_D8__GPIO3_12 0x85 + MX51_PAD_CSI1_D9__GPIO3_13 0x85 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + MX51_PAD_UART1_RTS__UART1_RTS 0x1c4 + MX51_PAD_UART1_CTS__UART1_CTS 0x1c4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0xc5 + MX51_PAD_UART2_TXD__UART2_TXD 0xc5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_EIM_D25__UART3_RXD 0x1c5 + MX51_PAD_EIM_D26__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usbgate26mhz: usbgate26mhzgrp { + fsl,pins = < + MX51_PAD_DISP2_DAT6__GPIO1_19 0x85 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX51_PAD_USBH1_STP__USBH1_STP 0x0 + MX51_PAD_USBH1_CLK__USBH1_CLK 0x0 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x0 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x0 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x0 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x0 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x0 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x0 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x0 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x0 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x0 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x0 + >; + }; + + pinctrl_usbh1phy: usbh1phygrp { + fsl,pins = < + MX51_PAD_NANDF_D0__GPIO4_8 0x85 + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX51_PAD_EIM_A26__USBH2_STP 0x0 + MX51_PAD_EIM_A24__USBH2_CLK 0x0 + MX51_PAD_EIM_A25__USBH2_DIR 0x0 + MX51_PAD_EIM_A27__USBH2_NXT 0x0 + MX51_PAD_EIM_D16__USBH2_DATA0 0x0 + MX51_PAD_EIM_D17__USBH2_DATA1 0x0 + MX51_PAD_EIM_D18__USBH2_DATA2 0x0 + MX51_PAD_EIM_D19__USBH2_DATA3 0x0 + MX51_PAD_EIM_D20__USBH2_DATA4 0x0 + MX51_PAD_EIM_D21__USBH2_DATA5 0x0 + MX51_PAD_EIM_D22__USBH2_DATA6 0x0 + MX51_PAD_EIM_D23__USBH2_DATA7 0x0 + >; + }; + + pinctrl_usbh2phy: usbh2phygrp { + fsl,pins = < + MX51_PAD_NANDF_D1__GPIO4_7 0x85 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 1ee1d542d9ad..378be720b3c7 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -148,14 +148,14 @@ ipu_di0: port@2 { reg = <2>; - ipu_di0_disp0: endpoint { + ipu_di0_disp1: endpoint { }; }; ipu_di1: port@3 { reg = <3>; - ipu_di1_disp1: endpoint { + ipu_di1_disp2: endpoint { }; }; }; diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index 4347a321c782..e48525763b1b 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@ -16,7 +16,7 @@ model = "Aries/DENX M53EVK"; compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53"; - display1: display@di1 { + display1: disp1 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "bgr666"; pinctrl-names = "default"; @@ -150,7 +150,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p2v>; @@ -183,7 +183,7 @@ >; }; - led_pin_gpio: led_gpio@0 { + led_pin_gpio: led_gpio { fsl,pins = < MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts index df705ba48897..296dd74fc246 100644 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts @@ -30,7 +30,7 @@ power-supply = <®_backlight>; }; - disp1: display@disp1 { + disp1: disp1 { compatible = "fsl,imx-parallel-display"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_disp1_1>; diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts new file mode 100644 index 000000000000..cce959438a79 --- /dev/null +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -0,0 +1,1042 @@ +/* + * Copyright 2014 General Electric Company + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx53.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "General Electric CS ONE"; + compatible = "ge,imx53-cpuvo", "fsl,imx53"; + + aliases { + spi0 = &cspi; + spi1 = &ecspi1; + spi2 = &ecspi2; + }; + + chosen { + stdout-path = "&uart1:115200n8"; + }; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x20000000>, + <0xb0000000 0x20000000>; + }; + + cko2_11M: sgtl-clock-cko2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + sgtlsound: sound { + compatible = "fsl,imx53-cpuvo-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx53-cpuvo-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <6>; + }; + + reg_sgtl5k: regulator-sgtl5k { + compatible = "regulator-fixed"; + regulator-name = "regulator-sgtl5k"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-0 = <&pinctrl_usb_otg_vbus>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usbh2_vbus: regulator-usbh2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2_vbus>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbh3_vbus: regulator-usbh3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh3_vbus>; + gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + pwm_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 50000>; + brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35 + 38 40 43 45 48 51 53 56 58 61 63 66 68 71 + 73 76 79 81 84 86 89 91 94 96 99 102 104 + 107 109 112 114 117 119 122 124 127 130 + 132 135 137 140 142 145 147 150 153 155 + 158 160 163 165 168 170 173 175 178 181 + 183 186 188 191 193 196 198 201 204 206 + 209 211 214 216 219 221 224 226 229 232 + 234 237 239 242 244 247 249 252 255>; + default-brightness-level = <0>; + enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "pwm-leds"; + + alarm-brightness { + pwms = <&pwm1 0 100000>; + max-brightness = <255>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + active-delay = <100>; + inactive-delay = <10>; + wait-delay = <100>; + }; + + power-gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + power-button { + label = "Power button"; + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_POWER>; + }; + }; + + touch-lock-key { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + touch-lock-button { + label = "Touch lock button"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_F12>; + }; + }; + + usbphy2: usbphy2 { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; + clock-names = "main_clk"; + clock-frequency = <24000000>; + clocks = <&clks IMX5_CLK_CKO2>; + assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; + assigned-clock-parents = <&clks IMX5_CLK_OSC>; + }; + + usbphy3: usbphy3 { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; + clock-names = "main_clk"; + + clock-frequency = <24000000>; + clocks = <&clks IMX5_CLK_CKO2>; + assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; + assigned-clock-parents = <&clks IMX5_CLK_OSC>; + }; + + panel-lvds0 { + compatible = "nvd,9128"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&cpu0 { + /* CPU rated to 1GHz, not 1.2GHz as per the default settings */ + operating-points = < + /* kHz uV */ + 166666 850000 + 400000 900000 + 800000 1050000 + 1000000 1200000 + >; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW + &gpio4 10 GPIO_ACTIVE_LOW + &gpio4 11 GPIO_ACTIVE_LOW + &gpio4 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + compatible = "ge,achc"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + + spidev1: spi@1 { + compatible = "ge,achc"; + reg = <1>; + spi-max-frequency = <1000000>; + }; + + gpioxra0: gpio@2 { + compatible = "exar,xra1403"; + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <1000000>; + }; + + gpioxra1: gpio@3 { + compatible = "exar,xra1403"; + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <1000000>; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-chipselects = <1>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + status = "okay"; + + da9053@0 { + compatible = "dlg,da9053-aa"; + reg = <0>; + interrupt-parent = <&gpio3>; + interrupts = <12 0x8>; + spi-max-frequency = <1000000>; + + regulators { + buck1_reg: buck1 { + regulator-name = "BUCKCORE"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2075000>; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "BUCKPRO"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2075000>; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "BUCKMEM"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + buck4_reg: buck4 { + regulator-name = "BUCKPERI"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "ldo1_1v3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "ldo2_1v3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "ldo3_3v3"; + regulator-min-microvolt = <1725000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "ldo4_2v775"; + regulator-min-microvolt = <1725000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "ldo5_3v3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "ldo6_1v3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "ldo7_2v75"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "ldo8_1v8"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + + ldo9_reg: ldo9 { + regulator-name = "ldo9_1v5"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <3650000>; + regulator-always-on; + }; + + ldo10_reg: ldo10 { + regulator-name = "ldo10_1v3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + }; + }; + }; + +}; + +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3>; + bus-width = <8>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9547"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + reset-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; + + i2c4: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + VDDA-supply = <®_sgtl5k>; + VDDIO-supply = <®_sgtl5k>; + clocks = <&cko2_11M>; + status = "okay"; + }; + }; + + i2c5: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + + temp@48 { + compatible = "ti,tmp112"; + reg = <0x48>; + }; + + mma8453q: accelerometer@1c { + compatible = "fsl,mma8453"; + reg = <0x1c>; + interrupt-parent = <&gpio1>; + interrupts = <6 0>; + interrupt-names = "INT1"; + }; + + mpl3115: pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; + }; + + i2c6: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c8: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c9: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c10: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + i2c11: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + status = "okay"; + + touchscreen@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpio5>; + interrupts = <4 0x8>; + }; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + status = "okay"; + + port@2 { + reg = <2>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + dr_mode = "otg"; + phy_type = "utmi"; + vbus-supply = <®_usb_otg_vbus>; + pinctrl-0 = <&pinctrl_usb_otg>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_vbus>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2>; + phy_type = "ulpi"; + dr_mode = "host"; + fsl,usbphy = <&usbphy2>; + vbus-supply = <®_usbh2_vbus>; + status = "okay"; +}; + +&usbh3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh3>; + phy_type = "ulpi"; + dr_mode = "host"; + vbus-supply = <®_usbh3_vbus>; + fsl,usbphy = <&usbphy3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_rev6>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x400 + MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x400 + MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x400 + MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x400 + MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x400 + MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x400 + MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x400 + MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x400 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x400 + MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x400 + MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x400 + /* ECSPI1_SS0, must treat as GPIO for EzPort */ + MX53_PAD_DISP0_DAT23__GPIO5_17 0x400 + MX53_PAD_KEY_COL2__GPIO4_10 0x0 + MX53_PAD_KEY_ROW2__GPIO4_11 0x0 + MX53_PAD_KEY_COL3__GPIO4_12 0x0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x0 + MX53_PAD_EIM_OE__ECSPI2_MISO 0x0 + MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x0 + MX53_PAD_EIM_RW__GPIO2_26 0x0 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x0 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x0 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x0 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x0 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x0 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x0 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x0 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x0 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x0 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x0 + >; + }; + + pinctrl_hog_rev6: hoggrp { + fsl,pins = < + /* CKO2 */ + MX53_PAD_GPIO_3__CCM_CLKO2 0x4 + /* DEFIB_SYNC_MARKER_IN_IRQ */ + MX53_PAD_GPIO_5__GPIO1_5 0x0 + /* ACCELEROMETER_DATA_RDY_N */ + MX53_PAD_GPIO_6__GPIO1_6 0x0 + /* TEMPERATURE_ALERT_N */ + MX53_PAD_GPIO_7__GPIO1_7 0x0 + /* BAROMETRIC_PRESSURE_DATA_RDY_N */ + MX53_PAD_GPIO_8__GPIO1_8 0x0 + /* DOCKING_I2C_INTERFACE_IRQ_N */ + MX53_PAD_PATA_DATA4__GPIO2_4 0x0 + /* PWR_OUT_TO_DOCK_FAULT_N */ + MX53_PAD_PATA_DATA5__GPIO2_5 0x0 + /* ENABLE_PWR_TO_DOCK_N */ + MX53_PAD_PATA_DATA6__GPIO2_6 0x0 + /* HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */ + MX53_PAD_PATA_DATA7__GPIO2_7 0x0 + /* REMOTE_ON_REQUEST_FROM_DOCKING_CONNECTOR_IS_ACTIVE_N */ + MX53_PAD_PATA_DATA12__GPIO2_12 0x0 + /* DOCK_PRESENT_N */ + MX53_PAD_PATA_DATA13__GPIO2_13 0x0 + /* ECG_MARKER_IN_FROM_DOCKING_CONNECTOR_IRQ */ + MX53_PAD_PATA_DATA14__GPIO2_14 0x0 + /* ENABLE_ECG_MARKER_INTERFACE_TO_DOCKING_CONNECTOR */ + MX53_PAD_PATA_DATA15__GPIO2_15 0x0 + /* RESET_IMX535_ETHERNET_PHY_N */ + MX53_PAD_EIM_A22__GPIO2_16 0x0 + /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */ + MX53_PAD_EIM_A21__GPIO2_17 0x0 + /* RESET_I2C1_BUS_SEGMENT_MUX_N */ + MX53_PAD_EIM_A20__GPIO2_18 0x0 + /* RESET_IMX535_USB_HOST3_PHY_N */ + MX53_PAD_EIM_A19__GPIO2_19 0x0 + /* ESDHC3_EMMC_NAND_RST_N */ + MX53_PAD_EIM_A18__GPIO2_20 0x0 + /* LCD_AND_UI_INTERFACE_PWR_FAULT_N */ + MX53_PAD_EIM_A17__GPIO2_21 0x0 + /* POWER_DOWN_LVDS0_DESERIALIZER_N */ + MX53_PAD_EIM_A16__GPIO2_22 0x0 + /* POWER_DOWN_LVDS1_DESERIALIZER_N */ + MX53_PAD_EIM_LBA__GPIO2_27 0x0 + /* RESET_DP0_TRANSMITTER_N */ + MX53_PAD_EIM_EB0__GPIO2_28 0x0 + /* RESET_DP1_TRANSMITTER_N */ + MX53_PAD_EIM_EB1__GPIO2_29 0x0 + /* ENABLE_SPDIF_AUDIO_TO_DP0 */ + MX53_PAD_EIM_DA0__GPIO3_0 0x0 + /* ENABLE_SPDIF_AUDIO_TO_DP1 */ + MX53_PAD_EIM_DA1__GPIO3_1 0x0 + /* LVDS1_MUX_CTRL */ + MX53_PAD_EIM_DA2__GPIO3_2 0x0 + /* LVDS0_MUX_CTRL */ + MX53_PAD_EIM_DA3__GPIO3_3 0x0 + /* DP1_TRANSMITTER_IRQ */ + MX53_PAD_EIM_DA4__GPIO3_4 0x0 + /* DP0_TRANSMITTER_IRQ */ + MX53_PAD_EIM_DA5__GPIO3_5 0x0 + /* USB_RESET_N */ + MX53_PAD_EIM_DA6__GPIO3_6 0x0 + /* ENABLE_BATTERY_CHARGER */ + MX53_PAD_EIM_DA7__GPIO3_7 0x0 + /* SOFTWARE_CONTROLLED_PWR_CYCLE */ + MX53_PAD_EIM_DA8__GPIO3_8 0x0 + /* SOFTWARE_CONTROLLED_POWERDOWN */ + MX53_PAD_EIM_DA9__GPIO3_9 0x0 + /* DC_PWR_IN_OK */ + MX53_PAD_EIM_DA10__GPIO3_10 0x0 + /* BATT_PRESENT_N */ + MX53_PAD_EIM_DA11__GPIO3_11 0xe4 + /* PMIC_IRQ_N */ + MX53_PAD_EIM_DA12__GPIO3_12 0x0 + /* PMIC_VDD_FAULT_STATUS_N */ + MX53_PAD_EIM_DA13__GPIO3_13 0x0 + /* IMX535_ETHERNET_PHY_STATUS_IRQ_N */ + MX53_PAD_EIM_DA14__GPIO3_14 0x0 + /* NOT USED - AVAILABLE 3.3V GPIO */ + MX53_PAD_EIM_DA15__GPIO3_15 0x0 + /* NOT USED - AVAILABLE 3.3V GPIO */ + MX53_PAD_EIM_D22__GPIO3_22 0x0 + /* NOT USED - AVAILABLE 3.3V GPIO */ + MX53_PAD_EIM_D24__GPIO3_24 0x0 + /* NBP_PUMP_VALVE_PWR_ENABLE */ + MX53_PAD_EIM_D25__GPIO3_25 0x0 + /* NIBP_RESET_N */ + MX53_PAD_EIM_D26__GPIO3_26 0x0 + /* LATCHED_OVERPRESSURE_N */ + MX53_PAD_EIM_D27__GPIO3_27 0x0 + /* NBP_SBWTCLK */ + MX53_PAD_EIM_D29__GPIO3_29 0x0 + /* ENABLE_WIFI_MODULE */ + MX53_PAD_GPIO_11__GPIO4_1 0x400 + /* WIFI_MODULE_IRQ_N */ + MX53_PAD_GPIO_12__GPIO4_2 0x400 + /* ENABLE_BLUETOOTH_MODULE */ + MX53_PAD_GPIO_13__GPIO4_3 0x400 + /* RESET_IMX535_USB_HOST2_PHY_N */ + MX53_PAD_GPIO_14__GPIO4_4 0x400 + /* ONKEY_IS_DEPRESSED */ + MX53_PAD_KEY_ROW3__GPIO4_13 0x0 + /* UNUSED_GPIO_TO_ALARM_LIGHT_BOARD */ + MX53_PAD_EIM_WAIT__GPIO5_0 0x0 + /* DISPLAY_LOCK_BUTTON_IS_DEPRESSED_N */ + MX53_PAD_EIM_A25__GPIO5_2 0x0 + /* I2C_PCAP_TOUCHSCREEN_IRQ_N */ + MX53_PAD_EIM_A24__GPIO5_4 0x0 + /* NOT USED - AVAILABLE 1.8V GPIO */ + MX53_PAD_DISP0_DAT13__GPIO5_7 0x400 + /* NOT USED - AVAILABLE 1.8V GPIO */ + MX53_PAD_DISP0_DAT14__GPIO5_8 0x400 + /* NOT USED - AVAILABLE 1.8V GPIO */ + MX53_PAD_DISP0_DAT15__GPIO5_9 0x400 + /* HOST_CONTROLLED_RESET_TO_LCD_N */ + MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0 + /* HOST_CONTROLLED_RESET_TO_PCAP_N */ + MX53_PAD_CSI0_MCLK__GPIO5_19 0x0 + /* LR_SCAN_CTRL */ + MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0 + /* UD_SCAN_CTRL */ + MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0 + /* DATA_WIDTH_CTRL */ + MX53_PAD_CSI0_DAT10__GPIO5_28 0x0 + /* BACKLIGHT_ENABLE */ + MX53_PAD_CSI0_DAT11__GPIO5_29 0x0 + /* MED_USB_PORT_1_HOST_SELECT */ + MX53_PAD_EIM_A23__GPIO6_6 0x0 + /* MED_USB_PORT_2_HOST_SELECT */ + MX53_PAD_NANDF_CLE__GPIO6_7 0x0 + /* MED_USB_PORT_3_HOST_SELECT */ + MX53_PAD_NANDF_ALE__GPIO6_8 0x0 + /* MED_USB_PORT_4_HOST_SELECT */ + MX53_PAD_NANDF_WP_B__GPIO6_9 0x0 + /* MED_USB_PORT_5_HOST_SELECT */ + MX53_PAD_NANDF_RB0__GPIO6_10 0x0 + /* MED_USB_PORT_6_HOST_SELECT */ + MX53_PAD_NANDF_CS0__GPIO6_11 0x0 + /* MED_USB_PORT_7_HOST_SELECT */ + MX53_PAD_NANDF_WE_B__GPIO6_12 0x0 + /* MED_USB_PORT_8_HOST_SELECT */ + MX53_PAD_NANDF_RE_B__GPIO6_13 0x0 + /* MED_USB_PORT_TO_IMX_SELECT_0 */ + MX53_PAD_NANDF_CS1__GPIO6_14 0x0 + /* MED_USB_PORT_TO_IMX_SELECT_1 */ + MX53_PAD_NANDF_CS2__GPIO6_15 0x0 + /* MED_USB_PORT_TO_IMX_SELECT_2 */ + MX53_PAD_NANDF_CS3__GPIO6_16 0x0 + /* POWER_AND_BOOT_STATUS_INDICATOR */ + MX53_PAD_PATA_INTRQ__GPIO7_2 0x1e4 + /* ACTIVATE_ALARM_LIGHT_RED */ + MX53_PAD_PATA_DIOR__GPIO7_3 0x0 + /* ACTIVATE_ALARM_LIGHT_YELLOW */ + MX53_PAD_PATA_DA_1__GPIO7_7 0x0 + /* ACTIVATE_ALARM_LIGHT_CYAN */ + MX53_PAD_PATA_DA_2__GPIO7_8 0x0 + /* RUNNING_ON_BATTERY_INDICATOR_GREEN */ + MX53_PAD_GPIO_16__GPIO7_11 0x0 + /* BATTERY_STATUS_INDICATOR_AMBER */ + MX53_PAD_GPIO_17__GPIO7_12 0x0 + /* AUDIO_ALARMS_SILENCED_INDICATOR */ + MX53_PAD_GPIO_18__GPIO7_13 0x0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D28__GPIO3_28 0x1e4 + MX53_PAD_EIM_D21__GPIO3_21 0x1e4 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_EIM_EB2__I2C2_SCL 0x400001e4 + MX53_PAD_EIM_D16__I2C2_SDA 0x400001e4 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D16__GPIO3_16 0x1e4 + MX53_PAD_EIM_EB2__GPIO2_30 0x1e4 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_EIM_D17__I2C3_SCL 0x400001e4 + MX53_PAD_EIM_D18__I2C3_SDA 0x400001e4 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D18__GPIO3_18 0x1e4 + MX53_PAD_EIM_D17__GPIO3_17 0x1e4 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX53_PAD_GPIO_9__PWM1_PWMO 0x5 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 + MX53_PAD_EIM_D23__UART3_CTS 0x1e4 + MX53_PAD_EIM_EB3__UART3_RTS 0x1e4 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 + MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4 + MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4 + >; + }; + + pinctrl_usb_otg_vbus: usb-otg-vbusgrp { + fsl,pins = < + /* USB_HS_OTG_VBUS_ENABLE */ + MX53_PAD_KEY_ROW4__GPIO4_15 0x1c4 + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + /* USB H2 */ + MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x180 + MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x180 + MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x180 + MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x180 + MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x180 + MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x180 + MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x180 + MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x180 + MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x180 + MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x180 + MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x180 + MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x5 + MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x180 + >; + }; + + pinctrl_usbh2_vbus: usbh2-vbusgrp { + fsl,pins = < + /* USB_HS_HOST2_VBUS_ENABLE */ + MX53_PAD_EIM_D31__GPIO3_31 0x0 + >; + }; + + pinctrl_usbh3_vbus: usbh3-vbusgrp { + fsl,pins = < + /* USB_HS_HOST3_VBUS_ENABLE */ + MX53_PAD_CSI0_DAT9__GPIO5_27 0x0 + >; + }; + + pinctrl_usbh3: usbh3grp { + fsl,pins = < + /* USB H3 */ + MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x180 + MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x180 + MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x180 + MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x180 + MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x180 + MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x180 + MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x180 + MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x180 + MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x5 + MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x180 + MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x180 + MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x180 + MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x180 + >; + }; + + pinctrl_usb_otg: usbotggrp { + fsl,pins = < + /* USB_OTG_FAULT_N */ + MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x180 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index 683dcbe27cbd..41a2e2a2b079 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@ -22,7 +22,7 @@ <0xb0000000 0x20000000>; }; - display0: display@di0 { + display0: disp0 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "rgb565"; pinctrl-names = "default"; @@ -172,7 +172,7 @@ >; }; - led_pin_gpio7_7: led_gpio7_7@0 { + led_pin_gpio7_7: led_gpio7_7 { fsl,pins = < MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 >; @@ -314,7 +314,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p2v>; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 33cb64fc8372..51f4a42a55e2 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -232,12 +232,12 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; }; - magnetometer: mag3110@0e { + magnetometer: mag3110@e { compatible = "fsl,mag3110"; reg = <0x0e>; }; diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts index 0ecb43d88522..7eb53e48c2f4 100644 --- a/arch/arm/boot/dts/imx53-tx53-x03x.dts +++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts @@ -1,12 +1,42 @@ /* - * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -24,7 +54,7 @@ }; soc { - display: display@di0 { + display: disp0 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "rgb24"; pinctrl-names = "default"; @@ -173,28 +203,24 @@ default-brightness-level = <50>; }; - regulators { - reg_lcd_pwr: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; + reg_lcd_pwr: regulator-lcd-pwr { + compatible = "regulator-fixed"; + regulator-name = "LCD POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; - reg_lcd_reset: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "LCD RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; + reg_lcd_reset: regulator-lcd-reset { + compatible = "regulator-fixed"; + regulator-name = "LCD RESET"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; }; }; @@ -203,7 +229,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_2v5>; @@ -228,7 +254,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc2007>; interrupt-parent = <&gpio3>; - interrupts = <26 0>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; ti,x-plate-ohms = <660>; wakeup-source; diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/imx53-tx53-x13x.dts index 3cf682a681f4..f2b2ad3ce9e5 100644 --- a/arch/arm/boot/dts/imx53-tx53-x13x.dts +++ b/arch/arm/boot/dts/imx53-tx53-x13x.dts @@ -1,6 +1,42 @@ /* - * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de> * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 at the following locations: @@ -63,82 +99,46 @@ default-brightness-level = <50>; }; - regulators { - reg_lcd_pwr0: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "LVDS0 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - reg_lcd_pwr1: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "LVDS1 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; + reg_lcd_pwr0: regulator-lvds0-pwr { + compatible = "regulator-fixed"; + regulator-name = "LVDS0 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; }; -}; -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - touchscreen2: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti2>; - interrupt-parent = <&gpio3>; - interrupts = <23 0>; - wakeup-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; - wakeup-source; + reg_lcd_pwr1: regulator-lvds1-pwr { + compatible = "regulator-fixed"; + regulator-name = "LVDS1 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; }; }; &i2c3 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_2v5>; VDDIO-supply = <®_3v3>; clocks = <&mclk>; }; - - touchscreen1: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti1>; - interrupt-parent = <&gpio3>; - interrupts = <22 0>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; }; &iomuxc { imx53-tx53-x13x { - pinctrl_i2c2: i2c2-grp1 { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - pinctrl_lvds0: lvds0grp { fsl,pins = < MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index 7807c1fa1101..71b58b6933e1 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -1,15 +1,45 @@ /* - * Copyright 2012 <LW@KARO-electronics.de> + * Copyright 2012-2017 <LW@KARO-electronics.de> * based on imx53-qsb.dts * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include "imx53.dtsi" @@ -66,61 +96,50 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2v5: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; + reg_2v5: regulator-2v5 { + compatible = "regulator-fixed"; + regulator-name = "2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; - reg_3v3: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; - reg_can_xcvr: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - }; + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + }; - reg_usbh1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usbotg_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; }; sound { @@ -208,14 +227,17 @@ phy0: ethernet-phy@0 { interrupt-parent = <&gpio2>; - interrupts = <4>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; device_type = "ethernet-phy"; }; }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-0 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; clock-frequency = <400000>; status = "okay"; @@ -225,7 +247,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ds1339>; interrupt-parent = <&gpio4>; - interrupts = <20 0>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + trickle-resistor-ohms = <250>; + trickle-diode-disable; }; }; @@ -368,15 +392,29 @@ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 - MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D21__GPIO3_21 0x400001e6 + MX53_PAD_EIM_D28__GPIO3_28 0x400001e6 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 + MX53_PAD_GPIO_3__I2C3_SCL 0x400001e4 + MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX53_PAD_GPIO_3__GPIO1_3 0x400001e6 + MX53_PAD_GPIO_6__GPIO1_6 0x400001e6 >; }; diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/imx53-voipac-bsb.dts index fc51b87ad208..25c78f19826c 100644 --- a/arch/arm/boot/dts/imx53-voipac-bsb.dts +++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts @@ -130,7 +130,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 8bf0d89cdd35..589a67c5f796 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -80,7 +80,7 @@ ports = <&ipu_di0>, <&ipu_di1>; }; - tzic: tz-interrupt-controller@0fffc000 { + tzic: tz-interrupt-controller@fffc000 { compatible = "fsl,imx53-tzic", "fsl,tzic"; interrupt-controller; #interrupt-cells = <1>; @@ -299,14 +299,14 @@ reg = <0x53f00000 0x60>; }; - usbphy0: usbphy@0 { + usbphy0: usbphy-0 { compatible = "usb-nop-xceiv"; clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; clock-names = "main_clk"; status = "okay"; }; - usbphy1: usbphy@1 { + usbphy1: usbphy-1 { compatible = "usb-nop-xceiv"; clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; clock-names = "main_clk"; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts index 0677625463d6..5f0d196495d0 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts @@ -52,7 +52,7 @@ reg = <0x10000000 0x40000000>; }; - display0: display@di0 { + display0: disp0 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx-parallel-display"; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts index 32a812b1839e..cc418cecabdb 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts @@ -32,7 +32,7 @@ }; soc { - display0: display@di0 { + display0: disp0 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "rgb24"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts index 15203f0e9725..126ff964eded 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts @@ -21,7 +21,7 @@ }; soc { - display0: display@di0 { + display0: disp0 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "rgb24"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index 26541538562c..5705ebee0595 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -88,7 +88,7 @@ }; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts index 6de83c72bd72..971f9fc39c66 100644 --- a/arch/arm/boot/dts/imx6dl-icore.dts +++ b/arch/arm/boot/dts/imx6dl-icore.dts @@ -57,3 +57,12 @@ &can2 { status = "okay"; }; + +&i2c1 { + max11801: touchscreen@48 { + compatible = "maxim,max11801"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 275c6c05219d..23e108204e1e 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -157,7 +157,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -165,7 +165,7 @@ VDDIO-supply = <®_3p3v>; }; - pmic: pf0100@08 { + pmic: pf0100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; interrupt-parent = <&gpio5>; diff --git a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts index aac42ac465b6..51a9bb9d6bc2 100644 --- a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts +++ b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,70 +42,16 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6DL Module on CoMpact TFT"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; +}; - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&ET070001DM6>; - - ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; +&backlight { + pwms = <&pwm2 0 500000 0>; + /delete-property/ turn-on-delay-ms; }; &can1 { @@ -116,14 +62,14 @@ xceiver-supply = <®_3v3>; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &kpp { status = "disabled"; }; +&lcd_panel { + compatible = "edt,etm0700g0edh6"; +}; + ®_can_xcvr { status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts new file mode 100644 index 000000000000..fc23b4d291a1 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl-tx6s-8034.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6S-8034 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034.dts b/arch/arm/boot/dts/imx6dl-tx6s-8034.dts index ff8f7b1c4282..9eb2ef17339c 100644 --- a/arch/arm/boot/dts/imx6dl-tx6s-8034.dts +++ b/arch/arm/boot/dts/imx6dl-tx6s-8034.dts @@ -1,5 +1,5 @@ /* - * Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2015-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,174 +42,15 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6S-8034 Module"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - aliases { - display = &display; - ipu1 = &ipu1; - }; - cpus { /delete-node/ cpu@1; }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_2>; - interface-pix-fmt = "rgb24"; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&vga>; - - vga: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; &ds1339 { @@ -227,11 +68,3 @@ MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ >; }; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -®_lcd0_pwr { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts new file mode 100644 index 000000000000..4101c6597721 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl-tx6s-8035.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-8035 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035.dts b/arch/arm/boot/dts/imx6dl-tx6s-8035.dts index f988950e9443..a5532ecc18c5 100644 --- a/arch/arm/boot/dts/imx6dl-tx6s-8035.dts +++ b/arch/arm/boot/dts/imx6dl-tx6s-8035.dts @@ -1,5 +1,5 @@ /* - * Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2015-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,174 +42,15 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6S-8035 Module"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - aliases { - display = &display; - ipu1 = &ipu1; - }; - cpus { /delete-node/ cpu@1; }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_2>; - interface-pix-fmt = "rgb24"; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&vga>; - - vga: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; &ds1339 { @@ -220,14 +61,6 @@ status = "disabled"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -®_lcd0_pwr { - status = "disabled"; -}; - &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts index d1f1298ec55a..67ed0452f5de 100644 --- a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts +++ b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,166 +42,9 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6U-801x Module"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; }; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts new file mode 100644 index 000000000000..d34189fc52d9 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl-tx6u-8033.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-8033 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-8033.dts b/arch/arm/boot/dts/imx6dl-tx6u-8033.dts index 4d3204a56f46..7030b2654bbd 100644 --- a/arch/arm/boot/dts/imx6dl-tx6u-8033.dts +++ b/arch/arm/boot/dts/imx6dl-tx6u-8033.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,169 +42,11 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6U-8033 Module"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_2>; - interface-pix-fmt = "rgb24"; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&vga>; - - vga: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; &ds1339 { @@ -215,14 +57,6 @@ status = "disabled"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -®_lcd0_pwr { - status = "disabled"; -}; - &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts new file mode 100644 index 000000000000..aef5fcc42904 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl-tx6u-801x.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-8030/-8010/-8012 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts b/arch/arm/boot/dts/imx6dl-tx6u-811x.dts index 5e0c6bb49f37..5342f2f5a8a8 100644 --- a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts +++ b/arch/arm/boot/dts/imx6dl-tx6u-811x.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,137 +42,9 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lvds.dtsi" / { model = "Ka-Ro electronics TX6U-811x Module"; compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_lcd0_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 0>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; -}; - -&i2c3 { - polytouch2: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti>; - interrupt-parent = <&gpio3>; - interrupts = <22 0>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; -}; - -&kpp { - status = "disabled"; /* pad conflict with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds_timing0>; - lvds_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "disabled"; - - display-timings { - native-mode = <&lvds_timing1>; - lvds_timing1: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&iomuxc { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; }; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts index b9a783f7160e..c4588fb0bf6f 100644 --- a/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts +++ b/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts @@ -1,5 +1,5 @@ /* - * Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2016-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -40,216 +40,9 @@ */ /dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" +#include "imx6dl-tx6u-811x.dts" +#include "imx6qdl-tx6-mb7.dtsi" / { - model = "Ka-Ro electronics TX6U-81xx Module on MB7 baseboard"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd0_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&i2c3 { - polytouch1: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti>; - interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; -}; - -&kpp { - status = "disabled"; /* pads partially clash with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds0_timing1>; - - lvds0_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds0_timing1: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - lvds0_timing2: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds1_timing2>; - - lvds1_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds1_timing1: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - lvds1_timing2: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&iomuxc { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; + model = "Ka-Ro electronics TX6U-8130/-8110 Module on MB7 baseboard"; }; diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts new file mode 100644 index 000000000000..aa4d4faaaec4 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts @@ -0,0 +1,22 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-wandboard-revd1.dtsi" + +/ { + model = "Wandboard i.MX6 Dual Lite Board revD1"; + compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 8475e6cc59ac..4d693a75ce98 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -60,35 +60,35 @@ }; soc { - ocram: sram@00900000 { + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips1: aips-bus@02000000 { - iomuxc: iomuxc@020e0000 { + aips1: aips-bus@2000000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6dl-iomuxc"; }; - pxp: pxp@020f0000 { + pxp: pxp@20f0000 { reg = <0x020f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; }; - epdc: epdc@020f4000 { + epdc: epdc@20f4000 { reg = <0x020f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; }; - lcdif: lcdif@020f8000 { + lcdif: lcdif@20f8000 { reg = <0x020f8000 0x4000>; interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; }; }; - aips2: aips-bus@02100000 { - i2c4: i2c@021f8000 { + aips2: aips-bus@2100000 { + i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts index 4bbfe3d61027..8b56656e53da 100644 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -76,7 +76,7 @@ }; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts index a35c7a54ad3b..27dc0fc686a9 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts @@ -77,7 +77,7 @@ }; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 60d33e99de76..40b2c67fe7af 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -76,7 +76,7 @@ }; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi index 1015e55ca8f7..b915837bbb5f 100644 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi @@ -165,7 +165,7 @@ #size-cells = <0>; reg = <0x3>; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&mclk>; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index fe6ab0aa34f9..bc7587c383f6 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -77,8 +77,7 @@ regulator-name = "regulator-pcie-power-on-gpio"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; - enable-active-high; + gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; }; reg_usb_h1_vbus: usb_h1_vbus { @@ -362,7 +361,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; - vdd-supply = <®_pcie_power_on_gpio>; + vpcie-supply = <®_pcie_power_on_gpio>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts b/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts new file mode 100644 index 000000000000..16658b76fc4e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts @@ -0,0 +1,51 @@ +/* + * Copyright 2017 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q-display5.dtsi" + +&panel { + compatible = "tianma,tm070jdhg30"; +}; + +&ldb { + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/imx6q-display5.dtsi new file mode 100644 index 000000000000..4084de43d4d9 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-display5.dtsi @@ -0,0 +1,596 @@ +/* + * Copyright 2017 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + model = "Liebherr (LWN) display5 i.MX6 Quad Board"; + compatible = "lwn,display5", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm2 0 5000000 0>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 101 102 103 104 105 106 107 108 109 + 110 111 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 128 129 + 130 131 132 133 134 135 136 137 138 139 + 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 168 169 + 170 171 172 173 174 175 176 177 178 179 + 180 181 182 183 184 185 186 187 188 189 + 190 191 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 208 209 + 210 211 212 213 214 215 216 217 218 219 + 220 221 222 223 224 225 226 227 228 229 + 230 231 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 248 249 + 250 251 252 253 254 255>; + default-brightness-level = <250>; + enable-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; + }; + + reg_lvds: regulator-lvds { + compatible = "regulator-fixed"; + regulator-name = "lvds_ppen"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lvds>; + gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbh1_vbus: usb-h1-vbus { + compatible = "regulator-fixed"; + gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-enable-ramp-delay = <300000>; + }; + + sound { + compatible = "simple-audio-card"; + label = "tfa9879-mono"; + + simple-audio-card,dai-link { + /* DAC */ + format = "i2s"; + bitclock-master = <&dailink_master>; + frame-master = <&dailink_master>; + + dailink_master: cpu { + sound-dai = <&ssi2>; + }; + codec { + sound-dai = <&codec>; + }; + }; + }; + + panel: panel-lvds0 { + backlight = <&backlight_lvds>; + power-supply = <®_lvds>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(5) | + IMX_AUDMUX_V2_PTCR_TCSEL(5) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(5) + >; + }; + + aud6 { + fsl,audmux-port = <5>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_RFSEL(8) | + IMX_AUDMUX_V2_PTCR_RCSEL(8) | + IMX_AUDMUX_V2_PTCR_TFSEL(1) | + IMX_AUDMUX_V2_PTCR_TCSEL(1) | + IMX_AUDMUX_V2_PTCR_RFSDIR | + IMX_AUDMUX_V2_PTCR_RCLKDIR | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(1) + >; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>; + status = "okay"; + + s25fl256s: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + + partition@0 { + label = "SPL (spi)"; + reg = <0x0 0x20000>; + read-only; + }; + partition@1 { + label = "u-boot (spi)"; + reg = <0x20000 0x100000>; + read-only; + }; + partition@2 { + label = "uboot-env (spi)"; + reg = <0x120000 0x10000>; + }; + partition@3 { + label = "uboot-envr (spi)"; + reg = <0x130000 0x10000>; + }; + partition@4 { + label = "linux-recovery (spi)"; + reg = <0x140000 0x800000>; + }; + partition@5 { + label = "swupdate-fitImg (spi)"; + reg = <0x940000 0x400000>; + }; + partition@6 { + label = "swupdate-initramfs (spi)"; + reg = <0xD40000 0x800000>; + }; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ðernet_phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@0 { + compatible = "marvell,88E1510"; + device_type = "ethernet-phy"; + /* Set LED0 control: */ + /* On - Link, Blink - Activity, Off - No Link */ + marvell,reg-init = <3 0x10 0 0x1011>; + max-speed = <100>; + reg = <0>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: tfa9879@6C { + #sound-dai-cells = <0>; + compatible = "nxp,tfa9879"; + reg = <0x6C>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + at24@50 { + compatible = "atmel,24c256"; + pagesize = <64>; + reg = <0x50>; + }; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pwm2 { + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + /* I2S OUTPUT AUD6*/ + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 + >; + }; + + pinctrl_backlight: dispgrp { + fsl,pins = < + /* BLEN_OUT */ + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi2_cs: ecspi2csgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 + >; + }; + + pinctrl_ecspi2_flwp: ecspi2flwpgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi3_cs: ecspi3csgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 + >; + }; + + pinctrl_ecspi3_flwp: ecspi3flwpgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_lvds: reqlvdsgrp { + fsl,pins = < + /* LVDS_PPEN_OUT */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x030b0 + >; + }; + + pinctrl_usbh1_vbus: usbh1_vbus_grp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index 33eb7f180995..f0316ea96898 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -139,7 +139,7 @@ &pinctrl_pfuze>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; interrupt-parent = <&gpio3>; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 9dbeea05a949..29adaa7c72f8 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -211,7 +211,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -322,7 +322,7 @@ reg = <0x1c>; }; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -330,7 +330,7 @@ VDDIO-supply = <®_3p3v>; }; - touchscreen: egalax_ts@04 { + touchscreen: egalax_ts@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio7>; @@ -392,127 +392,124 @@ }; &iomuxc { - imx6q-gw5400-a { - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + >; + }; - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ - >; - }; + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ + >; + }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ - >; - }; + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + >; + }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; }; }; diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts index 8f9252889971..a3269f57df2b 100644 --- a/arch/arm/boot/dts/imx6q-h100.dts +++ b/arch/arm/boot/dts/imx6q-h100.dts @@ -185,7 +185,7 @@ reg = <0x68>; }; - sgtl5000: sgtl5000@0a { + sgtl5000: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; pinctrl-names = "default"; @@ -195,7 +195,7 @@ VDDIO-supply = <®_3p3v>; }; - tc358743: tc358743@0f { + tc358743: tc358743@f { compatible = "toshiba,tc358743"; reg = <0x0f>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q-icore-rqs.dts b/arch/arm/boot/dts/imx6q-icore-rqs.dts index e451b4ceb4d8..b81f48c6a8c6 100644 --- a/arch/arm/boot/dts/imx6q-icore-rqs.dts +++ b/arch/arm/boot/dts/imx6q-icore-rqs.dts @@ -47,30 +47,6 @@ / { model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit"; compatible = "engicam,imx6-icore-rqs", "fsl,imx6q"; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx-audio-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&i2c3 { - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p8v>; - }; }; &sata { diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/imx6q-mccmon6.dts index eedbe737420c..cab36f48d5f1 100644 --- a/arch/arm/boot/dts/imx6q-mccmon6.dts +++ b/arch/arm/boot/dts/imx6q-mccmon6.dts @@ -121,7 +121,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pfuze100: pmic@08 { + pfuze100: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index d83cfb6ec598..7d7dc59507cf 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -158,7 +158,6 @@ regulator-max-microvolt = <1500000>; gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-always-on; }; reg_sata: regulator-sata { @@ -255,7 +254,7 @@ reg = <0x68>; }; - sbs_battery: bq20z75@0b { + sbs_battery: bq20z75@b { compatible = "sbs,sbs-battery"; reg = <0x0b>; sbs,i2c-retry-count = <50>; @@ -295,7 +294,7 @@ pinctrl-0 = <&pinctrl_i2c2_novena>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -447,6 +446,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie_novena>; reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts new file mode 100644 index 000000000000..1effb58f304c --- /dev/null +++ b/arch/arm/boot/dts/imx6q-pistachio.dts @@ -0,0 +1,693 @@ +/* + * Copyright (C) 2017 NutsBoard.Org + * + * Author: Wig Cheng <onlywig@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "imx6q.dtsi" + +/ { + model = "NutsBoard i.MX6 Quad Pistachio board"; + compatible = "nutsboard,imx6q-pistachio", "fsl,imx6q"; + + chosen { + stdout-path = &uart4; + }; + + memory: memory { + reg = <0x10000000 0x80000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + wlan_en_reg: regulator-wlan_en { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = <KEY_POWER>; + }; + }; + + sound { + compatible = "fsl,imx-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "audio-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000>; + brightness-levels = < + 0 /*1 2 3 4 5 6*/ 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <94>; + status = "okay"; + }; + + panel { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_1p8v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + ar1021@4d { + compatible = "microchip,ar1021-i2c"; + reg = <0x4d>; + interrupt-parent = <&gpio6>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /*pcie power*/ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /*LCD power*/ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /*backlight power*/ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /*SD3 CD pin*/ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /*codec power*/ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /*touch reset*/ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b01 /*touch irq*/ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0/*backlight pwr*/ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /*gpio 5V_1*/ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 /*gpio 5V_2*/ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /*gpio 5V_3*/ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /*gpio 5V_4*/ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /*AUX_5V_EN*/ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 /*AUX_5VB_EN*/ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 /*AUX_3V3_EN*/ + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /*I2C expander pwr*/ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + /* AR8035 reset */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x130b0 + /* AR8035 interrupt */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 + /* AR8035 pin strapping: IO voltage: pull up */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + /* AR8035 pin strapping: PHYADDR#0: pull down */ + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 + /* AR8035 pin strapping: PHYADDR#1: pull down */ + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + /* AR8035 pin strapping: MODE#1: pull up */ + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + /* AR8035 pin strapping: MODE#3: pull up */ + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + /* AR8035 pin strapping: MODE#0: pull down */ + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130b0 /*headphone det*/ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 /*microphone det*/ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x15059 /*BT_EN*/ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 + MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 + MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 + MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x15059 /*WL_EN_LDO*/ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x15059 /*WL_EN*/ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x15059 /*WL_IRQ*/ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b00 + >; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + fsl,dte-mode; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <0x5>; +}; + +&usbphy2 { + fsl,tx-d-cal = <0x5>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + keep-power-in-suspend; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + vmmc-supply = <&wlan_en_reg>; + no-1-8-v; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts index 06f492e17ca7..a3cd7afac20a 100644 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -158,7 +158,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - sgtl5000: sgtl5000@0a { + sgtl5000: sgtl5000@a { clocks = <&clks IMX6QDL_CLK_CKO>; compatible = "fsl,sgtl5000"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts index 71746edc2ee9..ac3050a835e5 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,70 +42,16 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +}; - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&ET070001DM6>; - - ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; +&backlight { + pwms = <&pwm2 0 500000 0>; + /delete-property/ turn-on-delay-ms; }; &can1 { @@ -116,14 +62,14 @@ xceiver-supply = <®_3v3>; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &kpp { status = "disabled"; }; +&lcd_panel { + compatible = "edt,etm0700g0edh6"; +}; + ®_can_xcvr { status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/imx6q-tx6q-1010.dts index f9cd21a41a79..4ee860b626ff 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1010.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1010.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,166 +42,13 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { - model = "Ka-Ro electronics TX6Q-1010 Module"; + model = "Ka-Ro electronics TX6Q-1010/-1030 Module"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; +&ipu2 { + status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts index 959ff3fb7304..a773f252816c 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,70 +42,16 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +}; - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&ET070001DM6>; - - ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; +&backlight { + pwms = <&pwm2 0 500000 0>; + /delete-property/ turn-on-delay-ms; }; &can1 { @@ -124,14 +70,14 @@ status = "disabled"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &kpp { status = "disabled"; }; +&lcd_panel { + compatible = "edt,etm0700g0edh6"; +}; + ®_can_xcvr { status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/imx6q-tx6q-1020.dts index b49133d25d80..0a4daec8d3ad 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1020.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1020.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,164 +42,11 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6Q-1020 Module"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; &ds1339 { @@ -210,14 +57,15 @@ status = "disabled"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; +&ipu2 { + status = "disabled"; }; &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; bus-width = <4>; + non-removable; no-1-8-v; fsl,wp-controller; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts b/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts new file mode 100644 index 000000000000..9ffbb0fe7df8 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q-tx6q-1036.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1036 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1036.dts b/arch/arm/boot/dts/imx6q-tx6q-1036.dts index 7c152e32758c..cb2fcb4896c6 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1036.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1036.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,169 +42,11 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" / { model = "Ka-Ro electronics TX6Q-1036 Module"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_2>; - interface-pix-fmt = "rgb24"; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&vga>; - - vga: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; &ds1339 { @@ -215,18 +57,10 @@ status = "disabled"; }; -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - &ipu2 { status = "disabled"; }; -®_lcd0_pwr { - status = "disabled"; -}; - &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; diff --git a/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts b/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts new file mode 100644 index 000000000000..d43a5d8f1749 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q-tx6q-1010.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1010/-1030 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1110.dts b/arch/arm/boot/dts/imx6q-tx6q-1110.dts index 0433e220a931..f7b0acb65352 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1110.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1110.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,141 +42,17 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lvds.dtsi" / { - model = "Ka-Ro electronics TX6Q-1110 Module"; + model = "Ka-Ro electronics TX6Q-1110/-1130 Module"; compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_lcd0_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 0>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; -}; - -&i2c3 { - polytouch1: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti>; - interrupt-parent = <&gpio3>; - interrupts = <22 0>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; }; -&kpp { - status = "disabled"; /* pad conflict with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds_timing0>; - lvds_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "disabled"; - - display-timings { - native-mode = <&lvds_timing1>; - lvds_timing1: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; +&ipu2 { + status = "disabled"; }; &sata { status = "okay"; }; - -&iomuxc { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts b/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts index d78b129d01ea..387edf2b3f96 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts @@ -1,5 +1,5 @@ /* - * Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2016-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -40,225 +40,9 @@ */ /dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" +#include "imx6q-tx6q-1110.dts" +#include "imx6qdl-tx6-mb7.dtsi" / { model = "Ka-Ro electronics TX6Q-1110/-1130 Module on MB7 baseboard"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &lvds0; - ipu1 = &ipu2; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd0_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&i2c3 { - polytouch1: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti>; - interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; -}; - -&ipu2 { - status = "disabled"; -}; - -&kpp { - status = "disabled"; /* pads partially clash with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds0_timing1>; - - lvds0_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds0_timing1: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - lvds0_timing2: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds1_timing2>; - - lvds1_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds1_timing1: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - lvds1_timing2: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&iomuxc { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; }; diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts index 16d5be1aeb3c..f5d9c34b0d39 100644 --- a/arch/arm/boot/dts/imx6q-utilite-pro.dts +++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts @@ -188,6 +188,8 @@ /delete-node/&hdmi_mux_1; &hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmicec>; ddc-i2c-bus = <&i2c2>; status = "okay"; }; @@ -211,6 +213,12 @@ >; }; + pinctrl_hdmicec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + pinctrl_hpd: hpdgrp { fsl,pins = < MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts new file mode 100644 index 000000000000..e87ddb168669 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts @@ -0,0 +1,26 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-wandboard-revd1.dtsi" + +/ { + model = "Wandboard i.MX6 Quad Board revD1"; + compatible = "wand,imx6q-wandboard", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 90a741732f60..bc581aa5cf17 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -79,15 +79,15 @@ }; soc { - ocram: sram@00900000 { + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x40000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips-bus@02000000 { /* AIPS1 */ - spba-bus@02000000 { - ecspi5: ecspi@02018000 { + aips-bus@2000000 { /* AIPS1 */ + spba-bus@2000000 { + ecspi5: ecspi@2018000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -102,12 +102,12 @@ }; }; - iomuxc: iomuxc@020e0000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6q-iomuxc"; }; }; - sata: sata@02200000 { + sata: sata@2200000 { compatible = "fsl,imx6q-ahci"; reg = <0x02200000 0x4000>; interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; @@ -118,7 +118,7 @@ status = "disabled"; }; - gpu_vg: gpu@02204000 { + gpu_vg: gpu@2204000 { compatible = "vivante,gc"; reg = <0x02204000 0x4000>; interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; @@ -128,7 +128,7 @@ power-domains = <&pd_pu>; }; - ipu2: ipu@02800000 { + ipu2: ipu@2800000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ipu"; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index ea339fa58f4a..e80fdca585f8 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -222,7 +222,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -313,7 +313,7 @@ }; }; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi index 9cd2a7477ed7..829a47938179 100644 --- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi @@ -54,7 +54,7 @@ stdout-path = &uart4; }; - display@di0 { + disp0 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "bgr666"; pinctrl-names = "default"; @@ -209,7 +209,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index ad84eddb6836..fc66bbfd6796 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -167,7 +167,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -248,7 +248,7 @@ }; }; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 885556260bd0..dea8fc43c692 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -332,175 +332,173 @@ }; &iomuxc { - imx6qdl-gw51xx { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 - >; - }; + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 + >; + }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ - >; - }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ + >; + }; - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - >; - }; + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 115d706228ef..363a44394dad 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -303,7 +303,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -311,7 +311,7 @@ VDDIO-supply = <®_3p3v>; }; - touchscreen: egalax_ts@04 { + touchscreen: egalax_ts@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio7>; @@ -423,213 +423,211 @@ }; &iomuxc { - imx6qdl-gw52xx { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + >; + }; - pinctrl_ecspi3: escpi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 - >; - }; + pinctrl_ecspi3: escpi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 + >; + }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ - >; - }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ + >; + }; - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ - >; - }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ + >; + }; - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + >; + }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 24be7965056c..c75385c0cad0 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -294,7 +294,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -302,7 +302,7 @@ VDDIO-supply = <®_3p3v>; }; - touchscreen: egalax_ts@04 { + touchscreen: egalax_ts@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio1>; @@ -415,205 +415,203 @@ }; &iomuxc { - imx6qdl-gw53xx { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + >; + }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - >; - }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ + >; + }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 4594b2279169..eab75f3dbaf3 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -223,7 +223,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -331,7 +331,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -339,7 +339,7 @@ VDDIO-supply = <®_3p3v>; }; - touchscreen: egalax_ts@04 { + touchscreen: egalax_ts@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio7>; @@ -468,221 +468,219 @@ }; &iomuxc { - imx6qdl-gw54xx { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + >; + }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; - pinctrl_ecspi2: escpi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 - >; - }; + pinctrl_ecspi2: escpi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 + >; + }; - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - >; - }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; - pinctrl_pwm4_backlight: pwm4grpbacklight { - fsl,pins = < - /* LVDS_PWM J6.5 */ - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; + pinctrl_pwm4_backlight: pwm4grpbacklight { + fsl,pins = < + /* LVDS_PWM J6.5 */ + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; - pinctrl_pwm4_dio: pwm4grpdio { - fsl,pins = < - /* DIO3 J16.4 */ - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 - >; - }; + pinctrl_pwm4_dio: pwm4grpdio { + fsl,pins = < + /* DIO3 J16.4 */ + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + >; + }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 + >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index 405b40310ddf..30d4662d4480 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -320,110 +320,108 @@ }; &iomuxc { - imx6qdl-gw51xx { - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ - >; - }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ + >; + }; - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index 67613dd7cc92..c67c10605070 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -270,105 +270,103 @@ }; &iomuxc { - imx6qdl-gw552x { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi index 988334c889eb..37c07c0748aa 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi @@ -138,7 +138,7 @@ }; /* Pro baseboard model */ - sgtl5000: sgtl5000@0a { + sgtl5000: sgtl5000@a { clocks = <&clks IMX6QDL_CLK_CKO>; compatible = "fsl,sgtl5000"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi index 7ca291e9dbdb..b6220d62f6de 100644 --- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi @@ -41,6 +41,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/imx6qdl-clock.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> / { memory { @@ -118,17 +119,77 @@ clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>; clock-names = "refclk"; }; -}; -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack", + "Speaker", "Line Out Jack", + "Speaker", "Ext Spk"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; }; &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; status = "okay"; + + audmux_ssi1 { + fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) + >; + }; + + audmux_aud4 { + fsl,audmux-port = <MX51_AUDMUX_PORT4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_3p3v>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + xceiver-supply = <®_3p3v>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; }; &fec { @@ -174,6 +235,16 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + + sgtl5000: codec@a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p8v>; + }; }; &pcie { @@ -184,6 +255,7 @@ }; &ssi1 { + fsl,mode = "i2s-slave"; status = "okay"; }; @@ -270,6 +342,20 @@ >; }; + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi index 56d0c5d21cd0..a1b469c142f1 100644 --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi @@ -42,6 +42,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> / { memory { @@ -55,6 +56,25 @@ default-brightness-level = <7>; }; + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + + reg_2p5v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "3P3V"; @@ -87,6 +107,59 @@ #clock-cells = <0>; clock-frequency = <25000000>; /* 25MHz for example */ }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx6qdl-icore-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack", + "Speaker", "Line Out Jack", + "Speaker", "Ext Spk"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + + audmux_ssi1 { + fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) + >; + }; + + audmux_aud4 { + fsl,audmux-port = <MX51_AUDMUX_PORT4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) + >; + }; }; &can1 { @@ -141,6 +214,16 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + + sgtl5000: codec@a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p8v>; + }; }; &pwm3 { @@ -149,6 +232,11 @@ status = "okay"; }; +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; @@ -178,6 +266,15 @@ }; &iomuxc { + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + pinctrl_enet: enetgrp { fsl,pins = < MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index 6b81580623ff..4cc4e23cf99c 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -255,7 +255,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; @@ -279,7 +279,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - touchscreen@04 { + touchscreen@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio1>; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index b63134e3b51a..3a77f0fedfce 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -256,7 +256,7 @@ status = "okay"; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; @@ -397,7 +397,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; @@ -429,7 +429,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - touchscreen@04 { + touchscreen@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio1>; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index a24e4f1911ab..40942d6b94b3 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -120,7 +120,7 @@ }; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; @@ -315,7 +315,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; @@ -347,7 +347,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - touchscreen@04 { + touchscreen@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio1>; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index d309a4d0eb08..4bdf29169d2a 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -197,7 +197,7 @@ status = "okay"; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; @@ -313,7 +313,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -340,7 +340,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - touchscreen@04 { + touchscreen@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio1>; diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi index 5cf90c24c707..6e9549ff11da 100644 --- a/arch/arm/boot/dts/imx6qdl-rex.dtsi +++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi @@ -121,7 +121,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 6a7594e5d183..4fa2fac3877b 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -244,7 +244,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 756c5054f047..35de7adc997b 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -221,7 +221,7 @@ status = "okay"; }; - lcd_display: display@di0 { + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; #address-cells = <1>; #size-cells = <0>; @@ -350,7 +350,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index b72b6fa47580..0a50705b9c18 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -67,7 +67,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 19 0>; - regulator-always-on; enable-active-high; }; }; @@ -214,6 +213,8 @@ }; &hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; ddc-i2c-bus = <&i2c2>; status = "okay"; }; @@ -304,7 +305,7 @@ }; }; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -411,7 +412,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - egalax_ts@04 { + egalax_ts@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio6>; @@ -486,6 +487,12 @@ >; }; + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 @@ -651,6 +658,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi new file mode 100644 index 000000000000..5102fc47380b --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi @@ -0,0 +1,252 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + aliases { + display = &display; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd1_pwr>; + enable-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + turn-on-delay-ms = <35>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + lcd_panel: lcd-panel { + compatible = "edt,etm0700g0dh6"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_pwr>; + enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + backlight = <&backlight>; + bus-format-override = "rgb24"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_out>; + }; + }; + }; + + display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_1>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + + display-timings { + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + u-boot,panel-name = "edt,et057090dhu"; + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0350 { + u-boot,panel-name = "edt,et0350g0dh6"; + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0430 { + u-boot,panel-name = "edt,et0430g0dh6"; + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0700 { /* same as ET0500 */ + u-boot,panel-name = "edt,etm0700g0dh6"; + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + CoMTFT { /* same as ET0700 but with inverted pixel clock */ + u-boot,panel-name = "edt,etm0700g0edh6"; + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_in>; +}; diff --git a/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi new file mode 100644 index 000000000000..2ca2eb37e14f --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi @@ -0,0 +1,286 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + aliases { + display = &lvds0; + lvds0 = &lvds0; + lvds1 = &lvds1; + }; + + backlight0: backlight0 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 0>; + power-supply = <®_lcd0_pwr>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 0>; + power-supply = <®_lcd1_pwr>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + lvds0_panel: lvds0-panel { + compatible = "nlt,nl12880bc20-spwg-24"; + backlight = <&backlight0>; + power-supply = <®_3v3>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + lvds1_panel: lvds1-panel { + compatible = "nlt,nl12880bc20-spwg-24"; + backlight = <&backlight1>; + power-supply = <®_3v3>; + + port { + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&kpp { + status = "disabled"; /* pad conflict with backlight1 PWM */ +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + + display-timings { + hsd100pxn1 { + u-boot,panel-name = "hannstar,hsd100pxn1"; + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + de-active = <1>; + pixelclk-active = <1>; + }; + + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hfront-porch = <16>; + vback-porch = <31>; + vfront-porch = <12>; + hsync-len = <96>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + nl12880bc20 { + u-boot,panel-name = "nlt,nl12880bc20-spwg-24"; + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <50>; + hfront-porch = <50>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <60>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0700 { + u-boot,panel-name = "edt,etm0700g0dh6"; + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + u-boot,panel-name = "edt,et057090dhu"; + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; + + lvds1: lvds-channel@1 { + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + + display-timings { + hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + de-active = <1>; + pixelclk-active = <1>; + }; + + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hfront-porch = <16>; + vback-porch = <31>; + vfront-porch = <12>; + hsync-len = <96>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + nl12880bc20 { + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <50>; + hfront-porch = <50>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <60>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +®_lcd0_pwr { + status = "okay"; +}; + +®_lcd1_pwr { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi new file mode 100644 index 000000000000..4c4e2e1a931f --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi @@ -0,0 +1,99 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + backlight0 { + pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; + turn-on-delay-ms = <35>; + power-supply = <®_lcd1_pwr>; + }; + + backlight1 { + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + turn-on-delay-ms = <35>; + power-supply = <®_lcd1_pwr>; + }; + + lcd-panel { + compatible = "edt,et057090dhu"; + bus-format-override = "rgb24"; + pixelclk-active = <0>; + }; + + lvds0-panel { + compatible = "edt,etml1010g0dka"; + bus-format-override = "spwg-18"; + pixelclk-active = <0>; + }; + + lvds1-panel { + compatible = "edt,etml1010g0dka"; + bus-format-override = "spwg-18"; + pixelclk-active = <0>; + }; +}; + +&can1 { + status = "disabled"; +}; + +&can2 { + xceiver-supply = <®_3v3>; +}; + +&ds1339 { + /* + * The backup voltage of the module internal RTC is not wired + * by default on the MB7, so disable that RTC chip. + */ + status = "disabled"; +}; + +&i2c3 { + rtc: mcp7940x@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; +}; + +®_lcd0_pwr { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index c6bec97fbeaf..6abb66cd7d4a 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,6 +43,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> / { aliases { @@ -145,7 +146,7 @@ pinctrl-0 = <&pinctrl_lcd0_pwr>; gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-boot-on; + status = "disabled"; }; reg_lcd1_pwr: regulator-lcd1-pwr { @@ -157,7 +158,7 @@ pinctrl-0 = <&pinctrl_lcd1_pwr>; gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-boot-on; + status = "disabled"; }; reg_usbh1_vbus: regulator-usbh1-vbus { @@ -183,24 +184,56 @@ }; sound { - compatible = "karo,imx6qdl-tx6qdl-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; + compatible = "karo,imx6qdl-tx6-sgtl5000", + "simple-audio-card"; + simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <5>; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; }; }; &audmux { status = "okay"; + + ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSEL(4) | + IMX_AUDMUX_V2_PTCR_TCSEL(4) | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + pins5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(0) + >; + }; }; &can1 { @@ -241,7 +274,7 @@ &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>; clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET_REF>, @@ -249,6 +282,7 @@ clock-names = "ipg", "ahb", "ptp", "enet_out"; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <10>; phy-handle = <&etnphy>; phy-supply = <®_3v3_etn>; status = "okay"; @@ -261,8 +295,9 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_mdio>; - interrupts-extended = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_etnphy_int>; + interrupt-parent = <&gpio7>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; }; }; }; @@ -276,25 +311,34 @@ }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; clock-frequency = <400000>; status = "okay"; ds1339: rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; + trickle-resistor-ohms = <250>; + trickle-diode-disable; }; }; &i2c3 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; clock-frequency = <400000>; status = "okay"; - sgtl5000: sgtl5000@0a { + sgtl5000: sgtl5000@a { compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; reg = <0x0a>; VDDA-supply = <®_2v5>; VDDIO-supply = <®_3v3>; @@ -332,8 +376,6 @@ pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ >; }; @@ -451,12 +493,24 @@ >; }; + pinctrl_etnphy_int: etnphy-intgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ + >; + }; + pinctrl_etnphy_power: etnphy-pwrgrp { fsl,pins = < MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ >; }; + pinctrl_etnphy_rst: etnphy-rstgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ + >; + }; + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 @@ -504,6 +558,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 @@ -511,6 +572,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 + >; + }; + pinctrl_kpp: kppgrp { fsl,pins = < MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi new file mode 100644 index 000000000000..6d8d9ca96646 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi @@ -0,0 +1,196 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include "imx6qdl-wandboard.dtsi" + +/ { + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed"; + regulator-name = "ETH_PHY"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 13 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&fec { + phy-supply = <®_eth_phy>; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-wandboard { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x80000000 /* USB Power Enable */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 + >; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index b4fa7f1d63da..ed96d7b5feab 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -82,7 +82,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index eeb7679fd348..7812fbac963c 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -390,7 +390,7 @@ clock-frequency = <100000>; status = "okay"; - pmic@08 { + pmic@8 { compatible = "fsl,pfuze100"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pfuze100_irq>; @@ -543,7 +543,7 @@ rmi4-f01@1 { reg = <0x1>; - syna,nosleep-mode = <1>; + syna,nosleep-mode = <2>; }; rmi4-f11@11 { @@ -728,6 +728,7 @@ &usbh1 { vbus-supply = <®_5p0v_main>; + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 8884b4a3cafb..1ce4eabf0590 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -87,7 +87,7 @@ interrupt-parent = <&gpc>; ranges; - dma_apbh: dma-apbh@00110000 { + dma_apbh: dma-apbh@110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, @@ -100,7 +100,7 @@ clocks = <&clks IMX6QDL_CLK_APBH_DMA>; }; - gpmi: gpmi-nand@00112000 { + gpmi: gpmi-nand@112000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; @@ -120,7 +120,7 @@ status = "disabled"; }; - hdmi: hdmi@0120000 { + hdmi: hdmi@120000 { #address-cells = <1>; #size-cells = <0>; reg = <0x00120000 0x9000>; @@ -148,7 +148,7 @@ }; }; - gpu_3d: gpu@00130000 { + gpu_3d: gpu@130000 { compatible = "vivante,gc"; reg = <0x00130000 0x4000>; interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; @@ -159,7 +159,7 @@ power-domains = <&pd_pu>; }; - gpu_2d: gpu@00134000 { + gpu_2d: gpu@134000 { compatible = "vivante,gc"; reg = <0x00134000 0x4000>; interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; @@ -169,7 +169,7 @@ power-domains = <&pd_pu>; }; - timer@00a00600 { + timer@a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; interrupts = <1 13 0xf01>; @@ -177,7 +177,7 @@ clocks = <&clks IMX6QDL_CLK_TWD>; }; - intc: interrupt-controller@00a01000 { + intc: interrupt-controller@a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -186,7 +186,7 @@ interrupt-parent = <&intc>; }; - L2: l2-cache@00a02000 { + L2: l2-cache@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; @@ -229,21 +229,21 @@ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; }; - aips-bus@02000000 { /* AIPS1 */ + aips-bus@2000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; - spba-bus@02000000 { + spba-bus@2000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x40000>; ranges; - spdif: spdif@02004000 { + spdif: spdif@2004000 { compatible = "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; @@ -263,7 +263,7 @@ status = "disabled"; }; - ecspi1: ecspi@02008000 { + ecspi1: ecspi@2008000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -277,7 +277,7 @@ status = "disabled"; }; - ecspi2: ecspi@0200c000 { + ecspi2: ecspi@200c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -291,7 +291,7 @@ status = "disabled"; }; - ecspi3: ecspi@02010000 { + ecspi3: ecspi@2010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -305,7 +305,7 @@ status = "disabled"; }; - ecspi4: ecspi@02014000 { + ecspi4: ecspi@2014000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -319,7 +319,7 @@ status = "disabled"; }; - uart1: serial@02020000 { + uart1: serial@2020000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; @@ -331,7 +331,7 @@ status = "disabled"; }; - esai: esai@02024000 { + esai: esai@2024000 { #sound-dai-cells = <0>; compatible = "fsl,imx35-esai"; reg = <0x02024000 0x4000>; @@ -347,7 +347,7 @@ status = "disabled"; }; - ssi1: ssi@02028000 { + ssi1: ssi@2028000 { #sound-dai-cells = <0>; compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi"; @@ -363,7 +363,7 @@ status = "disabled"; }; - ssi2: ssi@0202c000 { + ssi2: ssi@202c000 { #sound-dai-cells = <0>; compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi"; @@ -379,7 +379,7 @@ status = "disabled"; }; - ssi3: ssi@02030000 { + ssi3: ssi@2030000 { #sound-dai-cells = <0>; compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi"; @@ -395,7 +395,7 @@ status = "disabled"; }; - asrc: asrc@02034000 { + asrc: asrc@2034000 { compatible = "fsl,imx53-asrc"; reg = <0x02034000 0x4000>; interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; @@ -420,12 +420,12 @@ status = "okay"; }; - spba@0203c000 { + spba@203c000 { reg = <0x0203c000 0x4000>; }; }; - vpu: vpu@02040000 { + vpu: vpu@2040000 { compatible = "cnm,coda960"; reg = <0x02040000 0x3c000>; interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, @@ -439,11 +439,11 @@ iram = <&ocram>; }; - aipstz@0207c000 { /* AIPSTZ1 */ + aipstz@207c000 { /* AIPSTZ1 */ reg = <0x0207c000 0x4000>; }; - pwm1: pwm@02080000 { + pwm1: pwm@2080000 { #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; @@ -454,7 +454,7 @@ status = "disabled"; }; - pwm2: pwm@02084000 { + pwm2: pwm@2084000 { #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; @@ -465,7 +465,7 @@ status = "disabled"; }; - pwm3: pwm@02088000 { + pwm3: pwm@2088000 { #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; @@ -476,7 +476,7 @@ status = "disabled"; }; - pwm4: pwm@0208c000 { + pwm4: pwm@208c000 { #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; @@ -487,7 +487,7 @@ status = "disabled"; }; - can1: flexcan@02090000 { + can1: flexcan@2090000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; @@ -497,7 +497,7 @@ status = "disabled"; }; - can2: flexcan@02094000 { + can2: flexcan@2094000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; @@ -507,7 +507,7 @@ status = "disabled"; }; - gpt: gpt@02098000 { + gpt: gpt@2098000 { compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; reg = <0x02098000 0x4000>; interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; @@ -517,7 +517,7 @@ clock-names = "ipg", "per", "osc_per"; }; - gpio1: gpio@0209c000 { + gpio1: gpio@209c000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, @@ -528,7 +528,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio@020a0000 { + gpio2: gpio@20a0000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, @@ -539,7 +539,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio@020a4000 { + gpio3: gpio@20a4000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, @@ -550,7 +550,7 @@ #interrupt-cells = <2>; }; - gpio4: gpio@020a8000 { + gpio4: gpio@20a8000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, @@ -561,7 +561,7 @@ #interrupt-cells = <2>; }; - gpio5: gpio@020ac000 { + gpio5: gpio@20ac000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, @@ -572,7 +572,7 @@ #interrupt-cells = <2>; }; - gpio6: gpio@020b0000 { + gpio6: gpio@20b0000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020b0000 0x4000>; interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, @@ -583,7 +583,7 @@ #interrupt-cells = <2>; }; - gpio7: gpio@020b4000 { + gpio7: gpio@20b4000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020b4000 0x4000>; interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, @@ -594,7 +594,7 @@ #interrupt-cells = <2>; }; - kpp: kpp@020b8000 { + kpp: kpp@20b8000 { compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; @@ -602,14 +602,14 @@ status = "disabled"; }; - wdog1: wdog@020bc000 { + wdog1: wdog@20bc000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_DUMMY>; }; - wdog2: wdog@020c0000 { + wdog2: wdog@20c0000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; @@ -617,7 +617,7 @@ status = "disabled"; }; - clks: ccm@020c4000 { + clks: ccm@20c4000 { compatible = "fsl,imx6q-ccm"; reg = <0x020c4000 0x4000>; interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, @@ -625,7 +625,7 @@ #clock-cells = <1>; }; - anatop: anatop@020c8000 { + anatop: anatop@20c8000 { compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, @@ -737,7 +737,7 @@ clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; }; - usbphy1: usbphy@020c9000 { + usbphy1: usbphy@20c9000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; @@ -745,7 +745,7 @@ fsl,anatop = <&anatop>; }; - usbphy2: usbphy@020ca000 { + usbphy2: usbphy@20ca000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; @@ -753,7 +753,7 @@ fsl,anatop = <&anatop>; }; - snvs: snvs@020cc000 { + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -775,17 +775,17 @@ }; }; - epit1: epit@020d0000 { /* EPIT1 */ + epit1: epit@20d0000 { /* EPIT1 */ reg = <0x020d0000 0x4000>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; }; - epit2: epit@020d4000 { /* EPIT2 */ + epit2: epit@20d4000 { /* EPIT2 */ reg = <0x020d4000 0x4000>; interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@020d8000 { + src: src@20d8000 { compatible = "fsl,imx6q-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, @@ -793,7 +793,7 @@ #reset-cells = <1>; }; - gpc: gpc@020dc000 { + gpc: gpc@20dc000 { compatible = "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; interrupt-controller; @@ -826,9 +826,9 @@ }; }; - gpr: iomuxc-gpr@020e0000 { + gpr: iomuxc-gpr@20e0000 { compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; - reg = <0x020e0000 0x38>; + reg = <0x20e0000 0x38>; mux: mux-controller { compatible = "mmio-mux"; @@ -836,9 +836,9 @@ }; }; - iomuxc: iomuxc@020e0000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; - reg = <0x020e0000 0x4000>; + reg = <0x20e0000 0x4000>; }; ldb: ldb { @@ -895,17 +895,17 @@ }; }; - dcic1: dcic@020e4000 { + dcic1: dcic@20e4000 { reg = <0x020e4000 0x4000>; interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; }; - dcic2: dcic@020e8000 { + dcic2: dcic@20e8000 { reg = <0x020e8000 0x4000>; interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; }; - sdma: sdma@020ec000 { + sdma: sdma@20ec000 { compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; @@ -917,7 +917,7 @@ }; }; - aips-bus@02100000 { /* AIPS2 */ + aips-bus@2100000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -950,11 +950,11 @@ }; }; - aipstz@0217c000 { /* AIPSTZ2 */ + aipstz@217c000 { /* AIPSTZ2 */ reg = <0x0217c000 0x4000>; }; - usbotg: usb@02184000 { + usbotg: usb@2184000 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; @@ -967,7 +967,7 @@ status = "disabled"; }; - usbh1: usb@02184200 { + usbh1: usb@2184200 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; @@ -981,7 +981,7 @@ status = "disabled"; }; - usbh2: usb@02184400 { + usbh2: usb@2184400 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; @@ -994,7 +994,7 @@ status = "disabled"; }; - usbh3: usb@02184600 { + usbh3: usb@2184600 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184600 0x200>; interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; @@ -1007,14 +1007,14 @@ status = "disabled"; }; - usbmisc: usbmisc@02184800 { + usbmisc: usbmisc@2184800 { #index-cells = <1>; compatible = "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; clocks = <&clks IMX6QDL_CLK_USBOH3>; }; - fec: ethernet@02188000 { + fec: ethernet@2188000 { compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupts-extended = @@ -1027,14 +1027,14 @@ status = "disabled"; }; - mlb@0218c000 { + mlb@218c000 { reg = <0x0218c000 0x4000>; interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, <0 117 IRQ_TYPE_LEVEL_HIGH>, <0 126 IRQ_TYPE_LEVEL_HIGH>; }; - usdhc1: usdhc@02190000 { + usdhc1: usdhc@2190000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; @@ -1046,7 +1046,7 @@ status = "disabled"; }; - usdhc2: usdhc@02194000 { + usdhc2: usdhc@2194000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; @@ -1058,7 +1058,7 @@ status = "disabled"; }; - usdhc3: usdhc@02198000 { + usdhc3: usdhc@2198000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; @@ -1070,7 +1070,7 @@ status = "disabled"; }; - usdhc4: usdhc@0219c000 { + usdhc4: usdhc@219c000 { compatible = "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; @@ -1082,7 +1082,7 @@ status = "disabled"; }; - i2c1: i2c@021a0000 { + i2c1: i2c@21a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; @@ -1092,7 +1092,7 @@ status = "disabled"; }; - i2c2: i2c@021a4000 { + i2c2: i2c@21a4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; @@ -1102,7 +1102,7 @@ status = "disabled"; }; - i2c3: i2c@021a8000 { + i2c3: i2c@21a8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; @@ -1112,20 +1112,20 @@ status = "disabled"; }; - romcp@021ac000 { + romcp@21ac000 { reg = <0x021ac000 0x4000>; }; - mmdc0: mmdc@021b0000 { /* MMDC0 */ + mmdc0: mmdc@21b0000 { /* MMDC0 */ compatible = "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; }; - mmdc1: mmdc@021b4000 { /* MMDC1 */ + mmdc1: mmdc@21b4000 { /* MMDC1 */ reg = <0x021b4000 0x4000>; }; - weim: weim@021b8000 { + weim: weim@21b8000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx6q-weim"; @@ -1136,29 +1136,29 @@ status = "disabled"; }; - ocotp: ocotp@021bc000 { + ocotp: ocotp@21bc000 { compatible = "fsl,imx6q-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6QDL_CLK_IIM>; }; - tzasc@021d0000 { /* TZASC1 */ + tzasc@21d0000 { /* TZASC1 */ reg = <0x021d0000 0x4000>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; }; - tzasc@021d4000 { /* TZASC2 */ + tzasc@21d4000 { /* TZASC2 */ reg = <0x021d4000 0x4000>; interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; }; - audmux: audmux@021d8000 { + audmux: audmux@21d8000 { compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; reg = <0x021d8000 0x4000>; status = "disabled"; }; - mipi_csi: mipi@021dc000 { + mipi_csi: mipi@21dc000 { compatible = "fsl,imx6-mipi-csi2"; reg = <0x021dc000 0x4000>; #address-cells = <1>; @@ -1171,7 +1171,7 @@ status = "disabled"; }; - mipi_dsi: mipi@021e0000 { + mipi_dsi: mipi@21e0000 { #address-cells = <1>; #size-cells = <0>; reg = <0x021e0000 0x4000>; @@ -1199,14 +1199,14 @@ }; }; - vdoa@021e4000 { + vdoa@21e4000 { compatible = "fsl,imx6q-vdoa"; reg = <0x021e4000 0x4000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_VDOA>; }; - uart2: serial@021e8000 { + uart2: serial@21e8000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; @@ -1218,7 +1218,7 @@ status = "disabled"; }; - uart3: serial@021ec000 { + uart3: serial@21ec000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; @@ -1230,7 +1230,7 @@ status = "disabled"; }; - uart4: serial@021f0000 { + uart4: serial@21f0000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; @@ -1242,7 +1242,7 @@ status = "disabled"; }; - uart5: serial@021f4000 { + uart5: serial@21f4000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; @@ -1255,7 +1255,7 @@ }; }; - ipu1: ipu@02400000 { + ipu1: ipu@2400000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ipu"; diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts new file mode 100644 index 000000000000..92b38e6699aa --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6qp-tx6qp-8037.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-8037 Module on MB7 baseboard"; +}; diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts new file mode 100644 index 000000000000..ffc0f2ee11d2 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts @@ -0,0 +1,86 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6qp.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lcd.dtsi" + +/ { + model = "Ka-Ro electronics TX6QP-8037 Module"; + compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&ipu2 { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts new file mode 100644 index 000000000000..07ad70718aec --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts @@ -0,0 +1,57 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6qp-tx6qp-8137.dts" +#include "imx6qdl-tx6-mb7.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-8137 Module on MB7 baseboard"; + compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; +}; + +&ipu2 { + status = "disabled"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts new file mode 100644 index 000000000000..dd494d587014 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts @@ -0,0 +1,90 @@ +/* + * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6qp.dtsi" +#include "imx6qdl-tx6.dtsi" +#include "imx6qdl-tx6-lvds.dtsi" + +/ { + model = "Ka-Ro electronics TX6QP-8137 Module"; + compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&ipu2 { + status = "disabled"; +}; + +&sata { + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts new file mode 100644 index 000000000000..f7badd82ce8a --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts @@ -0,0 +1,26 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +/dts-v1/; +#include "imx6qp.dtsi" +#include "imx6qdl-wandboard-revd1.dtsi" + +/ { + model = "Wandboard i.MX6 QuadPlus Board revD1"; + compatible = "wand,imx6qp-wandboard", "fsl,imx6qp"; + + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index 299d863690c5..5f4fdce715c1 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -44,19 +44,19 @@ / { soc { - ocram2: sram@00940000 { + ocram2: sram@940000 { compatible = "mmio-sram"; reg = <0x00940000 0x20000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - ocram3: sram@00960000 { + ocram3: sram@960000 { compatible = "mmio-sram"; reg = <0x00960000 0x20000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips-bus@02100000 { + aips-bus@2100000 { pre1: pre@21c8000 { compatible = "fsl,imx6qp-pre"; reg = <0x021c8000 0x1000>; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 0a90eea17018..60600b4cf5fe 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -145,7 +145,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 3f76f980947e..3ea1a41893c8 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -76,7 +76,7 @@ }; }; - intc: interrupt-controller@00a01000 { + intc: interrupt-controller@a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -109,13 +109,13 @@ interrupt-parent = <&gpc>; ranges; - ocram: sram@00900000 { + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; clocks = <&clks IMX6SL_CLK_OCRAM>; }; - L2: l2-cache@00a02000 { + L2: l2-cache@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; @@ -130,21 +130,21 @@ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; }; - aips1: aips-bus@02000000 { + aips1: aips-bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; - spba: spba-bus@02000000 { + spba: spba-bus@2000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x40000>; ranges; - spdif: spdif@02004000 { + spdif: spdif@2004000 { compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; @@ -165,7 +165,7 @@ status = "disabled"; }; - ecspi1: ecspi@02008000 { + ecspi1: ecspi@2008000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; @@ -177,7 +177,7 @@ status = "disabled"; }; - ecspi2: ecspi@0200c000 { + ecspi2: ecspi@200c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; @@ -189,7 +189,7 @@ status = "disabled"; }; - ecspi3: ecspi@02010000 { + ecspi3: ecspi@2010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; @@ -201,7 +201,7 @@ status = "disabled"; }; - ecspi4: ecspi@02014000 { + ecspi4: ecspi@2014000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; @@ -213,7 +213,7 @@ status = "disabled"; }; - uart5: serial@02018000 { + uart5: serial@2018000 { compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02018000 0x4000>; @@ -226,7 +226,7 @@ status = "disabled"; }; - uart1: serial@02020000 { + uart1: serial@2020000 { compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; @@ -239,7 +239,7 @@ status = "disabled"; }; - uart2: serial@02024000 { + uart2: serial@2024000 { compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02024000 0x4000>; @@ -252,7 +252,7 @@ status = "disabled"; }; - ssi1: ssi@02028000 { + ssi1: ssi@2028000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; @@ -268,7 +268,7 @@ status = "disabled"; }; - ssi2: ssi@0202c000 { + ssi2: ssi@202c000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; @@ -284,7 +284,7 @@ status = "disabled"; }; - ssi3: ssi@02030000 { + ssi3: ssi@2030000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; @@ -300,7 +300,7 @@ status = "disabled"; }; - uart3: serial@02034000 { + uart3: serial@2034000 { compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02034000 0x4000>; @@ -313,7 +313,7 @@ status = "disabled"; }; - uart4: serial@02038000 { + uart4: serial@2038000 { compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02038000 0x4000>; @@ -327,7 +327,7 @@ }; }; - pwm1: pwm@02080000 { + pwm1: pwm@2080000 { #pwm-cells = <2>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; @@ -337,7 +337,7 @@ clock-names = "ipg", "per"; }; - pwm2: pwm@02084000 { + pwm2: pwm@2084000 { #pwm-cells = <2>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; @@ -347,7 +347,7 @@ clock-names = "ipg", "per"; }; - pwm3: pwm@02088000 { + pwm3: pwm@2088000 { #pwm-cells = <2>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; @@ -357,7 +357,7 @@ clock-names = "ipg", "per"; }; - pwm4: pwm@0208c000 { + pwm4: pwm@208c000 { #pwm-cells = <2>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; @@ -367,7 +367,7 @@ clock-names = "ipg", "per"; }; - gpt: gpt@02098000 { + gpt: gpt@2098000 { compatible = "fsl,imx6sl-gpt"; reg = <0x02098000 0x4000>; interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; @@ -376,7 +376,7 @@ clock-names = "ipg", "per"; }; - gpio1: gpio@0209c000 { + gpio1: gpio@209c000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, @@ -393,7 +393,7 @@ <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; }; - gpio2: gpio@020a0000 { + gpio2: gpio@20a0000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, @@ -411,7 +411,7 @@ <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; }; - gpio3: gpio@020a4000 { + gpio3: gpio@20a4000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, @@ -430,7 +430,7 @@ <&iomuxc 31 102 1>; }; - gpio4: gpio@020a8000 { + gpio4: gpio@20a8000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, @@ -456,7 +456,7 @@ <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; }; - gpio5: gpio@020ac000 { + gpio5: gpio@20ac000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, @@ -478,7 +478,7 @@ <&iomuxc 21 161 1>; }; - kpp: kpp@020b8000 { + kpp: kpp@20b8000 { compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; @@ -486,14 +486,14 @@ status = "disabled"; }; - wdog1: wdog@020bc000 { + wdog1: wdog@20bc000 { compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_DUMMY>; }; - wdog2: wdog@020c0000 { + wdog2: wdog@20c0000 { compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; @@ -501,7 +501,7 @@ status = "disabled"; }; - clks: ccm@020c4000 { + clks: ccm@20c4000 { compatible = "fsl,imx6sl-ccm"; reg = <0x020c4000 0x4000>; interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, @@ -509,7 +509,7 @@ #clock-cells = <1>; }; - anatop: anatop@020c8000 { + anatop: anatop@20c8000 { compatible = "fsl,imx6sl-anatop", "fsl,imx6q-anatop", "syscon", "simple-bus"; @@ -623,7 +623,7 @@ clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; }; - usbphy1: usbphy@020c9000 { + usbphy1: usbphy@20c9000 { compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; @@ -631,7 +631,7 @@ fsl,anatop = <&anatop>; }; - usbphy2: usbphy@020ca000 { + usbphy2: usbphy@20ca000 { compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; @@ -639,7 +639,7 @@ fsl,anatop = <&anatop>; }; - snvs: snvs@020cc000 { + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -661,17 +661,17 @@ }; }; - epit1: epit@020d0000 { + epit1: epit@20d0000 { reg = <0x020d0000 0x4000>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; }; - epit2: epit@020d4000 { + epit2: epit@20d4000 { reg = <0x020d4000 0x4000>; interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@020d8000 { + src: src@20d8000 { compatible = "fsl,imx6sl-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, @@ -679,7 +679,7 @@ #reset-cells = <1>; }; - gpc: gpc@020dc000 { + gpc: gpc@20dc000 { compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; interrupt-controller; @@ -692,28 +692,28 @@ #power-domain-cells = <1>; }; - gpr: iomuxc-gpr@020e0000 { + gpr: iomuxc-gpr@20e0000 { compatible = "fsl,imx6sl-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e0000 0x38>; }; - iomuxc: iomuxc@020e0000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6sl-iomuxc"; reg = <0x020e0000 0x4000>; }; - csi: csi@020e4000 { + csi: csi@20e4000 { reg = <0x020e4000 0x4000>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; }; - spdc: spdc@020e8000 { + spdc: spdc@20e8000 { reg = <0x020e8000 0x4000>; interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; }; - sdma: sdma@020ec000 { + sdma: sdma@20ec000 { compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; @@ -725,17 +725,17 @@ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; - pxp: pxp@020f0000 { + pxp: pxp@20f0000 { reg = <0x020f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; }; - epdc: epdc@020f4000 { + epdc: epdc@20f4000 { reg = <0x020f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; }; - lcdif: lcdif@020f8000 { + lcdif: lcdif@20f8000 { compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; reg = <0x020f8000 0x4000>; interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; @@ -746,7 +746,7 @@ status = "disabled"; }; - dcp: dcp@020fc000 { + dcp: dcp@20fc000 { compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; reg = <0x020fc000 0x4000>; interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, @@ -755,14 +755,14 @@ }; }; - aips2: aips-bus@02100000 { + aips2: aips-bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; - usbotg1: usb@02184000 { + usbotg1: usb@2184000 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; @@ -775,7 +775,7 @@ status = "disabled"; }; - usbotg2: usb@02184200 { + usbotg2: usb@2184200 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; @@ -788,7 +788,7 @@ status = "disabled"; }; - usbh: usb@02184400 { + usbh: usb@2184400 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; @@ -801,14 +801,14 @@ status = "disabled"; }; - usbmisc: usbmisc@02184800 { + usbmisc: usbmisc@2184800 { #index-cells = <1>; compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; clocks = <&clks IMX6SL_CLK_USBOH3>; }; - fec: ethernet@02188000 { + fec: ethernet@2188000 { compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; reg = <0x02188000 0x4000>; interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; @@ -818,7 +818,7 @@ status = "disabled"; }; - usdhc1: usdhc@02190000 { + usdhc1: usdhc@2190000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; @@ -830,7 +830,7 @@ status = "disabled"; }; - usdhc2: usdhc@02194000 { + usdhc2: usdhc@2194000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; @@ -842,7 +842,7 @@ status = "disabled"; }; - usdhc3: usdhc@02198000 { + usdhc3: usdhc@2198000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; @@ -854,7 +854,7 @@ status = "disabled"; }; - usdhc4: usdhc@0219c000 { + usdhc4: usdhc@219c000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; @@ -866,7 +866,7 @@ status = "disabled"; }; - i2c1: i2c@021a0000 { + i2c1: i2c@21a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; @@ -876,7 +876,7 @@ status = "disabled"; }; - i2c2: i2c@021a4000 { + i2c2: i2c@21a4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; @@ -886,7 +886,7 @@ status = "disabled"; }; - i2c3: i2c@021a8000 { + i2c3: i2c@21a8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; @@ -896,17 +896,17 @@ status = "disabled"; }; - mmdc: mmdc@021b0000 { + mmdc: mmdc@21b0000 { compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; }; - rngb: rngb@021b4000 { + rngb: rngb@21b4000 { reg = <0x021b4000 0x4000>; interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; }; - weim: weim@021b8000 { + weim: weim@21b8000 { #address-cells = <2>; #size-cells = <1>; reg = <0x021b8000 0x4000>; @@ -915,13 +915,13 @@ status = "disabled"; }; - ocotp: ocotp@021bc000 { + ocotp: ocotp@21bc000 { compatible = "fsl,imx6sl-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SL_CLK_OCOTP>; }; - audmux: audmux@021d8000 { + audmux: audmux@21d8000 { compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; reg = <0x021d8000 0x4000>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index c5578d1c1ee4..f9d40ee14982 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -231,7 +231,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index 71005478cdf0..e3533e74ccc8 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -18,7 +18,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index c0139d7e497a..6dd9bebfe027 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -18,7 +18,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze200"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts new file mode 100644 index 000000000000..4d8c6521845f --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts @@ -0,0 +1,572 @@ +/* + * Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "imx6sx.dtsi" + +/ { + model = "Softing VIN|ING 2000"; + compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + reg_usb_otg1_vbus: regulator-usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_peri_3v3: regulator-peri_3v3 { + compatible = "regulator-fixed"; + regulator-name = "peri_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pwmleds { + compatible = "pwm-leds"; + + red { + label = "red"; + max-brightness = <255>; + pwms = <&pwm6 0 50000>; + }; + + green { + label = "green"; + max-brightness = <255>; + pwms = <&pwm2 0 50000>; + }; + + blue { + label = "blue"; + max-brightness = <255>; + pwms = <&pwm1 0 50000>; + }; + }; +}; + +&adc1 { + vref-supply = <®_peri_3v3>; + status = "okay"; +}; + +&cpu0 { + /* + * This board has a shared rail of reg_arm and reg_soc (supplied by + * sw1a_reg) which is modeled below, but still this module behaves + * unstable without higher voltages. Hence, set higher voltages here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-supply = <®_peri_3v3>; + phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + phy-reset-duration = <5>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet0-phy@0 { + reg = <0>; + max-speed = <100>; + interrupt-parent = <&gpio2>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-supply = <®_peri_3v3>; + phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + phy-reset-duration = <5>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet1-phy@0 { + reg = <0>; + max-speed = <100>; + interrupt-parent = <&gpio2>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + proximity: sx9500@28 { + compatible = "semtech,sx9500"; + reg = <0x28>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sx9500>; + interrupt-parent = <&gpio2>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + }; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1 + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1 + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9 + MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038 + /* LAN8720 PHY Reset */ + MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0 + /* MDIO */ + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9 + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9 + /* IRQ from PHY */ + MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0 + MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038 + /* LAN8720 PHY Reset */ + MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0 + /* MDIO */ + MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9 + MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9 + /* IRQ from PHY */ + MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 + >; + }; + + pinctrl_gpios: gpiosgrp { + fsl,pins = < + /* reset external uC */ + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0 + /* IRQ from external uC */ + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0 + /* overcurrent detection */ + MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_pwm1: pwm1grp-1 { + fsl,pins = < + /* blue LED */ + MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp-1 { + fsl,pins = < + /* green LED */ + MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm6: pwm6grp-1 { + fsl,pins = < + /* red LED */ + MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1 + >; + }; + + pinctrl_sx9500: sx9500grp { + fsl,pins = < + /* Reset */ + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838 + /* IRQ */ + MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc2_50mhz: usdhc2grp-50mhz { + fsl,pins = < + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4grp-50mhz { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068 + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_soc { + vin-supply = <&sw1a_reg>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_50mhz>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc4 { + /* hs200-mode is currently unsupported because Vccq is on 3.1V, but + * not on necessary 1.8V. + */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + pinctrl-1 = <&pinctrl_usdhc4_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_200mhz>; + bus-width = <8>; + keep-power-in-suspend; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi index dcfc97591433..53b3eac94f0d 100644 --- a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi +++ b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi @@ -135,7 +135,7 @@ clock-frequency = <100000>; status = "okay"; - pmic: pmic@08 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 6c7eb54be9e2..5b03ba3beda9 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -95,7 +95,7 @@ }; }; - intc: interrupt-controller@00a01000 { + intc: interrupt-controller@a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -153,13 +153,13 @@ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; }; - ocram: sram@00900000 { + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; clocks = <&clks IMX6SX_CLK_OCRAM>; }; - L2: l2-cache@00a02000 { + L2: l2-cache@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; @@ -169,7 +169,7 @@ arm,data-latency = <4 2 3>; }; - gpu: gpu@01800000 { + gpu: gpu@1800000 { compatible = "vivante,gc"; reg = <0x01800000 0x4000>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; @@ -179,7 +179,7 @@ clock-names = "bus", "core", "shader"; }; - dma_apbh: dma-apbh@01804000 { + dma_apbh: dma-apbh@1804000 { compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, @@ -192,7 +192,7 @@ clocks = <&clks IMX6SX_CLK_APBH_DMA>; }; - gpmi: gpmi-nand@01806000{ + gpmi: gpmi-nand@1806000{ compatible = "fsl,imx6sx-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; @@ -212,21 +212,21 @@ status = "disabled"; }; - aips1: aips-bus@02000000 { + aips1: aips-bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; - spba-bus@02000000 { + spba-bus@2000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x40000>; ranges; - spdif: spdif@02004000 { + spdif: spdif@2004000 { compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; @@ -248,7 +248,7 @@ status = "disabled"; }; - ecspi1: ecspi@02008000 { + ecspi1: ecspi@2008000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -260,7 +260,7 @@ status = "disabled"; }; - ecspi2: ecspi@0200c000 { + ecspi2: ecspi@200c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -272,7 +272,7 @@ status = "disabled"; }; - ecspi3: ecspi@02010000 { + ecspi3: ecspi@2010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -284,7 +284,7 @@ status = "disabled"; }; - ecspi4: ecspi@02014000 { + ecspi4: ecspi@2014000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -296,7 +296,7 @@ status = "disabled"; }; - uart1: serial@02020000 { + uart1: serial@2020000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; @@ -309,7 +309,7 @@ status = "disabled"; }; - esai: esai@02024000 { + esai: esai@2024000 { reg = <0x02024000 0x4000>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_ESAI_IPG>, @@ -322,7 +322,7 @@ status = "disabled"; }; - ssi1: ssi@02028000 { + ssi1: ssi@2028000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; @@ -336,7 +336,7 @@ status = "disabled"; }; - ssi2: ssi@0202c000 { + ssi2: ssi@202c000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; @@ -350,7 +350,7 @@ status = "disabled"; }; - ssi3: ssi@02030000 { + ssi3: ssi@2030000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; @@ -364,7 +364,7 @@ status = "disabled"; }; - asrc: asrc@02034000 { + asrc: asrc@2034000 { reg = <0x02034000 0x4000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_ASRC_MEM>, @@ -381,7 +381,7 @@ }; }; - pwm1: pwm@02080000 { + pwm1: pwm@2080000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; @@ -391,7 +391,7 @@ #pwm-cells = <2>; }; - pwm2: pwm@02084000 { + pwm2: pwm@2084000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; @@ -401,7 +401,7 @@ #pwm-cells = <2>; }; - pwm3: pwm@02088000 { + pwm3: pwm@2088000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -411,7 +411,7 @@ #pwm-cells = <2>; }; - pwm4: pwm@0208c000 { + pwm4: pwm@208c000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; @@ -421,7 +421,7 @@ #pwm-cells = <2>; }; - flexcan1: can@02090000 { + flexcan1: can@2090000 { compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; @@ -431,7 +431,7 @@ status = "disabled"; }; - flexcan2: can@02094000 { + flexcan2: can@2094000 { compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; @@ -441,7 +441,7 @@ status = "disabled"; }; - gpt: gpt@02098000 { + gpt: gpt@2098000 { compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt"; reg = <0x02098000 0x4000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -450,7 +450,7 @@ clock-names = "ipg", "per"; }; - gpio1: gpio@0209c000 { + gpio1: gpio@209c000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, @@ -462,7 +462,7 @@ gpio-ranges = <&iomuxc 0 5 26>; }; - gpio2: gpio@020a0000 { + gpio2: gpio@20a0000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, @@ -474,7 +474,7 @@ gpio-ranges = <&iomuxc 0 31 20>; }; - gpio3: gpio@020a4000 { + gpio3: gpio@20a4000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, @@ -486,7 +486,7 @@ gpio-ranges = <&iomuxc 0 51 29>; }; - gpio4: gpio@020a8000 { + gpio4: gpio@20a8000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, @@ -498,7 +498,7 @@ gpio-ranges = <&iomuxc 0 80 32>; }; - gpio5: gpio@020ac000 { + gpio5: gpio@20ac000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, @@ -510,7 +510,7 @@ gpio-ranges = <&iomuxc 0 112 24>; }; - gpio6: gpio@020b0000 { + gpio6: gpio@20b0000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020b0000 0x4000>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, @@ -522,7 +522,7 @@ gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; }; - gpio7: gpio@020b4000 { + gpio7: gpio@20b4000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020b4000 0x4000>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, @@ -534,7 +534,7 @@ gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; }; - kpp: kpp@020b8000 { + kpp: kpp@20b8000 { compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; @@ -542,14 +542,14 @@ status = "disabled"; }; - wdog1: wdog@020bc000 { + wdog1: wdog@20bc000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_DUMMY>; }; - wdog2: wdog@020c0000 { + wdog2: wdog@20c0000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; @@ -557,7 +557,7 @@ status = "disabled"; }; - clks: ccm@020c4000 { + clks: ccm@20c4000 { compatible = "fsl,imx6sx-ccm"; reg = <0x020c4000 0x4000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, @@ -567,7 +567,7 @@ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; }; - anatop: anatop@020c8000 { + anatop: anatop@20c8000 { compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; @@ -675,11 +675,12 @@ compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; }; - usbphy1: usbphy@020c9000 { + usbphy1: usbphy@20c9000 { compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; @@ -687,7 +688,7 @@ fsl,anatop = <&anatop>; }; - usbphy2: usbphy@020ca000 { + usbphy2: usbphy@20ca000 { compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -695,7 +696,7 @@ fsl,anatop = <&anatop>; }; - snvs: snvs@020cc000 { + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -724,17 +725,17 @@ }; }; - epit1: epit@020d0000 { + epit1: epit@20d0000 { reg = <0x020d0000 0x4000>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; }; - epit2: epit@020d4000 { + epit2: epit@20d4000 { reg = <0x020d4000 0x4000>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@020d8000 { + src: src@20d8000 { compatible = "fsl,imx6sx-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, @@ -742,7 +743,7 @@ #reset-cells = <1>; }; - gpc: gpc@020dc000 { + gpc: gpc@20dc000 { compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; interrupt-controller; @@ -751,18 +752,18 @@ interrupt-parent = <&intc>; }; - iomuxc: iomuxc@020e0000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6sx-iomuxc"; reg = <0x020e0000 0x4000>; }; - gpr: iomuxc-gpr@020e4000 { + gpr: iomuxc-gpr@20e4000 { compatible = "fsl,imx6sx-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e4000 0x4000>; }; - sdma: sdma@020ec000 { + sdma: sdma@20ec000 { compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -775,7 +776,7 @@ }; }; - aips2: aips-bus@02100000 { + aips2: aips-bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -809,7 +810,7 @@ }; }; - usbotg1: usb@02184000 { + usbotg1: usb@2184000 { compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; @@ -823,7 +824,7 @@ status = "disabled"; }; - usbotg2: usb@02184200 { + usbotg2: usb@2184200 { compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; @@ -836,7 +837,7 @@ status = "disabled"; }; - usbh: usb@02184400 { + usbh: usb@2184400 { compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; @@ -851,14 +852,14 @@ status = "disabled"; }; - usbmisc: usbmisc@02184800 { + usbmisc: usbmisc@2184800 { #index-cells = <1>; compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; clocks = <&clks IMX6SX_CLK_USBOH3>; }; - fec1: ethernet@02188000 { + fec1: ethernet@2188000 { compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, @@ -875,7 +876,7 @@ status = "disabled"; }; - mlb: mlb@0218c000 { + mlb: mlb@218c000 { reg = <0x0218c000 0x4000>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, @@ -884,7 +885,7 @@ status = "disabled"; }; - usdhc1: usdhc@02190000 { + usdhc1: usdhc@2190000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x02190000 0x4000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; @@ -896,7 +897,7 @@ status = "disabled"; }; - usdhc2: usdhc@02194000 { + usdhc2: usdhc@2194000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x02194000 0x4000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; @@ -908,7 +909,7 @@ status = "disabled"; }; - usdhc3: usdhc@02198000 { + usdhc3: usdhc@2198000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x02198000 0x4000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; @@ -920,7 +921,7 @@ status = "disabled"; }; - usdhc4: usdhc@0219c000 { + usdhc4: usdhc@219c000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; @@ -932,7 +933,7 @@ status = "disabled"; }; - i2c1: i2c@021a0000 { + i2c1: i2c@21a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; @@ -942,7 +943,7 @@ status = "disabled"; }; - i2c2: i2c@021a4000 { + i2c2: i2c@21a4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; @@ -952,7 +953,7 @@ status = "disabled"; }; - i2c3: i2c@021a8000 { + i2c3: i2c@21a8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; @@ -962,12 +963,12 @@ status = "disabled"; }; - mmdc: mmdc@021b0000 { + mmdc: mmdc@21b0000 { compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; }; - fec2: ethernet@021b4000 { + fec2: ethernet@21b4000 { compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; reg = <0x021b4000 0x4000>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, @@ -982,7 +983,7 @@ status = "disabled"; }; - weim: weim@021b8000 { + weim: weim@21b8000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; @@ -993,13 +994,23 @@ status = "disabled"; }; - ocotp: ocotp@021bc000 { + ocotp: ocotp@21bc000 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,imx6sx-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SX_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; - sai1: sai@021d4000 { + sai1: sai@21d4000 { compatible = "fsl,imx6sx-sai"; reg = <0x021d4000 0x4000>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; @@ -1012,13 +1023,13 @@ status = "disabled"; }; - audmux: audmux@021d8000 { + audmux: audmux@21d8000 { compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; reg = <0x021d8000 0x4000>; status = "disabled"; }; - sai2: sai@021dc000 { + sai2: sai@21dc000 { compatible = "fsl,imx6sx-sai"; reg = <0x021dc000 0x4000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; @@ -1031,7 +1042,7 @@ status = "disabled"; }; - qspi1: qspi@021e0000 { + qspi1: qspi@21e0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-qspi"; @@ -1044,7 +1055,7 @@ status = "disabled"; }; - qspi2: qspi@021e4000 { + qspi2: qspi@21e4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-qspi"; @@ -1057,7 +1068,7 @@ status = "disabled"; }; - uart2: serial@021e8000 { + uart2: serial@21e8000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; @@ -1070,7 +1081,7 @@ status = "disabled"; }; - uart3: serial@021ec000 { + uart3: serial@21ec000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; @@ -1083,7 +1094,7 @@ status = "disabled"; }; - uart4: serial@021f0000 { + uart4: serial@21f0000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; @@ -1096,7 +1107,7 @@ status = "disabled"; }; - uart5: serial@021f4000 { + uart5: serial@21f4000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; @@ -1109,7 +1120,7 @@ status = "disabled"; }; - i2c4: i2c@021f8000 { + i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; @@ -1120,21 +1131,21 @@ }; }; - aips3: aips-bus@02200000 { + aips3: aips-bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02200000 0x100000>; ranges; - spba-bus@02200000 { + spba-bus@2200000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02240000 0x40000>; ranges; - csi1: csi@02214000 { + csi1: csi@2214000 { reg = <0x02214000 0x4000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, @@ -1144,7 +1155,7 @@ status = "disabled"; }; - pxp: pxp@02218000 { + pxp: pxp@2218000 { reg = <0x02218000 0x4000>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_PXP_AXI>, @@ -1153,7 +1164,7 @@ status = "disabled"; }; - csi2: csi@0221c000 { + csi2: csi@221c000 { reg = <0x0221c000 0x4000>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, @@ -1163,7 +1174,7 @@ status = "disabled"; }; - lcdif1: lcdif@02220000 { + lcdif1: lcdif@2220000 { compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02220000 0x4000>; interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>; @@ -1174,7 +1185,7 @@ status = "disabled"; }; - lcdif2: lcdif@02224000 { + lcdif2: lcdif@2224000 { compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02224000 0x4000>; interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>; @@ -1185,7 +1196,7 @@ status = "disabled"; }; - vadc: vadc@02228000 { + vadc: vadc@2228000 { reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; reg-names = "vadc-vafe", "vadc-vdec"; clocks = <&clks IMX6SX_CLK_VADC>, @@ -1195,7 +1206,7 @@ }; }; - adc1: adc@02280000 { + adc1: adc@2280000 { compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; reg = <0x02280000 0x4000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; @@ -1206,7 +1217,7 @@ status = "disabled"; }; - adc2: adc@02284000 { + adc2: adc@2284000 { compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; reg = <0x02284000 0x4000>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; @@ -1217,7 +1228,7 @@ status = "disabled"; }; - wdog3: wdog@02288000 { + wdog3: wdog@2288000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x02288000 0x4000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; @@ -1225,7 +1236,7 @@ status = "disabled"; }; - ecspi5: ecspi@0228c000 { + ecspi5: ecspi@228c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -1237,7 +1248,7 @@ status = "disabled"; }; - uart6: serial@022a0000 { + uart6: serial@22a0000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x022a0000 0x4000>; @@ -1250,7 +1261,7 @@ status = "disabled"; }; - pwm5: pwm@022a4000 { + pwm5: pwm@22a4000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x022a4000 0x4000>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; @@ -1260,7 +1271,7 @@ #pwm-cells = <2>; }; - pwm6: pwm@022a8000 { + pwm6: pwm@22a8000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x022a8000 0x4000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; @@ -1270,7 +1281,7 @@ #pwm-cells = <2>; }; - pwm7: pwm@022ac000 { + pwm7: pwm@22ac000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x022ac000 0x4000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -1280,7 +1291,7 @@ #pwm-cells = <2>; }; - pwm8: pwm@0022b0000 { + pwm8: pwm@22b0000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x0022b0000 0x4000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts index 9c23e017d86a..e5d3ef88be60 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -147,6 +147,8 @@ &lcdif { + assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 7d7254b12a75..3bf26ebd4df9 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -175,7 +175,7 @@ reg = <1>; max-speed = <100>; interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW 0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -186,7 +186,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@08 { + pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; @@ -223,7 +223,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { reg = <0x0a>; compatible = "fsl,sgtl5000"; clocks = <&sys_mclk>; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts index 28d055e3f301..2d80f7b50bc0 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts +++ b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts @@ -116,7 +116,7 @@ }; &i2c2 { - /delete-node/ codec@0a; + /delete-node/ codec@a; /delete-node/ touchscreen@48; rtc: mcp7940x@6f { diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index ec745eb3b6a8..65111f9843f4 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -362,7 +362,7 @@ clock-frequency = <400000>; status = "okay"; - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; #sound-dai-cells = <0>; @@ -424,7 +424,7 @@ display = <&display>; status = "okay"; - display: display@di0 { + display: disp0 { bits-per-pixel = <32>; bus-width = <24>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index f11a241a340d..d5181f85ca9c 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -98,7 +98,7 @@ }; }; - intc: interrupt-controller@00a01000 { + intc: interrupt-controller@a01000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -149,12 +149,12 @@ status = "disabled"; }; - ocram: sram@00900000 { + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; }; - dma_apbh: dma-apbh@01804000 { + dma_apbh: dma-apbh@1804000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, @@ -167,7 +167,7 @@ clocks = <&clks IMX6UL_CLK_APBHDMA>; }; - gpmi: gpmi-nand@01806000 { + gpmi: gpmi-nand@1806000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; @@ -187,21 +187,21 @@ status = "disabled"; }; - aips1: aips-bus@02000000 { + aips1: aips-bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; - spba-bus@02000000 { + spba-bus@2000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x40000>; ranges; - ecspi1: ecspi@02008000 { + ecspi1: ecspi@2008000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -213,7 +213,7 @@ status = "disabled"; }; - ecspi2: ecspi@0200c000 { + ecspi2: ecspi@200c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -225,7 +225,7 @@ status = "disabled"; }; - ecspi3: ecspi@02010000 { + ecspi3: ecspi@2010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -237,7 +237,7 @@ status = "disabled"; }; - ecspi4: ecspi@02014000 { + ecspi4: ecspi@2014000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -249,7 +249,7 @@ status = "disabled"; }; - uart7: serial@02018000 { + uart7: serial@2018000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x02018000 0x4000>; @@ -260,7 +260,7 @@ status = "disabled"; }; - uart1: serial@02020000 { + uart1: serial@2020000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x02020000 0x4000>; @@ -271,7 +271,7 @@ status = "disabled"; }; - uart8: serial@02024000 { + uart8: serial@2024000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x02024000 0x4000>; @@ -282,7 +282,7 @@ status = "disabled"; }; - sai1: sai@02028000 { + sai1: sai@2028000 { #sound-dai-cells = <0>; compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; reg = <0x02028000 0x4000>; @@ -297,7 +297,7 @@ status = "disabled"; }; - sai2: sai@0202c000 { + sai2: sai@202c000 { #sound-dai-cells = <0>; compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; reg = <0x0202c000 0x4000>; @@ -312,7 +312,7 @@ status = "disabled"; }; - sai3: sai@02030000 { + sai3: sai@2030000 { #sound-dai-cells = <0>; compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; reg = <0x02030000 0x4000>; @@ -328,7 +328,7 @@ }; }; - tsc: tsc@02040000 { + tsc: tsc@2040000 { compatible = "fsl,imx6ul-tsc"; reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, @@ -339,7 +339,7 @@ status = "disabled"; }; - pwm1: pwm@02080000 { + pwm1: pwm@2080000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; @@ -350,7 +350,7 @@ status = "disabled"; }; - pwm2: pwm@02084000 { + pwm2: pwm@2084000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; @@ -361,7 +361,7 @@ status = "disabled"; }; - pwm3: pwm@02088000 { + pwm3: pwm@2088000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; @@ -372,7 +372,7 @@ status = "disabled"; }; - pwm4: pwm@0208c000 { + pwm4: pwm@208c000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -383,7 +383,7 @@ status = "disabled"; }; - can1: flexcan@02090000 { + can1: flexcan@2090000 { compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; @@ -393,7 +393,7 @@ status = "disabled"; }; - can2: flexcan@02094000 { + can2: flexcan@2094000 { compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; @@ -403,7 +403,7 @@ status = "disabled"; }; - gpt1: gpt@02098000 { + gpt1: gpt@2098000 { compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; reg = <0x02098000 0x4000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -412,7 +412,7 @@ clock-names = "ipg", "per"; }; - gpio1: gpio@0209c000 { + gpio1: gpio@209c000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, @@ -425,7 +425,7 @@ <&iomuxc 16 33 16>; }; - gpio2: gpio@020a0000 { + gpio2: gpio@20a0000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, @@ -437,7 +437,7 @@ gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; }; - gpio3: gpio@020a4000 { + gpio3: gpio@20a4000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, @@ -449,7 +449,7 @@ gpio-ranges = <&iomuxc 0 65 29>; }; - gpio4: gpio@020a8000 { + gpio4: gpio@20a8000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, @@ -461,7 +461,7 @@ gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; }; - gpio5: gpio@020ac000 { + gpio5: gpio@20ac000 { compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, @@ -473,7 +473,7 @@ gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; }; - fec2: ethernet@020b4000 { + fec2: ethernet@20b4000 { compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; reg = <0x020b4000 0x4000>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, @@ -490,7 +490,7 @@ status = "disabled"; }; - kpp: kpp@020b8000 { + kpp: kpp@20b8000 { compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; @@ -498,14 +498,14 @@ status = "disabled"; }; - wdog1: wdog@020bc000 { + wdog1: wdog@20bc000 { compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_WDOG1>; }; - wdog2: wdog@020c0000 { + wdog2: wdog@20c0000 { compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; @@ -513,7 +513,7 @@ status = "disabled"; }; - clks: ccm@020c4000 { + clks: ccm@20c4000 { compatible = "fsl,imx6ul-ccm"; reg = <0x020c4000 0x4000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, @@ -523,7 +523,7 @@ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; }; - anatop: anatop@020c8000 { + anatop: anatop@20c8000 { compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; @@ -580,7 +580,7 @@ }; }; - usbphy1: usbphy@020c9000 { + usbphy1: usbphy@20c9000 { compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; @@ -589,7 +589,7 @@ fsl,anatop = <&anatop>; }; - usbphy2: usbphy@020ca000 { + usbphy2: usbphy@20ca000 { compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -598,7 +598,16 @@ fsl,anatop = <&anatop>; }; - snvs: snvs@020cc000 { + tempmon: tempmon { + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + }; + + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -628,17 +637,17 @@ }; }; - epit1: epit@020d0000 { + epit1: epit@20d0000 { reg = <0x020d0000 0x4000>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; }; - epit2: epit@020d4000 { + epit2: epit@20d4000 { reg = <0x020d4000 0x4000>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@020d8000 { + src: src@20d8000 { compatible = "fsl,imx6ul-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, @@ -646,7 +655,7 @@ #reset-cells = <1>; }; - gpc: gpc@020dc000 { + gpc: gpc@20dc000 { compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; interrupt-controller; @@ -655,18 +664,18 @@ interrupt-parent = <&intc>; }; - iomuxc: iomuxc@020e0000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6ul-iomuxc"; reg = <0x020e0000 0x4000>; }; - gpr: iomuxc-gpr@020e4000 { + gpr: iomuxc-gpr@20e4000 { compatible = "fsl,imx6ul-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e4000 0x4000>; }; - gpt2: gpt@020e8000 { + gpt2: gpt@20e8000 { compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; reg = <0x020e8000 0x4000>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; @@ -675,7 +684,7 @@ clock-names = "ipg", "per"; }; - sdma: sdma@020ec000 { + sdma: sdma@20ec000 { compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; @@ -687,7 +696,7 @@ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; - pwm5: pwm@020f0000 { + pwm5: pwm@20f0000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f0000 0x4000>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; @@ -698,7 +707,7 @@ status = "disabled"; }; - pwm6: pwm@020f4000 { + pwm6: pwm@20f4000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f4000 0x4000>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; @@ -709,7 +718,7 @@ status = "disabled"; }; - pwm7: pwm@020f8000 { + pwm7: pwm@20f8000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f8000 0x4000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; @@ -720,7 +729,7 @@ status = "disabled"; }; - pwm8: pwm@020fc000 { + pwm8: pwm@20fc000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020fc000 0x4000>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; @@ -732,14 +741,14 @@ }; }; - aips2: aips-bus@02100000 { + aips2: aips-bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; - usbotg1: usb@02184000 { + usbotg1: usb@2184000 { compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; @@ -753,7 +762,7 @@ status = "disabled"; }; - usbotg2: usb@02184200 { + usbotg2: usb@2184200 { compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; @@ -766,13 +775,13 @@ status = "disabled"; }; - usbmisc: usbmisc@02184800 { + usbmisc: usbmisc@2184800 { #index-cells = <1>; compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; }; - fec1: ethernet@02188000 { + fec1: ethernet@2188000 { compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, @@ -789,7 +798,7 @@ status = "disabled"; }; - usdhc1: usdhc@02190000 { + usdhc1: usdhc@2190000 { compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; reg = <0x02190000 0x4000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; @@ -801,7 +810,7 @@ status = "disabled"; }; - usdhc2: usdhc@02194000 { + usdhc2: usdhc@2194000 { compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; reg = <0x02194000 0x4000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; @@ -813,7 +822,7 @@ status = "disabled"; }; - adc1: adc@02198000 { + adc1: adc@2198000 { compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; reg = <0x02198000 0x4000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; @@ -825,7 +834,7 @@ status = "disabled"; }; - i2c1: i2c@021a0000 { + i2c1: i2c@21a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; @@ -835,7 +844,7 @@ status = "disabled"; }; - i2c2: i2c@021a4000 { + i2c2: i2c@21a4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; @@ -845,7 +854,7 @@ status = "disabled"; }; - i2c3: i2c@021a8000 { + i2c3: i2c@21a8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; @@ -855,18 +864,28 @@ status = "disabled"; }; - mmdc: mmdc@021b0000 { + mmdc: mmdc@21b0000 { compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; }; - ocotp: ocotp-ctrl@021bc000 { + ocotp: ocotp-ctrl@21bc000 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,imx6ul-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6UL_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; - lcdif: lcdif@021c8000 { + lcdif: lcdif@21c8000 { compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; reg = <0x021c8000 0x4000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; @@ -877,7 +896,7 @@ status = "disabled"; }; - qspi: qspi@021e0000 { + qspi: qspi@21e0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; @@ -890,7 +909,7 @@ status = "disabled"; }; - uart2: serial@021e8000 { + uart2: serial@21e8000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021e8000 0x4000>; @@ -901,7 +920,7 @@ status = "disabled"; }; - uart3: serial@021ec000 { + uart3: serial@21ec000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021ec000 0x4000>; @@ -912,7 +931,7 @@ status = "disabled"; }; - uart4: serial@021f0000 { + uart4: serial@21f0000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021f0000 0x4000>; @@ -923,7 +942,7 @@ status = "disabled"; }; - uart5: serial@021f4000 { + uart5: serial@21f4000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021f4000 0x4000>; @@ -934,7 +953,7 @@ status = "disabled"; }; - i2c4: i2c@021f8000 { + i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; @@ -944,7 +963,7 @@ status = "disabled"; }; - uart6: serial@021fc000 { + uart6: serial@21fc000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; reg = <0x021fc000 0x4000>; diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 0a3915868aa3..bb5bf94f1a32 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -121,7 +121,7 @@ pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { compatible = "fsl,sgtl5000"; #sound-dai-cells = <0>; reg = <0x0a>; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index e7998308861f..2b05898bb3f6 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -181,7 +181,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@08 { + pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx7d-pico.dts b/arch/arm/boot/dts/imx7d-pico.dts index e78c2c9cc28a..508328b2a6bf 100644 --- a/arch/arm/boot/dts/imx7d-pico.dts +++ b/arch/arm/boot/dts/imx7d-pico.dts @@ -52,6 +52,17 @@ reg = <0x80000000 0x80000000>; }; + reg_ap6212: regulator-ap6212 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_ap6212>; + regulator-name = "AP6212"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_2p5v: regulator-2p5v { compatible = "regulator-fixed"; regulator-name = "2P5V"; @@ -137,7 +148,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { #sound-dai-cells = <0>; reg = <0x0a>; compatible = "fsl,sgtl5000"; @@ -152,7 +163,7 @@ pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; - pmic: pfuze3000@08 { + pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; @@ -271,6 +282,17 @@ status = "okay"; }; +&usdhc2 { /* Wifi SDIO */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_ap6212>; + status = "okay"; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -326,6 +348,12 @@ >; }; + pinctrl_reg_ap6212: regap6212grp { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 + >; + }; + pinctrl_sai1: sai1grp { fsl,pins = < MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f @@ -348,6 +376,17 @@ >; }; + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x59 diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 44637cabcc56..a7a5dc7b2700 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -241,7 +241,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@08 { + pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 07b63f8b7314..9bdf121f7e43 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -122,7 +122,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@08 { + pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; @@ -226,7 +226,7 @@ pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { #sound-dai-cells = <0>; reg = <0x0a>; compatible = "fsl,sgtl5000"; diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index 380f9ae60c78..4d58638d104b 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi @@ -11,7 +11,7 @@ reg = <0x10000000 0x200>; /* Use core module LED to indicate CPU load */ - led@0c.0 { + led@c.0 { compatible = "register-bit-led"; offset = <0x0c>; mask = <0x01>; @@ -100,7 +100,7 @@ compatible = "syscon", "simple-mfd"; reg = <0x1a000000 0x10>; - led@04.0 { + led@4.0 { compatible = "register-bit-led"; offset = <0x04>; mask = <0x01>; @@ -108,21 +108,21 @@ linux,default-trigger = "heartbeat"; default-state = "on"; }; - led@04.1 { + led@4.1 { compatible = "register-bit-led"; offset = <0x04>; mask = <0x02>; label = "integrator:yellow"; default-state = "off"; }; - led@04.2 { + led@4.2 { compatible = "register-bit-led"; offset = <0x04>; mask = <0x04>; label = "integrator:red"; default-state = "off"; }; - led@04.3 { + led@4.3 { compatible = "register-bit-led"; offset = <0x04>; mask = <0x08>; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index a5d88a213dcd..94d2ff9836d0 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -154,21 +154,26 @@ }; pci: pciv3@62000000 { - compatible = "v3,v360epc-pci"; + compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <0x62000000 0x10000>; + /* Bridge registers and config access space */ + reg = <0x62000000 0x10000>, <0x61000000 0x01000000>; interrupt-parent = <&pic>; interrupts = <17>; /* Bus error IRQ */ - ranges = <0x00000000 0 0x61000000 /* config space */ - 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */ - 0x01000000 0 0x0 /* I/O space */ - 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */ - 0x02000000 0 0x00000000 /* non-prefectable memory */ - 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */ - 0x42000000 0 0x10000000 /* prefetchable memory */ - 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */ + clocks = <&pciclk>; + bus-range = <0x00 0xff>; + ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */ + 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */ + 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */ + 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */ + 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */ + 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */ + dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */ + 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */ + 0x02000000 0 0x80000000 /* Core module alias memory */ + 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */ interrupt-map-mask = <0xf800 0 0 0x7>; interrupt-map = < /* IDSEL 9 */ diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi new file mode 100644 index 000000000000..efd8af9242d1 --- /dev/null +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -0,0 +1,152 @@ +/* + * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/ { + aliases { + serial0 = &scif0; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + reg = <3>; + micrel,led-mode = <1>; + }; +}; + +&hsusb { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + }; +}; + +&pci0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&pfc { + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + scif0_pins: scif0 { + groups = "scif0_data_d"; + function = "scif0"; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi new file mode 100644 index 000000000000..31fab5f183a9 --- /dev/null +++ b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi @@ -0,0 +1,43 @@ +/* + * Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/ { + aliases { + serial1 = &scif1; + serial4 = &hscif1; + }; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&pfc { + hscif1_pins: hscif1 { + groups = "hscif1_data_c", "hscif1_ctrl_c"; + function = "hscif1"; + }; + + scif1_pins: scif1 { + groups = "scif1_data_d"; + function = "scif1"; + }; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index 819ab8345916..6b796b52ff4f 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -88,7 +88,7 @@ }; }; - msm_ram: msmram@0c000000 { + msm_ram: msmram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x200000>; ranges = <0x0 0x0c000000 0x200000>; @@ -100,7 +100,7 @@ }; }; - psc: power-sleep-controller@02350000 { + psc: power-sleep-controller@2350000 { pscrst: reset-controller { compatible = "ti,k2e-pscrst", "ti,syscon-reset"; #reset-cells = <1>; @@ -111,7 +111,7 @@ }; }; - dspgpio0: keystone_dsp_gpio@02620240 { + dspgpio0: keystone_dsp_gpio@2620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index f462f1043531..656af194a518 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -45,6 +45,22 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + ecap0_pins: ecap0_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */ + >; + }; + + spi1_pins: pinmux_spi1_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */ + K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */ + K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */ + K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */ + >; + }; + }; &k2g_pinctrl { @@ -81,6 +97,14 @@ K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ >; }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + >; + }; + }; &uart0 { @@ -112,3 +136,72 @@ memory-region = <&dsp_common_memory>; status = "okay"; }; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c1024"; + reg = <0x50>; + }; +}; + +&keystone_usb0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; + status = "okay"; +}; + +&keystone_usb1 { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; + + spi_nor: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <5000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x100000 0xf00000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 826b286665e6..8f313ff406b9 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -28,6 +28,9 @@ aliases { serial0 = &uart0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; rproc0 = &dsp0; }; @@ -42,7 +45,7 @@ }; }; - gic: interrupt-controller@02561000 { + gic: interrupt-controller@2561000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -80,7 +83,7 @@ ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; - msm_ram: msmram@0c000000 { + msm_ram: msmram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x100000>; ranges = <0x0 0x0c000000 0x100000>; @@ -92,19 +95,19 @@ }; }; - k2g_pinctrl: pinmux@02621000 { + k2g_pinctrl: pinmux@2621000 { compatible = "pinctrl-single"; reg = <0x02621000 0x410>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x001b0007>; }; - devctrl: device-state-control@02620000 { + devctrl: device-state-control@2620000 { compatible = "ti,keystone-devctrl", "syscon"; reg = <0x02620000 0x1000>; }; - uart0: serial@02530c00 { + uart0: serial@2530c00 { compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; @@ -115,7 +118,7 @@ status = "disabled"; }; - dcan0: can@0260B200 { + dcan0: can@260b200 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; reg = <0x0260B200 0x200>; interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; @@ -124,7 +127,7 @@ clocks = <&k2g_clks 0x0008 1>; }; - dcan1: can@0260B400 { + dcan1: can@260b400 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; reg = <0x0260B400 0x200>; interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; @@ -133,7 +136,40 @@ clocks = <&k2g_clks 0x0009 1>; }; - kirq0: keystone_irq@026202a0 { + i2c0: i2c@2530000 { + compatible = "ti,keystone-i2c"; + reg = <0x02530000 0x400>; + clocks = <&k2g_clks 0x003a 0>; + power-domains = <&k2g_pds 0x003a>; + interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@2530400 { + compatible = "ti,keystone-i2c"; + reg = <0x02530400 0x400>; + clocks = <&k2g_clks 0x003b 0>; + power-domains = <&k2g_pds 0x003b>; + interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@2530800 { + compatible = "ti,keystone-i2c"; + reg = <0x02530800 0x400>; + clocks = <&k2g_clks 0x003c 0>; + power-domains = <&k2g_pds 0x003c>; + interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + kirq0: keystone_irq@26202a0 { compatible = "ti,keystone-irq"; interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>; interrupt-controller; @@ -141,7 +177,7 @@ ti,syscon-dev = <&devctrl 0x2a0>; }; - dspgpio0: keystone_dsp_gpio@02620240 { + dspgpio0: keystone_dsp_gpio@2620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; #gpio-cells = <2>; @@ -164,7 +200,7 @@ status = "disabled"; }; - msgmgr: msgmgr@02a00000 { + msgmgr: msgmgr@2a00000 { compatible = "ti,k2g-message-manager"; #mbox-cells = <2>; reg-names = "queue_proxy_region", @@ -176,7 +212,7 @@ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; }; - pmmc: pmmc@02921c00 { + pmmc: pmmc@2921c00 { compatible = "ti,k2g-sci"; /* * In case of rare platforms that does not use k2g as @@ -246,7 +282,7 @@ clock-names = "gpio"; }; - edma0: edma@02700000 { + edma0: edma@2700000 { compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; reg = <0x02700000 0x8000>; reg-names = "edma3_cc"; @@ -265,19 +301,19 @@ power-domains = <&k2g_pds 0x3f>; }; - edma0_tptc0: tptc@02760000 { + edma0_tptc0: tptc@2760000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; reg = <0x02760000 0x400>; power-domains = <&k2g_pds 0x3f>; }; - edma0_tptc1: tptc@02768000 { + edma0_tptc1: tptc@2768000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; reg = <0x02768000 0x400>; power-domains = <&k2g_pds 0x3f>; }; - edma1: edma@02728000 { + edma1: edma@2728000 { compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; reg = <0x02728000 0x8000>; reg-names = "edma3_cc"; @@ -300,13 +336,13 @@ power-domains = <&k2g_pds 0x4f>; }; - edma1_tptc0: tptc@027b0000 { + edma1_tptc0: tptc@27b0000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; reg = <0x027b0000 0x400>; power-domains = <&k2g_pds 0x4f>; }; - edma1_tptc1: tptc@027b8000 { + edma1_tptc1: tptc@27b8000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; reg = <0x027b8000 0x400>; power-domains = <&k2g_pds 0x4f>; @@ -343,5 +379,177 @@ clock-names = "fck", "mmchsdb_fck"; status = "disabled"; }; + + mcasp0: mcasp@2340000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x02340000 0x2000>, + <0x21804000 0x1000>; + reg-names = "mpu","dat"; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + dmas = <&edma0 24 1>, <&edma0 25 1>; + dma-names = "tx", "rx"; + power-domains = <&k2g_pds 0x4>; + clocks = <&k2g_clks 0x4 0>; + clock-names = "fck"; + status = "disabled"; + }; + + mcasp1: mcasp@2342000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x02342000 0x2000>, + <0x21804400 0x1000>; + reg-names = "mpu","dat"; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + dmas = <&edma1 48 1>, <&edma1 49 1>; + dma-names = "tx", "rx"; + power-domains = <&k2g_pds 0x5>; + clocks = <&k2g_clks 0x5 0>; + clock-names = "fck"; + status = "disabled"; + }; + + mcasp2: mcasp@2344000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x02344000 0x2000>, + <0x21804800 0x1000>; + reg-names = "mpu","dat"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + dmas = <&edma1 50 1>, <&edma1 51 1>; + dma-names = "tx", "rx"; + power-domains = <&k2g_pds 0x6>; + clocks = <&k2g_clks 0x6 0>; + clock-names = "fck"; + status = "disabled"; + }; + + usb0_phy: usb-phy@0 { + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; + + keystone_usb0: keystone-dwc3@2680000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2680000 0x10000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + power-domains = <&k2g_pds 0x0016>; + + usb0: usb@2690000 { + compatible = "snps,dwc3"; + reg = <0x2690000 0x10000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + usb-phy = <&usb0_phy>; + status = "disabled"; + }; + }; + + usb1_phy: usb-phy@1 { + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; + + keystone_usb1: keystone-dwc3@2580000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2580000 0x10000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + power-domains = <&k2g_pds 0x0017>; + + usb1: usb@2590000 { + compatible = "snps,dwc3"; + reg = <0x2590000 0x10000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + usb-phy = <&usb1_phy>; + status = "disabled"; + }; + }; + + ecap0: pwm@21d1800 { + compatible = "ti,k2g-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x021d1800 0x60>; + power-domains = <&k2g_pds 0x38>; + clocks = <&k2g_clks 0x38 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap1: pwm@21d1c00 { + compatible = "ti,k2g-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x021d1c00 0x60>; + power-domains = <&k2g_pds 0x39>; + clocks = <&k2g_clks 0x39 0x0>; + clock-names = "fck"; + status = "disabled"; + }; + + spi0: spi@21805400 { + compatible = "ti,keystone-spi"; + reg = <0x21805400 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k2g_pds 0x0010>; + clocks = <&k2g_clks 0x0010 0>; + }; + + spi1: spi@21805800 { + compatible = "ti,keystone-spi"; + reg = <0x21805800 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k2g_pds 0x0011>; + clocks = <&k2g_clks 0x0011 0>; + }; + + spi2: spi@21805c00 { + compatible = "ti,keystone-spi"; + reg = <0x21805C00 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k2g_pds 0x0012>; + clocks = <&k2g_clks 0x0012 0>; + }; + + spi3: spi@21806000 { + compatible = "ti,keystone-spi"; + reg = <0x21806000 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k2g_pds 0x0013>; + clocks = <&k2g_clks 0x0013 0>; + }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi index 31dc00e4e5fd..7c486d9dc90e 100644 --- a/arch/arm/boot/dts/keystone-k2hk.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk.dtsi @@ -59,7 +59,7 @@ soc { /include/ "keystone-k2hk-clocks.dtsi" - msm_ram: msmram@0c000000 { + msm_ram: msmram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x600000>; ranges = <0x0 0x0c000000 0x600000>; @@ -71,7 +71,7 @@ }; }; - psc: power-sleep-controller@02350000 { + psc: power-sleep-controller@2350000 { pscrst: reset-controller { compatible = "ti,k2hk-pscrst", "ti,syscon-reset"; #reset-cells = <1>; @@ -89,7 +89,7 @@ }; }; - dspgpio0: keystone_dsp_gpio@02620240 { + dspgpio0: keystone_dsp_gpio@2620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; #gpio-cells = <2>; @@ -273,7 +273,7 @@ status = "disabled"; }; - mdio: mdio@02090300 { + mdio: mdio@2090300 { compatible = "ti,keystone_mdio", "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index 4431310bc922..4370e6513aa4 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -43,7 +43,7 @@ soc { /include/ "keystone-k2l-clocks.dtsi" - uart2: serial@02348400 { + uart2: serial@2348400 { compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; @@ -53,7 +53,7 @@ interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>; }; - uart3: serial@02348800 { + uart3: serial@2348800 { compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; @@ -63,7 +63,7 @@ interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>; }; - k2l_pmx: pinmux@02620690 { + k2l_pmx: pinmux@2620690 { compatible = "pinctrl-single"; reg = <0x02620690 0xc>; #address-cells = <1>; @@ -213,7 +213,7 @@ }; }; - msm_ram: msmram@0c000000 { + msm_ram: msmram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x200000>; ranges = <0x0 0x0c000000 0x200000>; @@ -225,7 +225,7 @@ }; }; - psc: power-sleep-controller@02350000 { + psc: power-sleep-controller@2350000 { pscrst: reset-controller { compatible = "ti,k2l-pscrst", "ti,syscon-reset"; #reset-cells = <1>; @@ -247,7 +247,7 @@ clocks = <&clkosr>; }; - dspgpio0: keystone_dsp_gpio@02620240 { + dspgpio0: keystone_dsp_gpio@2620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 8dd74f48a6d3..06e10544f9b1 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -78,17 +78,17 @@ ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; - pllctrl: pll-controller@02310000 { + pllctrl: pll-controller@2310000 { compatible = "ti,keystone-pllctrl", "syscon"; reg = <0x02310000 0x200>; }; - psc: power-sleep-controller@02350000 { + psc: power-sleep-controller@2350000 { compatible = "syscon", "simple-mfd"; reg = <0x02350000 0x1000>; }; - devctrl: device-state-control@02620000 { + devctrl: device-state-control@2620000 { compatible = "ti,keystone-devctrl", "syscon"; reg = <0x02620000 0x1000>; }; @@ -102,7 +102,7 @@ /include/ "keystone-clocks.dtsi" - uart0: serial@02530c00 { + uart0: serial@2530c00 { compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; @@ -112,7 +112,7 @@ interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; }; - uart1: serial@02531000 { + uart1: serial@2531000 { compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; @@ -214,7 +214,7 @@ }; }; - wdt: wdt@022f0080 { + wdt: wdt@22f0080 { compatible = "ti,keystone-wdt","ti,davinci-wdt"; reg = <0x022f0080 0x80>; clocks = <&clkwdtimer0>; diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi index 65e9524e852a..210d21a65bd1 100644 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi @@ -208,32 +208,32 @@ spi-max-frequency = <20000000>; mode = <0>; - partition@00000000 { + partition@0 { reg = <0x00000000 0x00080000>; label = "RedBoot"; }; - partition@00080000 { + partition@80000 { reg = <0x00080000 0x00200000>; label = "zImage"; }; - partition@00280000 { + partition@280000 { reg = <0x00280000 0x00140000>; label = "rd.gz"; }; - partition@003c0000 { + partition@3c0000 { reg = <0x003c0000 0x00010000>; label = "vendor"; }; - partition@003d0000 { + partition@3d0000 { reg = <0x003d0000 0x00020000>; label = "RedBoot config"; }; - partition@003f0000 { + partition@3f0000 { reg = <0x003f0000 0x00010000>; label = "FIS directory"; }; diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 4faea1d9facf..a88eb22070a1 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -45,29 +45,29 @@ spi-max-frequency = <20000000>; mode = <0>; - partition@0000000 { + partition@0 { reg = <0x00000000 0x00080000>; label = "U-Boot"; }; - partition@00200000 { + partition@200000 { reg = <0x00200000 0x00200000>; label = "Kernel"; }; - partition@00400000 { + partition@400000 { reg = <0x00400000 0x00900000>; label = "RootFS1"; }; - partition@00d00000 { + partition@d00000 { reg = <0x00d00000 0x00300000>; label = "RootFS2"; }; - partition@00040000 { + partition@40000 { reg = <0x00080000 0x00040000>; label = "U-Boot Config"; }; - partition@000c0000 { + partition@c0000 { reg = <0x000c0000 0x00140000>; label = "NAS Config"; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index a70fc7f01fc3..eb2bf7409655 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -41,7 +41,7 @@ pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ - nand: nand@012f { + nand: nand@12f { #address-cells = <1>; #size-cells = <1>; cle = <0>; @@ -57,7 +57,7 @@ status = "disabled"; }; - crypto_sram: sa-sram@0301 { + crypto_sram: sa-sram@301 { compatible = "mmio-sram"; reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>; clocks = <&gate_clk 17>; diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts index 52b3ed10283a..c43adb7b4d7c 100644 --- a/arch/arm/boot/dts/lpc3250-ea3250.dts +++ b/arch/arm/boot/dts/lpc3250-ea3250.dts @@ -231,24 +231,24 @@ #address-cells = <1>; #size-cells = <1>; - mtd0@00000000 { + mtd0@0 { label = "ea3250-boot"; reg = <0x00000000 0x00080000>; read-only; }; - mtd1@00080000 { + mtd1@80000 { label = "ea3250-uboot"; reg = <0x00080000 0x000c0000>; read-only; }; - mtd2@00140000 { + mtd2@140000 { label = "ea3250-kernel"; reg = <0x00140000 0x00400000>; }; - mtd3@00540000 { + mtd3@540000 { label = "ea3250-rootfs"; reg = <0x00540000 0x07ac0000>; }; diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index fd95e2b10357..c72eb9845603 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -154,29 +154,29 @@ #address-cells = <1>; #size-cells = <1>; - mtd0@00000000 { + mtd0@0 { label = "phy3250-boot"; reg = <0x00000000 0x00064000>; read-only; }; - mtd1@00064000 { + mtd1@64000 { label = "phy3250-uboot"; reg = <0x00064000 0x00190000>; read-only; }; - mtd2@001f4000 { + mtd2@1f4000 { label = "phy3250-ubt-prms"; reg = <0x001f4000 0x00010000>; }; - mtd3@00204000 { + mtd3@204000 { label = "phy3250-kernel"; reg = <0x00204000 0x00400000>; }; - mtd4@00604000 { + mtd4@604000 { label = "phy3250-rootfs"; reg = <0x00604000 0x039fc000>; }; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index d81fe433e3c8..abff7ef7c9cd 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -55,7 +55,7 @@ <0x20000000 0x20000000 0x30000000>, <0xe0000000 0xe0000000 0x04000000>; - iram: sram@08000000 { + iram: sram@8000000 { compatible = "mmio-sram"; reg = <0x08000000 0x20000>; diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index cd6ad072e72c..4926133077b3 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -80,6 +80,20 @@ #size-cells = <1>; ranges = <0x0 0xc1100000 0x200000>; + assist: assist@7c00 { + compatible = "amlogic,meson-mx-assist", "syscon"; + reg = <0x7c00 0x200>; + }; + + gpio_intc: interrupt-controller@9880 { + compatible = "amlogic,meson-gpio-intc"; + reg = <0xc1109880 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + status = "disabled"; + }; + hwrng: rng@8100 { compatible = "amlogic,meson-rng"; reg = <0x8100 0x8>; @@ -160,6 +174,15 @@ status = "disabled"; }; + sdio: mmc@8c20 { + compatible = "amlogic,meson-mx-sdio"; + reg = <0x8c20 0x20>; + interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spifc: spi@8c80 { compatible = "amlogic,meson6-spifc"; reg = <0x8c80 0x80>; @@ -217,7 +240,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0xc9040000 0x40000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb0_phy>; phy-names = "usb2-phy"; dr_mode = "host"; @@ -229,7 +252,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0xc90c0000 0x40000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb1_phy>; phy-names = "usb2-phy"; dr_mode = "host"; @@ -252,5 +275,25 @@ #size-cells = <1>; ranges = <0 0xd9000000 0x20000>; }; + + bootrom: bootrom@d9040000 { + compatible = "amlogic,meson-mx-bootrom", "syscon"; + reg = <0xd9040000 0x10000>; + }; + + secbus: secbus@da000000 { + compatible = "simple-bus"; + reg = <0xda000000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xda000000 0x6000>; + + efuse: nvmem@0 { + compatible = "amlogic,meson6-efuse"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; }; }; /* end of / */ diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index ef281d290052..9b463211339f 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -84,6 +84,9 @@ }; }; /* end of / */ +&efuse { + status = "disabled"; +}; &uart_AO { clocks = <&xtal>, <&clk81>, <&clk81>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index b98d44fde6b6..2d7a0752a460 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -45,6 +45,7 @@ #include <dt-bindings/clock/meson8b-clkc.h> #include <dt-bindings/gpio/meson8-gpio.h> +#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> #include "meson.dtsi" / { @@ -60,6 +61,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x200>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; }; cpu@201 { @@ -67,6 +70,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x201>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; }; cpu@202 { @@ -74,6 +79,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x202>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; }; cpu@203 { @@ -81,6 +88,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x203>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; }; }; @@ -118,6 +127,11 @@ }; /* end of / */ &aobus { + pmu: pmu@e0 { + compatible = "amlogic,meson8-pmu", "syscon"; + reg = <0xe0 0x8>; + }; + pinctrl_aobus: pinctrl@84 { compatible = "amlogic,meson8-aobus-pinctrl"; reg = <0x84 0xc>; @@ -132,7 +146,7 @@ reg-names = "mux", "pull", "gpio"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 120 16>; + gpio-ranges = <&pinctrl_aobus 0 0 16>; }; uart_ao_a_pins: uart_ao_a { @@ -173,6 +187,11 @@ reg = <0x8000 0x4>, <0x4000 0x460>; }; + analog_top: analog-top@81a8 { + compatible = "amlogic,meson8-analog-top", "syscon"; + reg = <0x81a8 0x14>; + }; + pwm_ef: pwm@86c0 { compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; reg = <0x86c0 0x10>; @@ -249,6 +268,19 @@ }; }; +&ahb_sram { + smp-sram@1ff80 { + compatible = "amlogic,meson8-smp-sram"; + reg = <0x1ff80 0x8>; + }; +}; + +&efuse { + compatible = "amlogic,meson8-efuse"; + clocks = <&clkc CLKID_EFUSE>; + clock-names = "core"; +}; + ðmac { clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; @@ -294,6 +326,12 @@ clock-names = "clkin", "core", "sana"; }; +&sdio { + compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; + clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; + clock-names = "core", "clkin"; +}; + &spifc { clocks = <&clkc CLKID_CLK81>; }; diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index e50f1a1fdbc7..9ff6ca4e20d0 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -76,3 +76,26 @@ pinctrl-0 = <&uart_ao_a_pins>; pinctrl-names = "default"; }; + +&gpio_ao { + /* + * WARNING: The USB Hub on the Odroid-C1/C1+ needs a reset signal + * to be turned high in order to be detected by the USB Controller. + * This signal should be handled by a USB specific power sequence + * in order to reset the Hub when USB bus is powered down. + */ + usb-hub { + gpio-hog; + gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index bc278da7df0d..d75e0ceda8bb 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -47,6 +47,7 @@ #include <dt-bindings/clock/meson8b-clkc.h> #include <dt-bindings/gpio/meson8b-gpio.h> #include <dt-bindings/reset/amlogic,meson8b-reset.h> +#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> #include "meson.dtsi" / { @@ -59,6 +60,8 @@ compatible = "arm,cortex-a5"; next-level-cache = <&L2>; reg = <0x200>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; }; cpu@201 { @@ -66,6 +69,8 @@ compatible = "arm,cortex-a5"; next-level-cache = <&L2>; reg = <0x201>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; }; cpu@202 { @@ -73,6 +78,8 @@ compatible = "arm,cortex-a5"; next-level-cache = <&L2>; reg = <0x202>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; }; cpu@203 { @@ -80,6 +87,20 @@ compatible = "arm,cortex-a5"; next-level-cache = <&L2>; reg = <0x203>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* 2 MiB reserved for Hardware ROM Firmware? */ + hwrom@0 { + reg = <0x0 0x200000>; + no-map; }; }; @@ -90,6 +111,11 @@ }; /* end of / */ &aobus { + pmu: pmu@e0 { + compatible = "amlogic,meson8b-pmu", "syscon"; + reg = <0xe0 0x18>; + }; + pinctrl_aobus: pinctrl@84 { compatible = "amlogic,meson8b-aobus-pinctrl"; reg = <0x84 0xc>; @@ -104,7 +130,7 @@ reg-names = "mux", "pull", "gpio"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 130 16>; + gpio-ranges = <&pinctrl_aobus 0 0 16>; }; uart_ao_a_pins: uart_ao_a { @@ -130,6 +156,11 @@ #reset-cells = <1>; }; + analog_top: analog-top@81a8 { + compatible = "amlogic,meson8b-analog-top", "syscon"; + reg = <0x81a8 0x14>; + }; + pwm_ef: pwm@86c0 { compatible = "amlogic,meson8b-pwm"; reg = <0x86c0 0x10>; @@ -157,11 +188,31 @@ }; }; +&ahb_sram { + smp-sram@1ff80 { + compatible = "amlogic,meson8b-smp-sram"; + reg = <0x1ff80 0x8>; + }; +}; + + +&efuse { + compatible = "amlogic,meson8b-efuse"; + clocks = <&clkc CLKID_EFUSE>; + clock-names = "core"; +}; + ðmac { clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; }; +&gpio_intc { + compatible = "amlogic,meson-gpio-intc", + "amlogic,meson8b-gpio-intc"; + status = "okay"; +}; + &hwrng { compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; @@ -190,6 +241,12 @@ clock-names = "clkin", "core", "sana"; }; +&sdio { + compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; + clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; + clock-names = "core", "clkin"; +}; + &uart_AO { clocks = <&clkc CLKID_CLK81>; }; diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts index 116ce78bea4f..36cfa215620d 100644 --- a/arch/arm/boot/dts/mpa1600.dts +++ b/arch/arm/boot/dts/mpa1600.dts @@ -46,7 +46,7 @@ }; }; - usb0: ohci@00300000 { + usb0: ohci@300000 { num-ports = <1>; status = "okay"; }; diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts index f48497354221..63af4b13a36f 100644 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ b/arch/arm/boot/dts/mt2701-evb.dts @@ -56,12 +56,29 @@ bt_sco_codec:bt_sco_codec { compatible = "linux,bt-sco"; }; + + backlight_lcd: backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&bls 0 100000>; + brightness-levels = < + 0 16 32 48 64 80 96 112 + 128 144 160 176 192 208 224 240 + 255 + >; + default-brightness-level = <9>; + }; }; &auxadc { status = "okay"; }; +&bls { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_bls_gpio>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -111,6 +128,12 @@ }; }; + pwm_bls_gpio: pwm_bls_gpio { + pins_cmd_dat { + pinmux = <MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM>; + }; + }; + spi_pins_a: spi0@0 { pins_spi { pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>, diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index afe12e5b51f9..965ddfbc9953 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -430,7 +430,9 @@ compatible = "mediatek,mt2701-audio"; reg = <0 0x11220000 0 0x2000>, <0 0x112a0000 0 0x20000>; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "afe", "asys"; power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; clocks = <&infracfg CLK_INFRA_AUDIO>, @@ -530,6 +532,15 @@ #clock-cells = <1>; }; + bls: pwm@1400a000 { + compatible = "mediatek,mt2701-disp-pwm"; + reg = <0 0x1400a000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>; + clock-names = "main", "mm"; + status = "disabled"; + }; + larb0: larb@14010000 { compatible = "mediatek,mt2701-smi-larb"; reg = <0 0x14010000 0 0x1000>; diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index 0d6f60af7640..41df742d7891 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -139,7 +139,7 @@ status = "disabled"; }; - wdt: watchdog@010000000 { + wdt: watchdog@10000000 { compatible = "mediatek,mt6589-wdt"; reg = <0x10000000 0x44>; }; diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index ec8a07415cb3..0640fb75bf59 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -227,8 +227,7 @@ }; pio: pinctrl@10005000 { - compatible = "mediatek,mt7623-pinctrl", - "mediatek,mt2701-pinctrl"; + compatible = "mediatek,mt7623-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; pins-are-numbered; @@ -544,7 +543,9 @@ "mediatek,mt2701-audio"; reg = <0 0x11220000 0 0x2000>, <0 0x112a0000 0 0x20000>; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "afe", "asys"; power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; clocks = <&infracfg CLK_INFRA_AUDIO>, @@ -678,7 +679,7 @@ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>; clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "free_ck"; + clock-names = "sys_ck", "ref_ck"; power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; status = "disabled"; @@ -688,8 +689,6 @@ compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy"; reg = <0 0x1a1c4000 0 0x0700>; - clocks = <&clk26m>; - clock-names = "u3phya_ref"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -697,12 +696,16 @@ u2port0: usb-phy@1a1c4800 { reg = <0 0x1a1c4800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; u3port0: usb-phy@1a1c4900 { reg = <0 0x1a1c4900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; @@ -717,7 +720,7 @@ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "free_ck"; + clock-names = "sys_ck", "ref_ck"; power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; status = "disabled"; @@ -727,8 +730,6 @@ compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy"; reg = <0 0x1a244000 0 0x0700>; - clocks = <&clk26m>; - clock-names = "u3phya_ref"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -736,12 +737,16 @@ u2port1: usb-phy@1a244800 { reg = <0 0x1a244800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; u3port1: usb-phy@1a244900 { reg = <0 0x1a244900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; @@ -782,16 +787,15 @@ }; crypto: crypto@1b240000 { - compatible = "mediatek,mt7623-crypto"; + compatible = "mediatek,eip97-crypto"; reg = <0 0x1b240000 0 0x20000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <ðsys CLK_ETHSYS_CRYPTO>; - clock-names = "ethif","cryp"; + clocks = <ðsys CLK_ETHSYS_CRYPTO>; + clock-names = "cryp"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index ee5a0bb22354..ec2283b1a638 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -20,7 +20,7 @@ }; }; - bootrom: bootrom@00000000 { + bootrom: bootrom@0 { reg = <0x00000000 0x80000>; }; diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi index 1de80c7886ab..1df3ace3af92 100644 --- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi +++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi @@ -7,6 +7,10 @@ reg = <0x80000000 0x8000000>; /* 128 MB */ }; + chosen { + stdout-path = &uart3; + }; + ocp { i2c0 { compatible = "i2c-cbus-gpio"; diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index c963b31ec3b3..5a4ba0aea447 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -9,146 +9,11 @@ #include "omap36xx.dtsi" #include "omap3-evm-common.dtsi" - +#include "omap3-evm-processor-common.dtsi" / { model = "TI OMAP37XX EVM (TMDSEVM3730)"; compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins1 - &dss_dpi_pins2 - >; -}; - -&hsusb2_phy { - pinctrl-names = "default"; - pinctrl-0 = <&ehci_phy_pins>; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; - - dss_dpi_pins1: pinmux_dss_dpi_pins2 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ - OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ - OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ - OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ - >; - }; - - /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ - on_board_gpio_61: pinmux_ehci_port_select_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) - >; - }; - - /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - - /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_cs1.hsusb2_data3 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) - >; - }; - - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ - OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ - >; - }; - - smsc911x_pins: pinmux_smsc911x_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ - >; - }; }; &omap3_pmx_core2 { @@ -191,74 +56,7 @@ }; }; -&omap3_pmx_wkup { - dss_dpi_pins2: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ - OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ - >; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -/* - * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface - * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. - */ -&gpio2 { - en_usb2_port { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ - output-low; - line-name = "enable usb2 port"; - }; -}; - -/* T2_GPIO_2 low to route GPIO_61 to on-board devices */ -&twl_gpio { - en_on_board_gpio_61 { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "en_hsusb2_clk"; - }; -}; - &gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ - <5 0 0x2c000000 0x01000000>; - nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ @@ -309,9 +107,4 @@ reg = <0x780000 0x1f880000>; }; }; - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&smsc911x_pins>; - }; }; diff --git a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi new file mode 100644 index 000000000000..ce7f42f9448c --- /dev/null +++ b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi @@ -0,0 +1,216 @@ +/* + * Common support for omap3 EVM 35xx/37xx processor modules + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + wl12xx_vmmc: wl12xx_vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + }; +}; + +&dss { + vdds_dsi-supply = <&vpll2>; + vdda_video-supply = <&lcd_3v3>; + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins1 + &dss_dpi_pins2 + >; +}; + +&hsusb2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&ehci_phy_pins>; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; + + dss_dpi_pins1: pinmux_dss_dpi_pins2 { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ + OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ + OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ + OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ + >; + }; + + /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ + on_board_gpio_61: pinmux_ehci_port_select_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) + >; + }; + + /* Used by OHCI and EHCI. OHCI won't work without external phy */ + hsusb2_pins: pinmux_hsusb2_pins { + pinctrl-single,pins = < + + /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* mcspi2_cs1.hsusb2_data3 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) + >; + }; + + wl12xx_gpio: pinmux_wl12xx_gpio { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ + OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ + >; + }; + + smsc911x_pins: pinmux_smsc911x_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ + >; + }; +}; + +&omap3_pmx_wkup { + dss_dpi_pins2: pinmux_dss_dpi_pins1 { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ + OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ + OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ + OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ + OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ + >; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; +}; + +&mmc3 { + status = "disabled"; +}; + +&uart1 { + interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +}; + +&uart2 { + interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; +}; + +&uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +/* + * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface + * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. + */ +&gpio2 { + en_usb2_port { + gpio-hog; + gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ + output-low; + line-name = "enable usb2 port"; + }; +}; + +/* T2_GPIO_2 low to route GPIO_61 to on-board devices */ +&twl_gpio { + en_on_board_gpio_61 { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "en_hsusb2_clk"; + }; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ + <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for LAN9220 */ + + ethernet@gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&smsc911x_pins>; + }; +}; diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index 99b2bfcd1059..21a3b88aef0c 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -9,13 +9,81 @@ #include "omap34xx.dtsi" #include "omap3-evm-common.dtsi" +#include "omap3-evm-processor-common.dtsi" / { model = "TI OMAP35XX EVM (TMDSEVM3530)"; - compatible = "ti,omap3-evm", "ti,omap3"; + compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_2_pins>; + + ehci_phy_pins: pinmux_ehci_phy_pins { + pinctrl-single,pins = < + + /* EHCI PHY reset GPIO etk_d7.gpio_21 */ + OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) + + /* EHCI VBUS etk_d8.gpio_22 */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) + >; + }; + + /* Used by OHCI and EHCI. OHCI won't work without external phy */ + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + + /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) + + /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) + + /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) + + /* etk_d15.hsusb2_data1 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) + >; + }; +}; + +&gpmc { + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name= "micron,mt29f2g16abdhc"; + nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ + #address-cells = <1>; + #size-cells = <1>; }; }; diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index fa611a5e4850..343a36d8031d 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi @@ -257,7 +257,7 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; gpiom1: gpio@20 { - compatible = "mcp,mcp23017"; + compatible = "microchip,mcp23017"; gpio-controller; #gpio-cells = <2>; reg = <0x20>; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 4acd32a1c4ef..669c51c00c00 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -791,7 +791,7 @@ }; /* D/A converter for auto-focus */ - ad5820: dac@0c { + ad5820: dac@c { compatible = "adi,ad5820"; reg = <0x0c>; diff --git a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi b/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi index 25e100db7b1a..b8b9fcc41ef1 100644 --- a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi +++ b/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi @@ -30,6 +30,7 @@ compatible = "sharp,ls037v7dw01"; label = "lcd"; power-supply = <&lcd_3v3>; + envdd-supply = <&lcd_3v3>; port { lcd_in: endpoint { diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 2b48e51c372a..22c1eee9b07a 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -13,6 +13,10 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; + chosen { + stdout-path = &uart3; + }; + aliases { display0 = &dvi0; display1 = &hdmi0; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index f69de916b06a..1dc5a76b3c71 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -828,7 +828,7 @@ /* * Child device unsupported by davinci-mcasp. At least - * TX path is disabled for omap4, and only DIT mode + * RX path is disabled for omap4, and only DIT mode * works with no I2S. See also old Android kernel * omap-mcasp driver for more information. */ diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index 7824b2631cb6..575ecffb0e9e 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -14,6 +14,10 @@ display0 = &hdmi0; }; + chosen { + stdout-path = &uart3; + }; + vmain: fixedregulator-vmain { compatible = "regulator-fixed"; regulator-name = "vmain"; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index b86ac7df620d..4cd0005e462f 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -194,7 +194,7 @@ pbias_mmc_reg: pbias_mmc_omap5 { regulator-name = "pbias_mmc_omap5"; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; }; }; }; diff --git a/arch/arm/boot/dts/owl-s500-cubieboard6.dts b/arch/arm/boot/dts/owl-s500-cubieboard6.dts new file mode 100644 index 000000000000..ea4e01bce8d1 --- /dev/null +++ b/arch/arm/boot/dts/owl-s500-cubieboard6.dts @@ -0,0 +1,44 @@ +/* + * Cubietech CubieBoard6 + * + * Copyright (c) 2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "owl-s500.dtsi" + +/ { + compatible = "cubietech,cubieboard6", "actions,s500"; + model = "CubieBoard6"; + + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; + + uart3_clk: uart3-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; +}; + +&timer { + clocks = <&hosc>; +}; + +&uart3 { + status = "okay"; + clocks = <&uart3_clk>; +}; diff --git a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts index 521463d4cac6..7be1d2eaf3f0 100644 --- a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts +++ b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts @@ -19,8 +19,15 @@ chosen { stdout-path = "serial3:115200n8"; }; + + uart3_clk: uart3-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; }; &uart3 { status = "okay"; + clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 51a48741d4c0..43c9980a4260 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -7,6 +7,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/owl-s500-powergate.h> / { compatible = "actions,s500"; @@ -43,6 +44,7 @@ compatible = "arm,cortex-a9"; reg = <0x2>; enable-method = "actions,s500-smp"; + power-domains = <&sps S500_PD_CPU2>; }; cpu3: cpu@3 { @@ -50,6 +52,7 @@ compatible = "arm,cortex-a9"; reg = <0x3>; enable-method = "actions,s500-smp"; + power-domains = <&sps S500_PD_CPU3>; }; }; diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi index 46aa6db8353a..c2b48a1838eb 100644 --- a/arch/arm/boot/dts/ox810se.dtsi +++ b/arch/arm/boot/dts/ox810se.dtsi @@ -207,7 +207,7 @@ }; }; - gpio0: gpio@000000 { + gpio0: gpio@0 { compatible = "oxsemi,ox810se-gpio"; reg = <0x000000 0x100000>; interrupts = <21>; @@ -296,7 +296,7 @@ compatible = "simple-bus"; ranges = <0 0x45000000 0x1000000>; - sys: sys-ctrl@000000 { + sys: sys-ctrl@0 { compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; reg = <0x000000 0x100000>; diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi index 459207536a46..085bbd33eadc 100644 --- a/arch/arm/boot/dts/ox820.dtsi +++ b/arch/arm/boot/dts/ox820.dtsi @@ -173,7 +173,7 @@ }; }; - gpio0: gpio@000000 { + gpio0: gpio@0 { compatible = "oxsemi,ox820-gpio"; reg = <0x000000 0x100000>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi index 533919e96eae..a1266cf8776c 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi @@ -124,7 +124,7 @@ #size-cells = <1>; ranges = <0 0x200000 0x80000>; - rtc0: rtc@00000 { + rtc0: rtc@0 { compatible = "picochip,pc3x2-rtc"; clock-freq = <200000000>; reg = <0x00000 0xf>; diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi index ab3e80085511..d78cd207eca1 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi @@ -223,7 +223,7 @@ #size-cells = <1>; ranges = <0 0x200000 0x80000>; - rtc0: rtc@00000 { + rtc0: rtc@0 { compatible = "picochip,pc3x2-rtc"; clock-freq = <200000000>; reg = <0x00000 0xf>; diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts index 3139221737ee..be5177221cbb 100644 --- a/arch/arm/boot/dts/pm9g45.dts +++ b/arch/arm/boot/dts/pm9g45.dts @@ -127,12 +127,12 @@ }; }; - usb0: ohci@00700000 { + usb0: ohci@700000 { status = "okay"; num-ports = <2>; }; - usb1: ehci@00800000 { + usb1: ehci@800000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 9d725f983282..497bb065eb9d 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -397,23 +397,23 @@ xoadc-ref-supply = <&pm8058_l18>; /* Board-specific channels */ - mpp5@05 { + mpp5@5 { /* Connected to AOUT of ALS sensor */ reg = <0x00 0x05>; }; - mpp6@06 { + mpp6@6 { /* Connected to test point TP43 */ reg = <0x00 0x06>; }; - mpp7@07 { + mpp7@7 { /* Connected to battery thermistor */ reg = <0x00 0x07>; }; - mpp8@08 { + mpp8@8 { /* Connected to battery ID detector */ reg = <0x00 0x08>; }; - mpp9@09 { + mpp9@9 { /* Connected to XO thermistor */ reg = <0x00 0x09>; }; @@ -512,7 +512,7 @@ pinctrl-names = "default"; pinctrl-0 = <&dragon_gsbi12_i2c_pins>; - ak8975@0c { + ak8975@c { compatible = "asahi-kasei,ak8975"; reg = <0x0c>; /* FIXME: GPIO33 has interrupt 224 on the PM8058 */ diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 6089c8d56cd5..3ca96e361878 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -591,6 +591,7 @@ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; + status = "disabled"; }; }; @@ -907,11 +908,11 @@ usb_hs1_phy: phy { compatible = "qcom,usb-hs-phy-apq8064", "qcom,usb-hs-phy"; - #phy-cells = <0>; clocks = <&sleep_clk>, <&cxo_board>; clock-names = "sleep", "ref"; resets = <&usb1 0>; reset-names = "por"; + #phy-cells = <0>; }; }; }; @@ -1264,6 +1265,7 @@ dsi0_phy: dsi-phy@4700200 { compatible = "qcom,dsi-phy-28nm-8960"; #clock-cells = <1>; + #phy-cells = <0>; reg = <0x04700200 0x100>, <0x04700300 0x200>, @@ -1418,6 +1420,7 @@ clocks = <&mmcc HDMI_S_AHB_CLK>; clock-names = "slave_iface_clk"; + #phy-cells = <0>; }; mdp: mdp@5100000 { diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 221c4584552f..33030f9419fe 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -124,6 +124,73 @@ reg = <0x900000 0x4000>; }; + gsbi6: gsbi@16500000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16500000 0x100>; + clocks = <&gcc GSBI6_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi6_serial: serial@16540000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16540000 0x1000>, + <0x16500000 0x1000>; + interrupts = <GIC_SPI 156 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi6_i2c: i2c@16580000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16580000 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gsbi7: gsbi@16600000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16600000 0x100>; + clocks = <&gcc GSBI7_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi7_serial: serial@16640000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16640000 0x1000>, + <0x16600000 0x1000>; + interrupts = <GIC_SPI 158 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16680000 0x1000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; gsbi8: gsbi@19800000 { compatible = "qcom,gsbi-v1.0.0"; @@ -317,37 +384,37 @@ #size-cells = <0>; #io-channel-cells = <2>; - vcoin: adc-channel@00 { + vcoin: adc-channel@0 { reg = <0x00 0x00>; }; - vbat: adc-channel@01 { + vbat: adc-channel@1 { reg = <0x00 0x01>; }; - dcin: adc-channel@02 { + dcin: adc-channel@2 { reg = <0x00 0x02>; }; - ichg: adc-channel@03 { + ichg: adc-channel@3 { reg = <0x00 0x03>; }; - vph_pwr: adc-channel@04 { + vph_pwr: adc-channel@4 { reg = <0x00 0x04>; }; - usb_vbus: adc-channel@0a { + usb_vbus: adc-channel@a { reg = <0x00 0x0a>; }; - die_temp: adc-channel@0b { + die_temp: adc-channel@b { reg = <0x00 0x0b>; }; - ref_625mv: adc-channel@0c { + ref_625mv: adc-channel@c { reg = <0x00 0x0c>; }; - ref_1250mv: adc-channel@0d { + ref_1250mv: adc-channel@d { reg = <0x00 0x0d>; }; - ref_325mv: adc-channel@0e { + ref_325mv: adc-channel@e { reg = <0x00 0x0e>; }; - ref_muxoff: adc-channel@0f { + ref_muxoff: adc-channel@f { reg = <0x00 0x0f>; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts new file mode 100644 index 000000000000..d0a5df90b543 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -0,0 +1,321 @@ +#include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + + +/ { + model = "Fairphone 2"; + compatible = "fairphone,fp2", "qcom,msm8974"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_CAMERA>; + wakeup-source; + debounce-interval = <15>; + }; + + volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + wakeup-source; + debounce-interval = <15>; + }; + + volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + wakeup-source; + debounce-interval = <15>; + }; + }; + + smd { + rpm { + rpm_requests { + pm8841-regulators { + s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + }; + + pm8941-regulators { + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + + regulator-always-on; + regulator-boot-on; + }; + + s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + + regulator-boot-on; + }; + + s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + + regulator-always-on; + regulator-boot-on; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l11 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1350000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + }; + + l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3350000>; + }; + + l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + + regulator-boot-on; + }; + }; + }; + }; + }; +}; + +&soc { + serial@f991e000 { + status = "ok"; + }; + + pinctrl@fd510000 { + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + }; + + sdhci@f9824900 { + status = "ok"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + bus-width = <8>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; + }; + + usb@f9a55000 { + status = "ok"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "ok"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; + }; +}; + +&spmi_bus { + pm8941@0 { + gpios@c000 { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio1", "gpio2", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = <PM8941_GPIO_S3>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts new file mode 100644 index 000000000000..e87f2c99060d --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts @@ -0,0 +1,641 @@ +#include "qcom-msm8974pro.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +/ { + model = "Sony Xperia Z2 Tablet"; + compatible = "sony,xperia-castor", "qcom,msm8974"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_CAMERA>; + }; + + camera-focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_CAMERA_FOCUS>; + }; + + volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + smd { + rpm { + rpm_requests { + pm8941-regulators { + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-system-load = <154000>; + }; + + s4 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + + regulator-always-on; + regulator-boot-on; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + }; + + l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-allow-set-load; + regulator-boot-on; + regulator-allow-set-load; + regulator-system-load = <500000>; + }; + + l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + + regulator-boot-on; + }; + }; + }; + }; + }; + + vreg_bl_vddio: lcd-backlight-vddio { + compatible = "regulator-fixed"; + regulator-name = "vreg_bl_vddio"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + + gpio = <&msmgpio 69 0>; + enable-active-high; + + vin-supply = <&pm8941_s3>; + startup-delay-us = <70000>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_backlight_en_pin_a>; + }; + + vreg_vsp: lcd-dcdc-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_vsp"; + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; + + gpio = <&pm8941_gpios 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_dcdc_en_pin_a>; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8941_gpios 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_pin>; + }; +}; + +&soc { + sdhci@f9824900 { + status = "ok"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + bus-width = <8>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; + }; + + sdhci@f9864900 { + status = "ok"; + + max-frequency = <100000000>; + non-removable; + vmmc-supply = <&vreg_wlan>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc3_pin_a>; + + #address-cells = <1>; + #size-cells = <0>; + + bcrmf@1 { + compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + brcm,drive-strength = <10>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin>; + }; + }; + + sdhci@f98a4900 { + status = "ok"; + + bus-width = <4>; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; + }; + + serial@f991e000 { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart2_pin_a>; + }; + + usb@f9a55000 { + status = "ok"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "ok"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; + }; + + pinctrl@fd510000 { + blsp1_uart2_pin_a: blsp1-uart2-pin-active { + rx { + pins = "gpio5"; + function = "blsp_uart2"; + + drive-strength = <2>; + bias-pull-up; + }; + + tx { + pins = "gpio4"; + function = "blsp_uart2"; + + drive-strength = <4>; + bias-disable; + }; + }; + + i2c8_pins: i2c8 { + mux { + pins = "gpio47", "gpio48"; + function = "blsp_i2c8"; + + drive-strength = <2>; + bias-disable; + }; + }; + + i2c11_pins: i2c11 { + mux { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + + drive-strength = <2>; + bias-disable; + }; + }; + + lcd_backlight_en_pin_a: lcd-backlight-vddio { + pins = "gpio69"; + drive-strength = <10>; + output-low; + bias-disable; + }; + + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc2_cd_pin_a: sdhc2-cd-pin-active { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdhc2_pin_a: sdhc2-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + sdhc3_pin_a: sdhc3-pin-active { + clk { + pins = "gpio40"; + function = "sdc3"; + + drive-strength = <10>; + bias-disable; + }; + + cmd { + pins = "gpio39"; + function = "sdc3"; + + drive-strength = <10>; + bias-pull-up; + }; + + data { + pins = "gpio35", "gpio36", "gpio37", "gpio38"; + function = "sdc3"; + + drive-strength = <10>; + bias-pull-up; + }; + }; + + ts_int_pin: synaptics { + pin { + pins = "gpio86"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + }; + + i2c@f9964000 { + status = "ok"; + + clock-frequency = <355000>; + qcom,src-freq = <50000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_pins>; + + synaptics@2c { + compatible = "syna,rmi-i2c"; + reg = <0x2c>; + + interrupt-parent = <&msmgpio>; + interrupts = <86 IRQ_TYPE_EDGE_FALLING>; + + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_pin>; + + rmi-f01@1 { + reg = <0x1>; + syna,nosleep = <1>; + }; + + rmi-f11@11 { + reg = <0x11>; + syna,f11-flip-x = <1>; + syna,sensor-type = <1>; + }; + }; + }; + + i2c@f9967000 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c11_pins>; + clock-frequency = <355000>; + qcom,src-freq = <50000000>; + + lp8566_wled: backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + power-supply = <&vreg_bl_vddio>; + + bl-name = "backlight"; + dev-ctrl = /bits/ 8 <0x05>; + init-brt = /bits/ 8 <0x3f>; + rom_a0h { + rom-addr = /bits/ 8 <0xa0>; + rom-val = /bits/ 8 <0xff>; + }; + rom_a1h { + rom-addr = /bits/ 8 <0xa1>; + rom-val = /bits/ 8 <0x3f>; + }; + rom_a2h { + rom-addr = /bits/ 8 <0xa2>; + rom-val = /bits/ 8 <0x20>; + }; + rom_a3h { + rom-addr = /bits/ 8 <0xa3>; + rom-val = /bits/ 8 <0x5e>; + }; + rom_a4h { + rom-addr = /bits/ 8 <0xa4>; + rom-val = /bits/ 8 <0x02>; + }; + rom_a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x04>; + }; + rom_a6h { + rom-addr = /bits/ 8 <0xa6>; + rom-val = /bits/ 8 <0x80>; + }; + rom_a7h { + rom-addr = /bits/ 8 <0xa7>; + rom-val = /bits/ 8 <0xf7>; + }; + rom_a9h { + rom-addr = /bits/ 8 <0xa9>; + rom-val = /bits/ 8 <0x80>; + }; + rom_aah { + rom-addr = /bits/ 8 <0xaa>; + rom-val = /bits/ 8 <0x0f>; + }; + rom_aeh { + rom-addr = /bits/ 8 <0xae>; + rom-val = /bits/ 8 <0x0f>; + }; + }; + }; +}; + +&spmi_bus { + pm8941@0 { + charger@1000 { + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <1500000>; + qcom,dc-current-limit = <1800000>; + qcom,fast-charge-safe-voltage = <4400000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,fast-charge-low-threshold-voltage = <3400000>; + qcom,auto-recharge-threshold-voltage = <4200000>; + qcom,minimum-input-voltage = <4300000>; + }; + + gpios@c000 { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio2", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = <PM8941_GPIO_S3>; + }; + + wlan_sleep_clk_pin: wl-sleep-clk { + pins = "gpio17"; + function = "func2"; + + output-high; + power-source = <PM8941_GPIO_S3>; + }; + + wlan_regulator_pin: wl-reg-active { + pins = "gpio18"; + function = "normal"; + + bias-disable; + power-source = <PM8941_GPIO_S3>; + }; + + lcd_dcdc_en_pin_a: lcd-dcdc-en-active { + pins = "gpio20"; + function = "normal"; + + bias-disable; + power-source = <PM8941_GPIO_S3>; + input-disable; + output-low; + }; + + }; + + coincell@2800 { + status = "ok"; + qcom,rset-ohms = <2100>; + qcom,vset-millivolts = <3000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 33002fed8cc3..d9019a49b292 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -18,27 +18,27 @@ #size-cells = <1>; ranges; - mpss@08000000 { + mpss@8000000 { reg = <0x08000000 0x5100000>; no-map; }; - mba@00d100000 { + mba@d100000 { reg = <0x0d100000 0x100000>; no-map; }; - reserved@0d200000 { + reserved@d200000 { reg = <0x0d200000 0xa00000>; no-map; }; - adsp_region: adsp@0dc00000 { + adsp_region: adsp@dc00000 { reg = <0x0dc00000 0x1900000>; no-map; }; - venus@0f500000 { + venus@f500000 { reg = <0x0f500000 0x500000>; no-map; }; @@ -48,17 +48,17 @@ no-map; }; - tz@0fc00000 { + tz@fc00000 { reg = <0x0fc00000 0x160000>; no-map; }; - rfsa@0fd60000 { + rfsa@fd60000 { reg = <0x0fd60000 0x20000>; no-map; }; - rmtfs@0fd80000 { + rmtfs@fd80000 { reg = <0x0fd80000 0x180000>; no-map; }; @@ -614,6 +614,20 @@ status = "disabled"; }; + sdhci@f9864900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>, + <GIC_SPI 224 IRQ_TYPE_NONE>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC3_APPS_CLK>, + <&gcc GCC_SDCC3_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + status = "disabled"; + }; + sdhci@f98a4900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qcom-msm8974pro.dtsi new file mode 100644 index 000000000000..6740a4cb7da8 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974pro.dtsi @@ -0,0 +1,18 @@ +#include "qcom-msm8974.dtsi" + +/ { + soc { + sdhci@f9824900 { + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>, + <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, + <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; + clock-names = "core", "iface", "xo", "cal", "sleep"; + }; + + clock-controller@fc400000 { + compatible = "qcom,gcc-msm8974pro"; + }; + }; +}; diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts index a1b2aef984f6..779f724b4531 100644 --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts @@ -11,6 +11,8 @@ /dts-v1/; #include "r7s72100.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/r7s72100-pinctrl.h> / { model = "GR-Peach"; @@ -28,7 +30,6 @@ memory@20000000 { device_type = "memory"; reg = <0x20000000 0x00a00000>; - }; lbsc { @@ -51,6 +52,44 @@ reg = <0x00600000 0x00200000>; }; }; + + leds { + status = "okay"; + compatible = "gpio-leds"; + + led1 { + gpios = <&port6 12 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + scif2_pins: serial2 { + /* P6_2 as RxD2; P6_3 as TxD2 */ + pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>; + }; + + ether_pins: ether { + /* Ethernet on Ports 1,3,5,10 */ + pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */ + <RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */ + <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */ + <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */ + <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */ + <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */ + <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */ + <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */ + <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */ + <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */ + <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */ + <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */ + <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */ + <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */ + <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */ + <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */ + <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */ + <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */ + }; }; &extal_clk { @@ -61,6 +100,38 @@ clock-frequency = <48000000>; }; +&mtu2 { + status = "okay"; +}; + +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + &scif2 { + pinctrl-names = "default"; + pinctrl-0 = <&scif2_pins>; + + status = "okay"; +}; + +ðer { + pinctrl-names = "default"; + pinctrl-0 = <ðer_pins>; + status = "okay"; + + renesas,no-ether-link; + phy-handle = <&phy0>; + + phy0: ethernet-phy@0 { + reg = <0>; + + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <5>; + }; }; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 4ed12a4d9d51..ab9645a42eca 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -203,6 +203,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <400000000>; + clocks = <&cpg_clocks R7S72100_CLK_I>; next-level-cache = <&L2>; }; }; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 310222634570..dd4d09712a2a 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -27,6 +27,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + clocks = <&cpg_clocks R8A73A4_CLK_Z>; clock-frequency = <1500000000>; power-domains = <&pd_a2sl>; next-level-cache = <&L2_CA15>; diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts new file mode 100644 index 000000000000..d90eb8464222 --- /dev/null +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts @@ -0,0 +1,19 @@ +/* + * Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7743-iwg20m.dtsi" +#include "iwg20d-q7-common.dtsi" +#include "iwg20d-q7-dbcm-ca.dtsi" + +/ { + model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board"; + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; +}; diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts index 081af0192851..6aa6b7467704 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -1,5 +1,5 @@ /* - * Device Tree Source for the iWave-RZG1M Qseven carrier board + * Device Tree Source for the iWave-RZ/G1M Qseven board * * Copyright (C) 2017 Renesas Electronics Corp. * @@ -10,47 +10,9 @@ /dts-v1/; #include "r8a7743-iwg20m.dtsi" +#include "iwg20d-q7-common.dtsi" / { model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M"; compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; - - aliases { - serial0 = &scif0; - ethernet0 = &avb; - }; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - avb_pins: avb { - groups = "avb_mdio", "avb_gmii"; - function = "avb"; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy3>; - phy-mode = "gmii"; - renesas,no-ether-link; - status = "okay"; - - phy3: ethernet-phy@3 { - reg = <3>; - micrel,led-mode = <1>; - }; }; diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi index ff7993818637..75a8ca571846 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi @@ -9,6 +9,7 @@ */ #include "r8a7743.dtsi" +#include <dt-bindings/gpio/gpio.h> / { compatible = "iwave,g20m", "renesas,r8a7743"; @@ -42,6 +43,17 @@ groups = "mmc_data8_b", "mmc_ctrl"; function = "mmc"; }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; }; &mmcif0 { @@ -53,3 +65,34 @@ non-removable; status = "okay"; }; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* WARNING - This device contains the bootloader. Handle with care. */ + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + m25p,fast-read; + spi-cpol; + spi-cpha; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 14222c72f0e0..7bbba4a36f31 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -25,6 +25,13 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + i2c6 = &iic0; + i2c7 = &iic1; + i2c8 = &iic3; + spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + spi3 = &msiof2; }; cpus { @@ -56,6 +63,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; power-domains = <&sysc R8A7743_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; @@ -101,7 +109,7 @@ gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -116,7 +124,7 @@ gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -131,7 +139,7 @@ gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -146,7 +154,7 @@ gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -161,7 +169,7 @@ gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -176,7 +184,7 @@ gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -191,7 +199,7 @@ gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -206,7 +214,7 @@ gpio7: gpio@e6055800 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -348,6 +356,34 @@ dma-channels = <15>; }; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7743-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7743-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + /* The memory map in the User's Manual maps the cores to bus * numbers */ @@ -436,6 +472,58 @@ status = "disabled"; }; + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7743", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7743", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; + + iic3: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7743", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7743", "renesas,rcar-gen2-scifa", "renesas,scifa"; @@ -779,6 +867,241 @@ max-frequency = <97500000>; status = "disabled"; }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7743", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 917>; + status = "disabled"; + }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7743", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 000>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7743", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 208>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7743", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 205>; + status = "disabled"; + }; + + /* + * pci1 and xhci share the same phy, therefore only one of them + * can be active at any one time. If both of them are enabled, + * a race condition will determine who'll control the phy. + * A firmware file is needed by the xhci driver in order for + * USB 3.0 to work properly. + */ + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7743", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7743"; + reg = <0 0xee100000 0 0x328>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7743"; + reg = <0 0xee140000 0 0x100>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7743"; + reg = <0 0xee160000 0 0x100>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7743", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7743", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7743", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7743", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; }; /* External root clock */ diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts new file mode 100644 index 000000000000..52153ec3638c --- /dev/null +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -0,0 +1,109 @@ +/* + * Device Tree Source for the iWave-RZG1E SODIMM carrier board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7745-iwg22m.dtsi" + +/ { + model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E"; + compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; + + aliases { + serial0 = &scif4; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&pfc { + scif4_pins: scif4 { + groups = "scif4_data_b"; + function = "scif4"; + }; + + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; +}; + +&scif4 { + pinctrl-0 = <&scif4_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + /* + * On some older versions of the platform (before R4.0) the phy address + * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. + */ + reg = <3>; + micrel,led-mode = <1>; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi new file mode 100644 index 000000000000..ed9a8cf3fe36 --- /dev/null +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi @@ -0,0 +1,111 @@ +/* + * Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include "r8a7745.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "iwave,g22m", "renesas,r8a7745"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x20000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + mmcif0_pins: mmc { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + i2c3_pins: i2c3 { + groups = "i2c3_b"; + function = "i2c3"; + }; +}; + +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* WARNING - This device contains the bootloader. Handle with care. */ + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + m25p,fast-read; + spi-cpol; + spi-cpha; + }; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + }; +}; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index aff90dfb8b32..3a50f703601c 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -18,6 +18,19 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + spi3 = &msiof2; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -65,6 +78,111 @@ resets = <&cpg 408>; }; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + irqc: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a7745", "renesas,irqc"; #interrupt-cells = <2>; @@ -508,6 +626,317 @@ #size-cells = <0>; status = "disabled"; }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7745", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7745", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + max-frequency = <97500000>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7745", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 917>; + status = "disabled"; + }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 000>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 208>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 205>; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7745"; + reg = <0 0xee100000 0 0x328>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7745"; + reg = <0 0xee140000 0 0x100>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7745"; + reg = <0 0xee160000 0 0x100>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7745", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7745", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7745", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; }; /* External root clock */ diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 8f3156c0e575..a39472aab867 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -33,6 +33,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <800000000>; + clocks = <&z_clk>; }; }; @@ -88,7 +89,7 @@ }; gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc40000 0x2c>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -99,7 +100,7 @@ }; gpio1: gpio@ffc41000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc41000 0x2c>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -110,7 +111,7 @@ }; gpio2: gpio@ffc42000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc42000 0x2c>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -121,7 +122,7 @@ }; gpio3: gpio@ffc43000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc43000 0x2c>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -132,7 +133,7 @@ }; gpio4: gpio@ffc44000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc44000 0x2c>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 8ee0b2ca5d39..e8eb94748b27 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -29,12 +29,14 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; power-domains = <&sysc R8A7779_PD_ARM1>; }; cpu@2 { @@ -42,6 +44,7 @@ compatible = "arm,cortex-a9"; reg = <2>; clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; power-domains = <&sysc R8A7779_PD_ARM2>; }; cpu@3 { @@ -49,6 +52,7 @@ compatible = "arm,cortex-a9"; reg = <3>; clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; power-domains = <&sysc R8A7779_PD_ARM3>; }; }; @@ -76,7 +80,7 @@ }; gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc40000 0x2c>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -87,7 +91,7 @@ }; gpio1: gpio@ffc41000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc41000 0x2c>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -98,7 +102,7 @@ }; gpio2: gpio@ffc42000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc42000 0x2c>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -109,7 +113,7 @@ }; gpio3: gpio@ffc43000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc43000 0x2c>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -120,7 +124,7 @@ }; gpio4: gpio@ffc44000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc44000 0x2c>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -131,7 +135,7 @@ }; gpio5: gpio@ffc45000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc45000 0x2c>; interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -142,7 +146,7 @@ }; gpio6: gpio@ffc46000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc46000 0x2c>; interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index ba100a6f67ca..e3d27783b6b5 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -316,11 +316,8 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7790_CLK_DU0>, - <&mstp7_clks R8A7790_CLK_DU1>, - <&mstp7_clks R8A7790_CLK_DU2>, - <&mstp7_clks R8A7790_CLK_LVDS0>, - <&mstp7_clks R8A7790_CLK_LVDS1>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 16358bf8d1db..2f017fee4009 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -10,7 +10,7 @@ * kind, whether express or implied. */ -#include <dt-bindings/clock/r8a7790-clock.h> +#include <dt-bindings/clock/r8a7790-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/r8a7790-sysc.h> @@ -52,10 +52,11 @@ reg = <0>; clock-frequency = <1300000000>; voltage-tolerance = <1>; /* 1% */ - clocks = <&cpg_clocks R8A7790_CLK_Z>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7790_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, @@ -71,8 +72,10 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu2: cpu@2 { @@ -80,8 +83,10 @@ compatible = "arm,cortex-a15"; reg = <2>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu3: cpu@3 { @@ -89,8 +94,10 @@ compatible = "arm,cortex-a15"; reg = <3>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu4: cpu@100 { @@ -98,8 +105,10 @@ compatible = "arm,cortex-a7"; reg = <0x100>; clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu5: cpu@101 { @@ -107,8 +116,10 @@ compatible = "arm,cortex-a7"; reg = <0x101>; clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu6: cpu@102 { @@ -116,8 +127,10 @@ compatible = "arm,cortex-a7"; reg = <0x102>; clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU2>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu7: cpu@103 { @@ -125,8 +138,10 @@ compatible = "arm,cortex-a7"; reg = <0x103>; clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU3>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; L2_CA15: cache-controller-0 { @@ -185,13 +200,14 @@ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&mstp4_clks R8A7790_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -199,12 +215,13 @@ gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -212,12 +229,13 @@ gpio-ranges = <&pfc 0 32 30>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -225,12 +243,13 @@ gpio-ranges = <&pfc 0 64 30>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -238,12 +257,13 @@ gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -251,12 +271,13 @@ gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -264,8 +285,9 @@ gpio-ranges = <&pfc 0 160 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; thermal: thermal@e61f0000 { @@ -274,8 +296,9 @@ "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; + clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 522>; #thermal-sensor-cells = <0>; }; @@ -292,9 +315,10 @@ reg = <0 0xffca0000 0 0x1004>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_CMT0>; + clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 124>; renesas,channels-mask = <0x60>; @@ -312,9 +336,10 @@ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_CMT1>; + clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 329>; renesas,channels-mask = <0xff>; @@ -330,8 +355,9 @@ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp4_clks R8A7790_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; dmac0: dma-controller@e6700000 { @@ -358,9 +384,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -389,9 +416,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -418,9 +446,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>; + clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <13>; }; @@ -447,9 +476,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>; + clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <13>; }; @@ -460,8 +490,9 @@ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; + clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 330>; #dma-cells = <1>; dma-channels = <2>; }; @@ -472,8 +503,9 @@ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; + clocks = <&cpg CPG_MOD 331>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 331>; #dma-cells = <1>; dma-channels = <2>; }; @@ -484,8 +516,9 @@ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 931>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -496,8 +529,9 @@ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 930>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -508,8 +542,9 @@ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 929>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -520,8 +555,9 @@ compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 928>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -533,11 +569,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_IIC0>; + clocks = <&cpg CPG_MOD 318>; dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 318>; status = "disabled"; }; @@ -548,11 +585,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x425>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_IIC1>; + clocks = <&cpg CPG_MOD 323>; dmas = <&dmac0 0x65>, <&dmac0 0x66>, <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 323>; status = "disabled"; }; @@ -563,11 +601,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6520000 0 0x425>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_IIC2>; + clocks = <&cpg CPG_MOD 300>; dmas = <&dmac0 0x69>, <&dmac0 0x6a>, <&dmac1 0x69>, <&dmac1 0x6a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 300>; status = "disabled"; }; @@ -578,11 +617,12 @@ "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x425>; interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; + clocks = <&cpg CPG_MOD 926>; dmas = <&dmac0 0x77>, <&dmac0 0x78>, <&dmac1 0x77>, <&dmac1 0x78>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 926>; status = "disabled"; }; @@ -590,11 +630,12 @@ compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; + clocks = <&cpg CPG_MOD 315>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 315>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -604,11 +645,12 @@ compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; + clocks = <&cpg CPG_MOD 305>; dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, <&dmac1 0xe1>, <&dmac1 0xe2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 305>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -623,12 +665,13 @@ compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee100000 0 0x328>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; @@ -636,12 +679,13 @@ compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee120000 0 0x328>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; + clocks = <&cpg CPG_MOD 313>; dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 313>; status = "disabled"; }; @@ -649,12 +693,13 @@ compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee140000 0 0x100>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; + clocks = <&cpg CPG_MOD 312>; dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 312>; status = "disabled"; }; @@ -662,12 +707,13 @@ compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee160000 0 0x100>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; + clocks = <&cpg CPG_MOD 311>; dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 311>; status = "disabled"; }; @@ -676,12 +722,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; + clocks = <&cpg CPG_MOD 204>; clock-names = "fck"; dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -690,12 +737,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; + clocks = <&cpg CPG_MOD 203>; clock-names = "fck"; dmas = <&dmac0 0x25>, <&dmac0 0x26>, <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -704,12 +752,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; + clocks = <&cpg CPG_MOD 202>; clock-names = "fck"; dmas = <&dmac0 0x27>, <&dmac0 0x28>, <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -718,12 +767,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; + clocks = <&cpg CPG_MOD 206>; clock-names = "fck"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -732,12 +782,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; + clocks = <&cpg CPG_MOD 207>; clock-names = "fck"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>, <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -746,12 +797,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; + clocks = <&cpg CPG_MOD 216>; clock-names = "fck"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -760,13 +812,14 @@ "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -775,13 +828,14 @@ "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -790,13 +844,14 @@ "renesas,scif"; reg = <0 0xe6e56000 0 64>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 310>; status = "disabled"; }; @@ -805,13 +860,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -820,13 +876,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -852,8 +909,9 @@ compatible = "renesas,ether-r8a7790"; reg = <0 0xee700000 0 0x400>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_ETHER>; + clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -865,8 +923,9 @@ "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -876,8 +935,9 @@ compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; reg = <0 0xee300000 0 0x2000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_SATA0>; + clocks = <&cpg CPG_MOD 815>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 815>; status = "disabled"; }; @@ -885,8 +945,9 @@ compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; reg = <0 0xee500000 0 0x2000>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_SATA1>; + clocks = <&cpg CPG_MOD 814>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 814>; status = "disabled"; }; @@ -894,11 +955,12 @@ compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs"; reg = <0 0xe6590000 0 0x100>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 704>; renesas,buswait = <4>; phys = <&usb0 1>; phy-names = "usb"; @@ -911,9 +973,10 @@ reg = <0 0xe6590100 0 0x100>; #address-cells = <1>; #size-cells = <0>; - clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; clock-names = "usbhs"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 704>; status = "disabled"; usb0: usb-channel@0 { @@ -930,8 +993,9 @@ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -939,8 +1003,9 @@ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -948,8 +1013,9 @@ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_VIN2>; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 809>; status = "disabled"; }; @@ -957,41 +1023,46 @@ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef3000 0 0x1000>; interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_VIN3>; + clocks = <&cpg CPG_MOD 808>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 808>; status = "disabled"; }; - vsp1@fe920000 { + vsp@fe920000 { compatible = "renesas,vsp1"; reg = <0 0xfe920000 0 0x8000>; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; + clocks = <&cpg CPG_MOD 130>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 130>; }; - vsp1@fe928000 { + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; + clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 131>; }; - vsp1@fe930000 { + vsp@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; + clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; - vsp1@fe938000 { + vsp@fe938000 { compatible = "renesas,vsp1"; reg = <0 0xfe938000 0 0x8000>; interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; + clocks = <&cpg CPG_MOD 127>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 127>; }; du: display@feb00000 { @@ -1003,11 +1074,9 @@ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_DU0>, - <&mstp7_clks R8A7790_CLK_DU1>, - <&mstp7_clks R8A7790_CLK_DU2>, - <&mstp7_clks R8A7790_CLK_LVDS0>, - <&mstp7_clks R8A7790_CLK_LVDS1>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>, + <&cpg CPG_MOD 725>; clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; status = "disabled"; @@ -1037,10 +1106,11 @@ compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, - <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7790_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -1048,10 +1118,11 @@ compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, - <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7790_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; @@ -1059,443 +1130,77 @@ compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu"; reg = <0 0xfe980000 0 0x10300>; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_JPU>; + clocks = <&cpg CPG_MOD 106>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 106>; }; - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency clocks by - * default. Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7790-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "sd1", - "z", "rcan", "adsp"; - #power-domain-cells = <0>; - }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc1_clk: mmc1@e6150244 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150244 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssp_clk: ssp@e6150248 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150248 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssprs_clk: ssprs@e615024c { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615024c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - z2_clk: z2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - b_clk: b { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cl_clk: cl { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - imp_clk: imp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - oscclk_clk: oscclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(12 * 1024)>; - clock-mult = <1>; - }; - zb3_clk: zb3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - zb3d2_clk: zb3d2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - ddr_clk: ddr { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = <R8A7790_CLK_MSIOF0>; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>, - <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>, - <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, - <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 - R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 - R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC - R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0 - R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 - R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0 - R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S - >; - clock-output-names = - "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1", - "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1", - "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0", - "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 - R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 - R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 - R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "msiof3", "scifb2", - "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>, - <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3 - R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 - R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 - R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1 - >; - clock-output-names = - "iic2", "tpu0", "mmcif1", "scif2", "sdhi3", - "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "iic0", "pciec", "iic1", "ssusb", "cmt1", - "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = <R8A7790_CLK_IRQC R8A7790_CLK_INTC_SYS>; - clock-output-names = "irqc", "intc-sys"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>, - <&extal_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 - R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL - R8A7790_CLK_PWM - >; - clock-output-names = "audmac0", "audmac1", "adsp_mod", - "thermal", "pwm"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, - <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 - R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 - R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 - R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 - >; - clock-output-names = - "ehci", "hsusb", "hscif1", "hscif0", "scif1", - "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 - R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 - R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER - R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 - >; - clock-output-names = - "mlb", "vin3", "vin2", "vin1", "vin0", - "etheravb", "ether", "sata1", "sata0"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, - <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 - R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 - R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS - R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 - >; - clock-output-names = - "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", - "rcan1", "rcan0", "qspi_mod", "iic3", - "i2c3", "i2c2", "i2c1", "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&p_clk>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>; - - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_SSI_ALL - R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5 - R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 - R8A7790_CLK_SCU_ALL - R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0 - R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0 - R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5 - R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0 - >; - clock-output-names = - "ssi-all", - "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", - "scu-all", - "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", - "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7790-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; }; prr: chipid@ff000044 { @@ -1518,11 +1223,12 @@ compatible = "renesas,qspi-r8a7790", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1534,11 +1240,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e20000 0 0x0064>; interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; + clocks = <&cpg CPG_MOD 0>; dmas = <&dmac0 0x51>, <&dmac0 0x52>, <&dmac1 0x51>, <&dmac1 0x52>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1549,11 +1256,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e10000 0 0x0064>; interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; + clocks = <&cpg CPG_MOD 208>; dmas = <&dmac0 0x55>, <&dmac0 0x56>, <&dmac1 0x55>, <&dmac1 0x56>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 208>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1564,11 +1272,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e00000 0 0x0064>; interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; + clocks = <&cpg CPG_MOD 205>; dmas = <&dmac0 0x41>, <&dmac0 0x42>, <&dmac1 0x41>, <&dmac1 0x42>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 205>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1579,11 +1288,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6c90000 0 0x0064>; interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; + clocks = <&cpg CPG_MOD 215>; dmas = <&dmac0 0x45>, <&dmac0 0x46>, <&dmac1 0x45>, <&dmac1 0x46>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 215>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1593,8 +1303,9 @@ compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci"; reg = <0 0xee000000 0 0xc00>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; + clocks = <&cpg CPG_MOD 328>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 328>; phys = <&usb2 1>; phy-names = "usb"; status = "disabled"; @@ -1606,8 +1317,9 @@ reg = <0 0xee090000 0 0xc00>, <0 0xee080000 0 0x1100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <0 0>; @@ -1639,8 +1351,9 @@ reg = <0 0xee0b0000 0 0xc00>, <0 0xee0a0000 0 0x1100>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <1 1>; @@ -1657,8 +1370,9 @@ pci2: pci@ee0d0000 { compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; device_type = "pci"; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; reg = <0 0xee0d0000 0 0xc00>, <0 0xee0c0000 0 0x1100>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; @@ -1707,9 +1421,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 319>; status = "disabled"; }; @@ -1728,21 +1443,22 @@ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, - <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>, - <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>, - <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>, - <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>, - <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>, - <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>, - <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, - <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, - <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, - <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7790_CLK_M2>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", @@ -1753,6 +1469,13 @@ "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; status = "disabled"; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 0ce0b278e1cb..e164eda69baf 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -330,9 +330,7 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7791_CLK_DU0>, - <&mstp7_clks R8A7791_CLK_DU1>, - <&mstp7_clks R8A7791_CLK_LVDS0>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "lvds.0", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index 95da5cb9d37a..eb374956294f 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -419,9 +419,7 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7791_CLK_DU0>, - <&mstp7_clks R8A7791_CLK_DU1>, - <&mstp7_clks R8A7791_CLK_LVDS0>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, <&x3_clk>, <&x16_clk>; clock-names = "du.0", "du.1", "lvds.0", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index f1d1a9772153..67831d0405f3 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -10,7 +10,7 @@ * kind, whether express or implied. */ -#include <dt-bindings/clock/r8a7791-clock.h> +#include <dt-bindings/clock/r8a7791-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/r8a7791-sysc.h> @@ -51,7 +51,7 @@ reg = <0>; clock-frequency = <1500000000>; voltage-tolerance = <1>; /* 1% */ - clocks = <&cpg_clocks R8A7791_CLK_Z>; + clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7791_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; @@ -70,6 +70,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; power-domains = <&sysc R8A7791_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; @@ -117,13 +118,14 @@ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&mstp4_clks R8A7791_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -131,12 +133,13 @@ gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -144,12 +147,13 @@ gpio-ranges = <&pfc 0 32 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -157,12 +161,13 @@ gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -170,12 +175,13 @@ gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -183,12 +189,13 @@ gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -196,12 +203,13 @@ gpio-ranges = <&pfc 0 160 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -209,12 +217,13 @@ gpio-ranges = <&pfc 0 192 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; + clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 905>; }; gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -222,8 +231,9 @@ gpio-ranges = <&pfc 0 224 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; + clocks = <&cpg CPG_MOD 904>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 904>; }; thermal: thermal@e61f0000 { @@ -232,8 +242,9 @@ "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; + clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 522>; #thermal-sensor-cells = <0>; }; @@ -250,9 +261,10 @@ reg = <0 0xffca0000 0 0x1004>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7791_CLK_CMT0>; + clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 124>; renesas,channels-mask = <0x60>; @@ -270,9 +282,10 @@ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_CMT1>; + clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 329>; renesas,channels-mask = <0xff>; @@ -294,8 +307,9 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp4_clks R8A7791_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; dmac0: dma-controller@e6700000 { @@ -322,9 +336,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -353,9 +368,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -382,9 +398,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; + clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <13>; }; @@ -411,9 +428,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; + clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <13>; }; @@ -424,8 +442,9 @@ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>; + clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 330>; #dma-cells = <1>; dma-channels = <2>; }; @@ -436,8 +455,9 @@ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>; + clocks = <&cpg CPG_MOD 331>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 331>; #dma-cells = <1>; dma-channels = <2>; }; @@ -449,8 +469,9 @@ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 931>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -461,8 +482,9 @@ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 930>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -473,8 +495,9 @@ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 929>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -485,8 +508,9 @@ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 928>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -497,8 +521,9 @@ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6520000 0 0x40>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C4>; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 927>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -510,8 +535,9 @@ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6528000 0 0x40>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C5>; + clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 925>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -524,11 +550,12 @@ "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x425>; interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; + clocks = <&cpg CPG_MOD 926>; dmas = <&dmac0 0x77>, <&dmac0 0x78>, <&dmac1 0x77>, <&dmac1 0x78>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 926>; status = "disabled"; }; @@ -539,11 +566,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_IIC0>; + clocks = <&cpg CPG_MOD 318>; dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 318>; status = "disabled"; }; @@ -554,11 +582,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x425>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_IIC1>; + clocks = <&cpg CPG_MOD 323>; dmas = <&dmac0 0x65>, <&dmac0 0x66>, <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 323>; status = "disabled"; }; @@ -571,11 +600,12 @@ compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; + clocks = <&cpg CPG_MOD 315>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 315>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -585,12 +615,13 @@ compatible = "renesas,sdhi-r8a7791"; reg = <0 0xee100000 0 0x328>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; @@ -598,12 +629,13 @@ compatible = "renesas,sdhi-r8a7791"; reg = <0 0xee140000 0 0x100>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; + clocks = <&cpg CPG_MOD 312>; dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 312>; status = "disabled"; }; @@ -611,12 +643,13 @@ compatible = "renesas,sdhi-r8a7791"; reg = <0 0xee160000 0 0x100>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; + clocks = <&cpg CPG_MOD 311>; dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 311>; status = "disabled"; }; @@ -625,12 +658,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; + clocks = <&cpg CPG_MOD 204>; clock-names = "fck"; dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -639,12 +673,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; + clocks = <&cpg CPG_MOD 203>; clock-names = "fck"; dmas = <&dmac0 0x25>, <&dmac0 0x26>, <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -653,12 +688,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; + clocks = <&cpg CPG_MOD 202>; clock-names = "fck"; dmas = <&dmac0 0x27>, <&dmac0 0x28>, <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -667,12 +703,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c70000 0 64>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; + clocks = <&cpg CPG_MOD 1106>; clock-names = "fck"; dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, <&dmac1 0x1b>, <&dmac1 0x1c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1106>; status = "disabled"; }; @@ -681,12 +718,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c78000 0 64>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; + clocks = <&cpg CPG_MOD 1107>; clock-names = "fck"; dmas = <&dmac0 0x1f>, <&dmac0 0x20>, <&dmac1 0x1f>, <&dmac1 0x20>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1107>; status = "disabled"; }; @@ -695,12 +733,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c80000 0 64>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; + clocks = <&cpg CPG_MOD 1108>; clock-names = "fck"; dmas = <&dmac0 0x23>, <&dmac0 0x24>, <&dmac1 0x23>, <&dmac1 0x24>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1108>; status = "disabled"; }; @@ -709,12 +748,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; + clocks = <&cpg CPG_MOD 206>; clock-names = "fck"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -723,12 +763,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; + clocks = <&cpg CPG_MOD 207>; clock-names = "fck"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>, <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -737,12 +778,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; + clocks = <&cpg CPG_MOD 216>; clock-names = "fck"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -751,13 +793,14 @@ "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -766,22 +809,24 @@ "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; adc: adc@e6e54000 { compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; reg = <0 0xe6e54000 0 64>; - clocks = <&mstp9_clks R8A7791_CLK_GYROADC>; + clocks = <&cpg CPG_MOD 901>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 901>; status = "disabled"; }; @@ -790,13 +835,14 @@ "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -805,13 +851,14 @@ "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>, + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -820,13 +867,14 @@ "renesas,scif"; reg = <0 0xe6ee0000 0 64>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>, + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, <&dmac1 0xfb>, <&dmac1 0xfc>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 715>; status = "disabled"; }; @@ -835,13 +883,14 @@ "renesas,scif"; reg = <0 0xe6ee8000 0 64>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>, + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, <&dmac1 0xfd>, <&dmac1 0xfe>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 714>; status = "disabled"; }; @@ -850,13 +899,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -865,13 +915,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -880,13 +931,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62d0000 0 96>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, <&dmac1 0x3b>, <&dmac1 0x3c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 713>; status = "disabled"; }; @@ -912,8 +964,9 @@ compatible = "renesas,ether-r8a7791"; reg = <0 0xee700000 0 0x400>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_ETHER>; + clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -925,8 +978,9 @@ "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -936,8 +990,9 @@ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; reg = <0 0xee300000 0 0x2000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_SATA0>; + clocks = <&cpg CPG_MOD 815>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 815>; status = "disabled"; }; @@ -945,8 +1000,9 @@ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; reg = <0 0xee500000 0 0x2000>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_SATA1>; + clocks = <&cpg CPG_MOD 814>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 814>; status = "disabled"; }; @@ -954,11 +1010,12 @@ compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs"; reg = <0 0xe6590000 0 0x100>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 704>; renesas,buswait = <4>; phys = <&usb0 1>; phy-names = "usb"; @@ -971,9 +1028,10 @@ reg = <0 0xe6590100 0 0x100>; #address-cells = <1>; #size-cells = <0>; - clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; clock-names = "usbhs"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 704>; status = "disabled"; usb0: usb-channel@0 { @@ -990,8 +1048,9 @@ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -999,8 +1058,9 @@ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -1008,33 +1068,37 @@ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_VIN2>; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 809>; status = "disabled"; }; - vsp1@fe928000 { + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; + clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 131>; }; - vsp1@fe930000 { + vsp@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; + clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; - vsp1@fe938000 { + vsp@fe938000 { compatible = "renesas,vsp1"; reg = <0 0xfe938000 0 0x8000>; interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; + clocks = <&cpg CPG_MOD 127>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 127>; }; du: display@feb00000 { @@ -1044,9 +1108,9 @@ reg-names = "du", "lvds.0"; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_DU0>, - <&mstp7_clks R8A7791_CLK_DU1>, - <&mstp7_clks R8A7791_CLK_LVDS0>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 726>; clock-names = "du.0", "du.1", "lvds.0"; status = "disabled"; @@ -1071,10 +1135,11 @@ compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, - <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7791_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -1082,10 +1147,11 @@ compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, - <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7791_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; @@ -1093,435 +1159,78 @@ compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu"; reg = <0 0xfe980000 0 0x10300>; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7791_CLK_JPU>; + clocks = <&cpg CPG_MOD 106>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 106>; }; - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency clocks by - * default. Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7791-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z", - "rcan", "adsp"; - #power-domain-cells = <0>; - }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssp_clk: ssp@e6150248 { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150248 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssprs_clk: ssprs@e615024c { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615024c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - b_clk: b { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cl_clk: cl { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - oscclk_clk: oscclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(12 * 1024)>; - clock-mult = <1>; - }; - zb3_clk: zb3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - zb3d2_clk: zb3d2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - ddr_clk: ddr { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = <R8A7791_CLK_MSIOF0>; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>, - <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU - R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG - R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 - R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 - R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 - R8A7791_CLK_VSP1_S - >; - clock-output-names = - "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg", - "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0", - "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 - R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 - R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 - R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "scifb2", - "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 - R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 - R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 - R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1 - >; - clock-output-names = - "tpu0", "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1", - "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = <R8A7791_CLK_IRQC R8A7791_CLK_INTC_SYS>; - clock-output-names = "irqc", "intc-sys"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>, - <&extal_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 - R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL - R8A7791_CLK_PWM - >; - clock-output-names = "audmac0", "audmac1", "adsp_mod", - "thermal", "pwm"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&zx_clk>, <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 - R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 - R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 - R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 - R8A7791_CLK_LVDS0 - >; - clock-output-names = - "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", - "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB - R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 - R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER - R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 - >; - clock-output-names = - "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", - "etheravb", "ether", "sata1", "sata0"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&p_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, - <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_GYROADC - R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 - R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 - R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 - R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 - R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 - >; - clock-output-names = - "gyroadc", - "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", - "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", - "i2c1", "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&p_clk>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; - - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_SSI_ALL - R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 - R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 - R8A7791_CLK_SCU_ALL - R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 - R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0 - R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 - R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 - >; - clock-output-names = - "ssi-all", - "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", - "scu-all", - "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", - "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; - }; - mstp11_clks: mstp11_clks@e615099c { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 - >; - clock-output-names = "scifa3", "scifa4", "scifa5"; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7791-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; }; rst: reset-controller@e6160000 { @@ -1544,11 +1253,12 @@ compatible = "renesas,qspi-r8a7791", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1560,11 +1270,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e20000 0 0x0064>; interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; + clocks = <&cpg CPG_MOD 000>; dmas = <&dmac0 0x51>, <&dmac0 0x52>, <&dmac1 0x51>, <&dmac1 0x52>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1575,11 +1286,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e10000 0 0x0064>; interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; + clocks = <&cpg CPG_MOD 208>; dmas = <&dmac0 0x55>, <&dmac0 0x56>, <&dmac1 0x55>, <&dmac1 0x56>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 208>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1590,11 +1302,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e00000 0 0x0064>; interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; + clocks = <&cpg CPG_MOD 205>; dmas = <&dmac0 0x41>, <&dmac0 0x42>, <&dmac1 0x41>, <&dmac1 0x42>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 205>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1604,8 +1317,9 @@ compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci"; reg = <0 0xee000000 0 0xc00>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; + clocks = <&cpg CPG_MOD 328>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 328>; phys = <&usb2 1>; phy-names = "usb"; status = "disabled"; @@ -1617,8 +1331,9 @@ reg = <0 0xee090000 0 0xc00>, <0 0xee080000 0 0x1100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <0 0>; @@ -1650,8 +1365,9 @@ reg = <0 0xee0d0000 0 0xc00>, <0 0xee0c0000 0 0x1100>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7791_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <1 1>; @@ -1697,9 +1413,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 319>; status = "disabled"; }; @@ -1778,21 +1495,22 @@ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, - <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, - <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>, - <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>, - <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>, - <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>, - <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>, - <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, - <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, - <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, - <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7791_CLK_M2>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", @@ -1803,6 +1521,13 @@ "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; status = "disabled"; diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index f3ea43b7b724..9b67dca6c9ef 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -310,8 +310,7 @@ pinctrl-0 = <&du0_pins &du1_pins>; pinctrl-names = "default"; - clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>, - <&x1_clk>, <&x2_clk>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; status = "okay"; diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index c24f26fdab1f..b9471b67b728 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -305,8 +305,7 @@ pinctrl-0 = <&du0_pins &du1_pins>; pinctrl-names = "default"; - clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>, - <&osc2_clk>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&osc2_clk>; clock-names = "du.0", "du.1", "dclkin.0"; status = "okay"; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 2623f39bed2b..131f65b0426e 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -8,7 +8,7 @@ * kind, whether express or implied. */ -#include <dt-bindings/clock/r8a7792-clock.h> +#include <dt-bindings/clock/r8a7792-cpg-mssr.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7792-sysc.h> @@ -46,7 +46,7 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1000000000>; - clocks = <&z_clk>; + clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; power-domains = <&sysc R8A7792_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; }; @@ -56,6 +56,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; power-domains = <&sysc R8A7792_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; @@ -92,9 +93,10 @@ <0 0xf1006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&mstp4_clks R8A7792_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; irqc: interrupt-controller@e61c0000 { @@ -106,8 +108,9 @@ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp4_clks R8A7792_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; timer { @@ -145,7 +148,7 @@ gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -153,13 +156,14 @@ gpio-ranges = <&pfc 0 0 29>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -167,13 +171,14 @@ gpio-ranges = <&pfc 0 32 23>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -181,13 +186,14 @@ gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -195,13 +201,14 @@ gpio-ranges = <&pfc 0 96 28>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -209,13 +216,14 @@ gpio-ranges = <&pfc 0 128 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -223,13 +231,14 @@ gpio-ranges = <&pfc 0 160 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; gpio6: gpio@e6055100 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055100 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -237,13 +246,14 @@ gpio-ranges = <&pfc 0 192 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO6>; + clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 905>; }; gpio7: gpio@e6055200 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055200 0 0x50>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -251,13 +261,14 @@ gpio-ranges = <&pfc 0 224 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO7>; + clocks = <&cpg CPG_MOD 904>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 904>; }; gpio8: gpio@e6055300 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055300 0 0x50>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -265,13 +276,14 @@ gpio-ranges = <&pfc 0 256 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO8>; + clocks = <&cpg CPG_MOD 921>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 921>; }; gpio9: gpio@e6055400 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -279,13 +291,14 @@ gpio-ranges = <&pfc 0 288 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO9>; + clocks = <&cpg CPG_MOD 919>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 919>; }; gpio10: gpio@e6055500 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055500 0 0x50>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -293,13 +306,14 @@ gpio-ranges = <&pfc 0 320 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO10>; + clocks = <&cpg CPG_MOD 914>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 914>; }; gpio11: gpio@e6055600 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055600 0 0x50>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -307,8 +321,9 @@ gpio-ranges = <&pfc 0 352 30>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO11>; + clocks = <&cpg CPG_MOD 913>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 913>; }; dmac0: dma-controller@e6700000 { @@ -336,9 +351,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -368,9 +384,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -380,13 +397,14 @@ "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -395,13 +413,14 @@ "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -410,13 +429,14 @@ "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -425,13 +445,14 @@ "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -440,13 +461,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -455,13 +477,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -490,8 +513,9 @@ dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; - clocks = <&mstp3_clks R8A7792_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; @@ -500,8 +524,9 @@ "renesas,rcar-gen2-jpu"; reg = <0 0xfe980000 0 0x10300>; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7792_CLK_JPU>; + clocks = <&cpg CPG_MOD 106>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 106>; }; avb: ethernet@e6800000 { @@ -509,8 +534,9 @@ "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -522,8 +548,9 @@ "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 931>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -535,8 +562,9 @@ "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 930>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -548,8 +576,9 @@ "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 929>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -561,8 +590,9 @@ "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 928>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -574,8 +604,9 @@ "renesas,rcar-gen2-i2c"; reg = <0 0xe6520000 0 0x40>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_I2C4>; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 927>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -587,8 +618,9 @@ "renesas,rcar-gen2-i2c"; reg = <0 0xe6528000 0 0x40>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_I2C5>; + clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 925>; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; #size-cells = <0>; @@ -599,11 +631,12 @@ compatible = "renesas,qspi-r8a7792", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -615,11 +648,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e20000 0 0x0064>; interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>; + clocks = <&cpg CPG_MOD 000>; dmas = <&dmac0 0x51>, <&dmac0 0x52>, <&dmac1 0x51>, <&dmac1 0x52>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -630,11 +664,12 @@ "renesas,rcar-gen2-msiof"; reg = <0 0xe6e10000 0 0x0064>; interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>; + clocks = <&cpg CPG_MOD 208>; dmas = <&dmac0 0x55>, <&dmac0 0x56>, <&dmac1 0x55>, <&dmac1 0x56>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 208>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -646,8 +681,8 @@ reg-names = "du"; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7792_CLK_DU0>, - <&mstp7_clks R8A7792_CLK_DU1>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; status = "disabled"; @@ -673,10 +708,11 @@ "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_CAN0>, - <&rcan_clk>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -685,10 +721,11 @@ "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7792_CLK_CAN1>, - <&rcan_clk>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; @@ -697,8 +734,9 @@ "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -707,8 +745,9 @@ "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -717,8 +756,9 @@ "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_VIN2>; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 809>; status = "disabled"; }; @@ -727,8 +767,9 @@ "renesas,rcar-gen2-vin"; reg = <0 0xe6ef3000 0 0x1000>; interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_VIN3>; + clocks = <&cpg CPG_MOD 808>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 808>; status = "disabled"; }; @@ -737,8 +778,9 @@ "renesas,rcar-gen2-vin"; reg = <0 0xe6ef4000 0 0x1000>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_VIN4>; + clocks = <&cpg CPG_MOD 805>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 805>; status = "disabled"; }; @@ -747,254 +789,47 @@ "renesas,rcar-gen2-vin"; reg = <0 0xe6ef5000 0 0x1000>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7792_CLK_VIN5>; + clocks = <&cpg CPG_MOD 804>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 804>; status = "disabled"; }; - vsp1@fe928000 { + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>; + clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 131>; }; - vsp1@fe930000 { + vsp@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>; + clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; - vsp1@fe938000 { + vsp@fe938000 { compatible = "renesas,vsp1"; reg = <0 0xfe938000 0 0x8000>; interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>; + clocks = <&cpg CPG_MOD 127>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 127>; }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7792-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7792-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; clocks = <&extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi"; + clock-names = "extal"; + #clock-cells = <2>; #power-domain-cells = <0>; }; - - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - z_clk: z { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL0>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - sd_clk: sd { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rcan_clk: rcan { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <49>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <5>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = <R8A7792_CLK_MSIOF0>; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_JPU - R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0 - R8A7792_CLK_VSP1_SY - >; - clock-output-names = "jpu", "vsp1du1", "vsp1du0", - "vsp1-sy"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_MSIOF1 - R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0 - >; - clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&sd_clk>; - #clock-cells = <1>; - renesas,clock-indices = <R8A7792_CLK_SDHI0>; - clock-output-names = "sdhi0"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_IRQC R8A7792_CLK_INTC_SYS - >; - clock-output-names = "irqc", "intc-sys"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0 - R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2 - R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0 - R8A7792_CLK_DU1 R8A7792_CLK_DU0 - >; - clock-output-names = "hscif1", "hscif0", "scif3", - "scif2", "scif1", "scif0", - "du1", "du0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&zg_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_VIN5 R8A7792_CLK_VIN4 - R8A7792_CLK_VIN3 R8A7792_CLK_VIN2 - R8A7792_CLK_VIN1 R8A7792_CLK_VIN0 - R8A7792_CLK_ETHERAVB - >; - clock-output-names = "vin5", "vin4", "vin3", "vin2", - "vin1", "vin0", "etheravb"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, - <&cpg_clocks R8A7792_CLK_QSPI>, - <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 - R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4 - R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2 - R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0 - R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 - R8A7792_CLK_CAN1 R8A7792_CLK_CAN0 - R8A7792_CLK_QSPI_MOD - R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 - R8A7792_CLK_I2C5 R8A7792_CLK_I2C4 - R8A7792_CLK_I2C3 R8A7792_CLK_I2C2 - R8A7792_CLK_I2C1 R8A7792_CLK_I2C0 - >; - clock-output-names = - "gpio7", "gpio6", "gpio5", "gpio4", - "gpio3", "gpio2", "gpio1", "gpio0", - "gpio11", "gpio10", "can1", "can0", - "qspi_mod", "gpio9", "gpio8", - "i2c5", "i2c4", "i2c3", "i2c2", - "i2c1", "i2c0"; - }; }; /* External root clock */ diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 76e3aca2029e..51b3ffac8efa 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -303,9 +303,7 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7793_CLK_DU0>, - <&mstp7_clks R8A7793_CLK_DU1>, - <&mstp7_clks R8A7793_CLK_LVDS0>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "lvds.0", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 497716b6fbe2..58eae569b4e0 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -8,7 +8,7 @@ * kind, whether express or implied. */ -#include <dt-bindings/clock/r8a7793-clock.h> +#include <dt-bindings/clock/r8a7793-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/r8a7793-sysc.h> @@ -43,7 +43,7 @@ reg = <0>; clock-frequency = <1500000000>; voltage-tolerance = <1>; /* 1% */ - clocks = <&cpg_clocks R8A7793_CLK_Z>; + clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7793_PD_CA15_CPU0>; @@ -62,6 +62,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; power-domains = <&sysc R8A7793_PD_CA15_CPU1>; }; @@ -108,13 +109,14 @@ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&mstp4_clks R8A7793_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -122,12 +124,13 @@ gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -135,12 +138,13 @@ gpio-ranges = <&pfc 0 32 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -148,12 +152,13 @@ gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -161,12 +166,13 @@ gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -174,12 +180,13 @@ gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -187,12 +194,13 @@ gpio-ranges = <&pfc 0 160 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -200,12 +208,13 @@ gpio-ranges = <&pfc 0 192 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO6>; + clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 905>; }; gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -213,8 +222,9 @@ gpio-ranges = <&pfc 0 224 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO7>; + clocks = <&cpg CPG_MOD 904>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 904>; }; thermal: thermal@e61f0000 { @@ -223,8 +233,9 @@ "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp5_clks R8A7793_CLK_THERMAL>; + clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 522>; #thermal-sensor-cells = <0>; }; @@ -241,9 +252,10 @@ reg = <0 0xffca0000 0 0x1004>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7793_CLK_CMT0>; + clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 124>; renesas,channels-mask = <0x60>; @@ -261,9 +273,10 @@ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_CMT1>; + clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 329>; renesas,channels-mask = <0xff>; @@ -285,8 +298,9 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp4_clks R8A7793_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; dmac0: dma-controller@e6700000 { @@ -313,9 +327,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -344,9 +359,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -373,9 +389,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>; + clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <13>; }; @@ -402,9 +419,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>; + clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <13>; }; @@ -416,8 +434,9 @@ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 931>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -428,8 +447,9 @@ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 930>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -440,8 +460,9 @@ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 929>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -452,8 +473,9 @@ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 928>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -464,8 +486,9 @@ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6520000 0 0x40>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_I2C4>; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 927>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -477,8 +500,9 @@ compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6528000 0 0x40>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_I2C5>; + clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 925>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -491,11 +515,12 @@ "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x425>; interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>; + clocks = <&cpg CPG_MOD 926>; dmas = <&dmac0 0x77>, <&dmac0 0x78>, <&dmac1 0x77>, <&dmac1 0x78>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 926>; status = "disabled"; }; @@ -506,11 +531,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_IIC0>; + clocks = <&cpg CPG_MOD 318>; dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 318>; status = "disabled"; }; @@ -521,11 +547,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x425>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_IIC1>; + clocks = <&cpg CPG_MOD 323>; dmas = <&dmac0 0x65>, <&dmac0 0x66>, <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 323>; status = "disabled"; }; @@ -538,12 +565,13 @@ compatible = "renesas,sdhi-r8a7793"; reg = <0 0xee100000 0 0x328>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; @@ -551,12 +579,13 @@ compatible = "renesas,sdhi-r8a7793"; reg = <0 0xee140000 0 0x100>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_SDHI1>; + clocks = <&cpg CPG_MOD 312>; dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 312>; status = "disabled"; }; @@ -564,12 +593,13 @@ compatible = "renesas,sdhi-r8a7793"; reg = <0 0xee160000 0 0x100>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_SDHI2>; + clocks = <&cpg CPG_MOD 311>; dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 311>; status = "disabled"; }; @@ -577,11 +607,12 @@ compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>; + clocks = <&cpg CPG_MOD 315>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 315>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -592,12 +623,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>; + clocks = <&cpg CPG_MOD 204>; clock-names = "fck"; dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -606,12 +638,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>; + clocks = <&cpg CPG_MOD 203>; clock-names = "fck"; dmas = <&dmac0 0x25>, <&dmac0 0x26>, <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -620,12 +653,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>; + clocks = <&cpg CPG_MOD 202>; clock-names = "fck"; dmas = <&dmac0 0x27>, <&dmac0 0x28>, <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -634,12 +668,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c70000 0 64>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>; + clocks = <&cpg CPG_MOD 1106>; clock-names = "fck"; dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, <&dmac1 0x1b>, <&dmac1 0x1c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1106>; status = "disabled"; }; @@ -648,12 +683,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c78000 0 64>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>; + clocks = <&cpg CPG_MOD 1107>; clock-names = "fck"; dmas = <&dmac0 0x1f>, <&dmac0 0x20>, <&dmac1 0x1f>, <&dmac1 0x20>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1107>; status = "disabled"; }; @@ -662,12 +698,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c80000 0 64>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>; + clocks = <&cpg CPG_MOD 1108>; clock-names = "fck"; dmas = <&dmac0 0x23>, <&dmac0 0x24>, <&dmac1 0x23>, <&dmac1 0x24>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1108>; status = "disabled"; }; @@ -676,12 +713,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>; + clocks = <&cpg CPG_MOD 206>; clock-names = "fck"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -690,12 +728,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>; + clocks = <&cpg CPG_MOD 207>; clock-names = "fck"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>, <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -704,12 +743,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>; + clocks = <&cpg CPG_MOD 216>; clock-names = "fck"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -718,13 +758,14 @@ "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -733,13 +774,14 @@ "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -748,13 +790,14 @@ "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -763,13 +806,14 @@ "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>, + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -778,13 +822,14 @@ "renesas,scif"; reg = <0 0xe6ee0000 0 64>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>, + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, <&dmac1 0xfb>, <&dmac1 0xfc>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 715>; status = "disabled"; }; @@ -793,13 +838,14 @@ "renesas,scif"; reg = <0 0xe6ee8000 0 64>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>, + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, <&dmac1 0xfd>, <&dmac1 0xfe>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 714>; status = "disabled"; }; @@ -808,13 +854,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -823,13 +870,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -838,13 +886,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62d0000 0 96>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, <&dmac1 0x3b>, <&dmac1 0x3c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 713>; status = "disabled"; }; @@ -870,8 +919,9 @@ compatible = "renesas,ether-r8a7793"; reg = <0 0xee700000 0 0x400>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7793_CLK_ETHER>; + clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -882,8 +932,9 @@ compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7793_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -891,8 +942,9 @@ compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7793_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -900,8 +952,9 @@ compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7793_CLK_VIN2>; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 809>; status = "disabled"; }; @@ -909,11 +962,12 @@ compatible = "renesas,qspi-r8a7793", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -927,9 +981,9 @@ reg-names = "du", "lvds.0"; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7793_CLK_DU0>, - <&mstp7_clks R8A7793_CLK_DU1>, - <&mstp7_clks R8A7793_CLK_LVDS0>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 726>; clock-names = "du.0", "du.1", "lvds.0"; status = "disabled"; @@ -954,10 +1008,11 @@ compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_RCAN0>, - <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -965,376 +1020,74 @@ compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7793_CLK_RCAN1>, - <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency clocks by - * default. Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7793-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z", - "rcan", "adsp"; - #power-domain-cells = <0>; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7793-div6-clock", - "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7793-div6-clock", - "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7793-div6-clock", - "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <5>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Gate clocks */ - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, - <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, - <&zs_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_VCP0 R8A7793_CLK_VPC0 - R8A7793_CLK_SSP1 R8A7793_CLK_TMU1 - R8A7793_CLK_3DG R8A7793_CLK_2DDMAC - R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0 - R8A7793_CLK_TMU3 R8A7793_CLK_TMU2 - R8A7793_CLK_CMT0 R8A7793_CLK_TMU0 - R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0 - R8A7793_CLK_VSP1_S - >; - clock-output-names = - "vcp0", "vpc0", "ssp_dev", "tmu1", - "pvrsrvkm", "tddmac", "fdp1", "fdp0", - "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", - "vsp1-du0", "vsps"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0 - R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2 - R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "scifb0", - "scifb1", "scifb2", "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, - <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, - <&rclk_clk>, <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2 - R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0 - R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0 - R8A7793_CLK_PCIEC R8A7793_CLK_IIC1 - R8A7793_CLK_SSUSB R8A7793_CLK_CMT1 - R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1 - >; - clock-output-names = - "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "i2c7", "pciec", "i2c8", "ssusb", "cmt1", - "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_IRQC R8A7793_CLK_INTC_SYS - >; - clock-output-names = "irqc", "intc-sys"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>; - #clock-cells = <1>; - clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1 - R8A7793_CLK_THERMAL>; - clock-output-names = "audmac0", "audmac1", "thermal"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, - <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_EHCI R8A7793_CLK_HSUSB - R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5 - R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1 - R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3 - R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1 - R8A7793_CLK_SCIF0 R8A7793_CLK_DU1 - R8A7793_CLK_DU0 R8A7793_CLK_LVDS0 - >; - clock-output-names = - "ehci", "hsusb", "hscif2", "scif5", "scif4", - "hscif1", "hscif0", "scif3", "scif2", - "scif1", "scif0", "du1", "du0", "lvds0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&p_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2 - R8A7793_CLK_VIN1 R8A7793_CLK_VIN0 - R8A7793_CLK_ETHER R8A7793_CLK_SATA1 - R8A7793_CLK_SATA0 - >; - clock-output-names = - "ipmmu_sgx", "vin2", "vin1", "vin0", "ether", - "sata1", "sata0"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&p_clk>, <&p_clk>, - <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>, - <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6 - R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4 - R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2 - R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0 - R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1 - R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5 - R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4 - R8A7793_CLK_I2C3 R8A7793_CLK_I2C2 - R8A7793_CLK_I2C1 R8A7793_CLK_I2C0 - >; - clock-output-names = - "gpio7", "gpio6", "gpio5", "gpio4", - "gpio3", "gpio2", "gpio1", "gpio0", - "rcan1", "rcan0", "qspi_mod", "i2c5", - "i2c6", "i2c4", "i2c3", "i2c2", "i2c1", - "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&p_clk>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>; - - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_SSI_ALL - R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5 - R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0 - R8A7793_CLK_SCU_ALL - R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0 - R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0 - R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5 - R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0 - >; - clock-output-names = - "ssi-all", - "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", - "scu-all", - "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", - "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; - }; - mstp11_clks: mstp11_clks@e615099c { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5 - >; - clock-output-names = "scifa3", "scifa4", "scifa5"; - }; + /* Special CPG clocks */ + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7793-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; }; rst: reset-controller@e6160000 { @@ -1428,19 +1181,20 @@ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>, - <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>, - <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>, - <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>, - <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>, - <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>, - <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>, - <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>, - <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>, - <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>, - <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7793_CLK_M2>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", @@ -1449,6 +1203,13 @@ "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; status = "disabled"; diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index f1eea13cdf44..bd98790d964e 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -167,8 +167,7 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU1>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; @@ -305,7 +304,7 @@ vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; sd-uhs-sdr50; sd-uhs-sdr104; status = "okay"; @@ -319,7 +318,7 @@ vmmc-supply = <&vcc_sdhi1>; vqmmc-supply = <&vccq_sdhi1>; cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; sd-uhs-sdr50; status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 4cb5278d104d..edfad0e5ac53 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -423,8 +423,7 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU1>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x2_clk>, <&x3_clk>; clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 26535414203a..905e50c9b524 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -9,7 +9,7 @@ * kind, whether express or implied. */ -#include <dt-bindings/clock/r8a7794-clock.h> +#include <dt-bindings/clock/r8a7794-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/r8a7794-sysc.h> @@ -43,7 +43,7 @@ compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; - clocks = <&z2_clk>; + clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; power-domains = <&sysc R8A7794_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; }; @@ -53,6 +53,7 @@ compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; power-domains = <&sysc R8A7794_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; }; @@ -75,13 +76,14 @@ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&mstp4_clks R8A7794_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -89,12 +91,13 @@ gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -102,12 +105,13 @@ gpio-ranges = <&pfc 0 32 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -115,12 +119,13 @@ gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -128,12 +133,13 @@ gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -141,12 +147,13 @@ gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -154,12 +161,13 @@ gpio-ranges = <&pfc 0 160 28>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -167,8 +175,9 @@ gpio-ranges = <&pfc 0 192 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO6>; + clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 905>; }; cmt0: timer@ffca0000 { @@ -176,9 +185,10 @@ reg = <0 0xffca0000 0 0x1004>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7794_CLK_CMT0>; + clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 124>; renesas,channels-mask = <0x60>; @@ -196,9 +206,10 @@ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_CMT1>; + clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 329>; renesas,channels-mask = <0xff>; @@ -228,8 +239,9 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp4_clks R8A7794_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; pfc: pin-controller@e6060000 { @@ -261,9 +273,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -292,9 +305,10 @@ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -320,9 +334,10 @@ "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>; + clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <13>; }; @@ -332,12 +347,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; + clocks = <&cpg CPG_MOD 204>; clock-names = "fck"; dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -346,12 +362,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; + clocks = <&cpg CPG_MOD 203>; clock-names = "fck"; dmas = <&dmac0 0x25>, <&dmac0 0x26>, <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -360,12 +377,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; + clocks = <&cpg CPG_MOD 202>; clock-names = "fck"; dmas = <&dmac0 0x27>, <&dmac0 0x28>, <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -374,12 +392,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c70000 0 64>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; + clocks = <&cpg CPG_MOD 1106>; clock-names = "fck"; dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, <&dmac1 0x1b>, <&dmac1 0x1c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1106>; status = "disabled"; }; @@ -388,12 +407,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c78000 0 64>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; + clocks = <&cpg CPG_MOD 1107>; clock-names = "fck"; dmas = <&dmac0 0x1f>, <&dmac0 0x20>, <&dmac1 0x1f>, <&dmac1 0x20>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1107>; status = "disabled"; }; @@ -402,12 +422,13 @@ "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c80000 0 64>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; + clocks = <&cpg CPG_MOD 1108>; clock-names = "fck"; dmas = <&dmac0 0x23>, <&dmac0 0x24>, <&dmac1 0x23>, <&dmac1 0x24>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1108>; status = "disabled"; }; @@ -416,12 +437,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; + clocks = <&cpg CPG_MOD 206>; clock-names = "fck"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -430,12 +452,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; + clocks = <&cpg CPG_MOD 207>; clock-names = "fck"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>, <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -444,12 +467,13 @@ "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; + clocks = <&cpg CPG_MOD 216>; clock-names = "fck"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -458,13 +482,14 @@ "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -473,13 +498,14 @@ "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -488,13 +514,14 @@ "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -503,13 +530,14 @@ "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>, + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -518,13 +546,14 @@ "renesas,scif"; reg = <0 0xe6ee0000 0 64>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>, + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, <&dmac1 0xfb>, <&dmac1 0xfc>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 715>; status = "disabled"; }; @@ -533,13 +562,14 @@ "renesas,scif"; reg = <0 0xe6ee8000 0 64>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>, + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, <&dmac1 0xfd>, <&dmac1 0xfe>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 714>; status = "disabled"; }; @@ -548,13 +578,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -563,13 +594,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -578,13 +610,14 @@ "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62d0000 0 96>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, <&dmac1 0x3b>, <&dmac1 0x3c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 713>; status = "disabled"; }; @@ -610,8 +643,9 @@ compatible = "renesas,ether-r8a7794"; reg = <0 0xee700000 0 0x400>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7794_CLK_ETHER>; + clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -623,8 +657,9 @@ "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -635,8 +670,9 @@ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 931>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -647,8 +683,9 @@ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 930>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -659,8 +696,9 @@ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 929>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -671,8 +709,9 @@ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 928>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -683,8 +722,9 @@ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6520000 0 0x40>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_I2C4>; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 927>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -695,8 +735,9 @@ compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6528000 0 0x40>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_I2C5>; + clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 925>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -708,11 +749,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_IIC0>; + clocks = <&cpg CPG_MOD 318>; dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 318>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -723,11 +765,12 @@ "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x425>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_IIC1>; + clocks = <&cpg CPG_MOD 323>; dmas = <&dmac0 0x65>, <&dmac0 0x66>, <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 323>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -737,11 +780,12 @@ compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; + clocks = <&cpg CPG_MOD 315>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 315>; reg-io-width = <4>; status = "disabled"; }; @@ -750,12 +794,13 @@ compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee100000 0 0x328>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; @@ -763,12 +808,13 @@ compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee140000 0 0x100>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; + clocks = <&cpg CPG_MOD 312>; dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 312>; status = "disabled"; }; @@ -776,12 +822,13 @@ compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee160000 0 0x100>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; + clocks = <&cpg CPG_MOD 311>; dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 311>; status = "disabled"; }; @@ -789,11 +836,12 @@ compatible = "renesas,qspi-r8a7794", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -804,8 +852,9 @@ compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7794_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -813,8 +862,9 @@ compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7794_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -824,8 +874,9 @@ reg = <0 0xee090000 0 0xc00>, <0 0xee080000 0 0x1100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <0 0>; @@ -857,8 +908,9 @@ reg = <0 0xee0d0000 0 0xc00>, <0 0xee0c0000 0 0x1100>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <1 1>; @@ -888,8 +940,9 @@ compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs"; reg = <0 0xe6590000 0 0x100>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 704>; renesas,buswait = <4>; phys = <&usb0 1>; phy-names = "usb"; @@ -902,9 +955,10 @@ reg = <0 0xe6590100 0 0x100>; #address-cells = <1>; #size-cells = <0>; - clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; clock-names = "usbhs"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 704>; status = "disabled"; usb0: usb-channel@0 { @@ -917,20 +971,22 @@ }; }; - vsp1@fe928000 { + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>; + clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 131>; }; - vsp1@fe930000 { + vsp@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>; + clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; du: display@feb00000 { @@ -939,8 +995,7 @@ reg-names = "du"; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU1>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; status = "disabled"; @@ -965,10 +1020,11 @@ compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_RCAN0>, - <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -976,434 +1032,73 @@ compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7794_CLK_RCAN1>, - <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* - * The external audio clocks are configured as 0 Hz fixed - * frequency clocks by default. Boards that provide audio - * clocks should override them. - */ - audio_clka: audio_clka { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkb: audio_clkb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkc: audio_clkc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7794-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "rcan"; - #power-domain-cells = <0>; - }; - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - z2_clk: z2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL0>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - b_clk: b { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cl_clk: cl { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - oscclk_clk: oscclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(12 * 1024)>; - clock-mult = <1>; - }; - zb3_clk: zb3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - zb3d2_clk: zb3d2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - ddr_clk: ddr { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - acp_clk: acp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; + /* + * The external audio clocks are configured as 0 Hz fixed + * frequency clocks by default. Boards that provide audio + * clocks should override them. + */ + audio_clka: audio_clka { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkb: audio_clkb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkc: audio_clkc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = <R8A7794_CLK_MSIOF0>; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, - <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 - R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 - R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 - R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S - >; - clock-output-names = - "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", - "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 - R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 - R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 - R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "scifb2", - "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 - R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0 - R8A7794_CLK_IIC1 R8A7794_CLK_CMT1 - R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 - >; - clock-output-names = - "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c6", "i2c7", - "cmt1", "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = <R8A7794_CLK_IRQC R8A7794_CLK_INTC_SYS>; - clock-output-names = "irqc", "intc-sys"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = <R8A7794_CLK_AUDIO_DMAC0 - R8A7794_CLK_PWM>; - clock-output-names = "audmac0", "pwm"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_EHCI R8A7794_CLK_HSUSB - R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 - R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 - R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 - R8A7794_CLK_SCIF0 - R8A7794_CLK_DU1 R8A7794_CLK_DU0 - >; - clock-output-names = - "ehci", "hsusb", - "hscif2", "scif5", "scif4", "hscif1", "hscif0", - "scif3", "scif2", "scif1", "scif0", - "du1", "du0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 - R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER - >; - clock-output-names = - "vin1", "vin0", "etheravb", "ether"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>, - <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>, - <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5 - R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3 - R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1 - R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1 - R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD - R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 - R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 - R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>; - clock-output-names = - "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", - "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", - "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7794-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&p_clk>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>; - #clock-cells = <1>; - clock-indices = <R8A7794_CLK_SSI_ALL - R8A7794_CLK_SSI9 R8A7794_CLK_SSI8 - R8A7794_CLK_SSI7 R8A7794_CLK_SSI6 - R8A7794_CLK_SSI5 R8A7794_CLK_SSI4 - R8A7794_CLK_SSI3 R8A7794_CLK_SSI2 - R8A7794_CLK_SSI1 R8A7794_CLK_SSI0 - R8A7794_CLK_SCU_ALL - R8A7794_CLK_SCU_DVC1 - R8A7794_CLK_SCU_DVC0 - R8A7794_CLK_SCU_CTU1_MIX1 - R8A7794_CLK_SCU_CTU0_MIX0 - R8A7794_CLK_SCU_SRC6 - R8A7794_CLK_SCU_SRC5 - R8A7794_CLK_SCU_SRC4 - R8A7794_CLK_SCU_SRC3 - R8A7794_CLK_SCU_SRC2 - R8A7794_CLK_SCU_SRC1>; - clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7", - "ssi6", "ssi5", "ssi4", "ssi3", - "ssi2", "ssi1", "ssi0", - "scu-all", "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src6", "scu-src5", "scu-src4", - "scu-src3", "scu-src2", "scu-src1"; - }; - mstp11_clks: mstp11_clks@e615099c { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 - >; - clock-output-names = "scifa3", "scifa4", "scifa5"; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7794-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; }; rst: reset-controller@e6160000 { @@ -1490,31 +1185,20 @@ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI9>, - <&mstp10_clks R8A7794_CLK_SSI8>, - <&mstp10_clks R8A7794_CLK_SSI7>, - <&mstp10_clks R8A7794_CLK_SSI6>, - <&mstp10_clks R8A7794_CLK_SSI5>, - <&mstp10_clks R8A7794_CLK_SSI4>, - <&mstp10_clks R8A7794_CLK_SSI3>, - <&mstp10_clks R8A7794_CLK_SSI2>, - <&mstp10_clks R8A7794_CLK_SSI1>, - <&mstp10_clks R8A7794_CLK_SSI0>, - <&mstp10_clks R8A7794_CLK_SCU_SRC6>, - <&mstp10_clks R8A7794_CLK_SCU_SRC5>, - <&mstp10_clks R8A7794_CLK_SCU_SRC4>, - <&mstp10_clks R8A7794_CLK_SCU_SRC3>, - <&mstp10_clks R8A7794_CLK_SCU_SRC2>, - <&mstp10_clks R8A7794_CLK_SCU_SRC1>, - <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, - <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, - <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7794_CLK_SCU_DVC0>, - <&mstp10_clks R8A7794_CLK_SCU_DVC1>, + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, + <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, + <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clka>, <&audio_clkb>, <&audio_clkc>, - <&m2_clk>; + <&cpg CPG_CORE R8A7794_CLK_M2>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", @@ -1525,6 +1209,13 @@ "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; status = "disabled"; diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index fdb1570bc7d3..e2a0f576946f 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -135,6 +135,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 4916c65e0ace..3b704cfed69a 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -152,6 +152,25 @@ }; }; + gpu: gpu@10090000 { + compatible = "rockchip,rk3036-mali", "arm,mali-400"; + reg = <0x10090000 0x10000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0"; + assigned-clocks = <&cru SCLK_GPU>; + assigned-clock-rates = <100000000>; + clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; + clock-names = "core", "bus"; + resets = <&cru SRST_GPU>; + status = "disabled"; + }; + vop: vop@10118000 { compatible = "rockchip,rk3036-vop"; reg = <0x10118000 0x19c>; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 400cbf9609e3..cdf301f5778b 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -196,7 +196,7 @@ clock-frequency = <400000>; status = "okay"; - ak8963: ak8963@0d { + ak8963: ak8963@d { compatible = "asahi-kasei,ak8975"; reg = <0x0d>; interrupt-parent = <&gpio4>; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index f50481fd8e5c..06523caca27d 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -610,6 +610,30 @@ }; }; +&gpu { + compatible = "rockchip,rk3066-mali", "arm,mali-400"; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 53d6fc2fdbce..00e05a6662ac 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -176,6 +176,10 @@ cpu0-supply = <&vdd_arm>; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 1399bc04ea77..aa10caae51c3 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -553,6 +553,30 @@ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; }; +&gpu { + compatible = "rockchip,rk3188-mali", "arm,mali-400"; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; +}; + &i2c0 { compatible = "rockchip,rk3188-i2c"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 06814421eed2..780ec3a99b21 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -558,6 +558,27 @@ status = "disabled"; }; + gpu: gpu@20000000 { + compatible = "rockchip,rk3228-mali", "arm,mali-400"; + reg = <0x20000000 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1"; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "core", "bus"; + resets = <&cru SRST_GPU_A>; + status = "disabled"; + }; + vpu_mmu: iommu@20020800 { compatible = "rockchip,iommu"; reg = <0x20020800 0x100>; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi index 5f05815f47e0..5f1e336dbaac 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi @@ -184,6 +184,7 @@ regulator-name = "vdd10_lcd"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + regulator-always-on; }; vcca_18: REG7 { @@ -223,6 +224,7 @@ regulator-name = "vcc18_lcd"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index 7da0947ababb..eab176e3dfc3 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -226,6 +226,13 @@ }; }; +&hdmi { + ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec_c0>; + status = "okay"; +}; + &i2c0 { hym8563: hym8563@51 { compatible = "haoyu,hym8563"; @@ -255,6 +262,10 @@ }; }; +&i2c5 { + status = "okay"; +}; + &i2s { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index f084e0c8dcb3..c06d0f4ceb81 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -384,7 +384,7 @@ status = "okay"; clock-frequency = <400000>; - ak8963: ak8963@0d { + ak8963: ak8963@d { compatible = "asahi-kasei,ak8975"; reg = <0x0d>; interrupt-parent = <&gpio8>; diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts new file mode 100644 index 000000000000..9842a006e823 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -0,0 +1,498 @@ +/* + * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288.dtsi" + +/ { + model = "Amarula Vyasa-RK3288"; + compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; + + chosen { + stdout-path = &uart2; + }; + + memory { + reg = <0x0 0x0 0x0 0x80000000>; + device_type = "memory"; + }; + + dc12_vbat: dc12-vbat { + compatible = "regulator-fixed"; + regulator-name = "dc12_vbat"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vboot_3v3: vboot-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vboot_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc12_vbat>; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc12_vbat>; + }; + + vboot_5v: vboot-5v { + compatible = "regulator-fixed"; + regulator-name = "vboot_sv"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc12_vbat>; + }; + + v3g_3v3: v3g-3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3g_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc12_vbat>; + }; + + vsus_5v: vsus-5v { + compatible = "regulator-fixed"; + regulator-name = "vsus_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vusb1_5v: vusb1-5v { + compatible = "regulator-fixed"; + regulator-name = "vusb1_5v"; + enable-active-high; + gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* OTG_VBUS_DRV */ + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vsus_5v>; + }; + + vusb2_5v: vusb2-5v { + compatible = "regulator-fixed"; + regulator-name = "vusb2_5v"; + enable-active-high; + gpio = <&gpio8 RK_PB1 GPIO_ACTIVE_HIGH>; /* USB2_PWR_EN */ + pinctrl-names = "default"; + pinctrl-0 = <&usb2_pwr_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vsus_5v>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_tp: LDO_REG1 { + regulator-name = "vcc_tp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_codec: LDO_REG2 { + regulator-name = "vcc_codec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_gps: LDO_REG4 { + regulator-name = "vcc_gps"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc10_lcd: LDO_REG6 { + regulator-name = "vcc10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: SWITCH_REG1 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lan: SWITCH_REG2 { + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&vcc_18>; + bb-supply = <&vcc_io>; + dvp-supply = <&vcc_io>; + flash0-suuply = <&vcc_18>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830 = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + pinctrl-names = "default"; + pinctrl-0 = <&phy_pwr_en>; + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb_host { + phy_pwr_en: phy-pwr-en { + rockchip,pins = <RK_GPIO2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + usb2_pwr_en: usb2-pwr-en { + rockchip,pins = <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <RK_GPIO0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + + }; + }; +}; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 356ed1e62452..cd24894ee5c6 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -972,6 +972,17 @@ status = "disabled"; }; + rga: rga@ff920000 { + compatible = "rockchip,rk3288-rga"; + reg = <0x0 0xff920000 0x0 0x180>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk", "hclk", "sclk"; + power-domains = <&power RK3288_PD_VIO>; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; + reset-names = "core", "axi", "ahb"; + }; + vopb: vop@ff930000 { compatible = "rockchip,rk3288-vop"; reg = <0x0 0xff930000 0x0 0x19c>; @@ -1002,6 +1013,11 @@ reg = <2>; remote-endpoint = <&mipi_in_vopb>; }; + + vopb_out_lvds: endpoint@3 { + reg = <3>; + remote-endpoint = <&lvds_in_vopb>; + }; }; }; @@ -1045,6 +1061,11 @@ reg = <2>; remote-endpoint = <&mipi_in_vopl>; }; + + vopl_out_lvds: endpoint@3 { + reg = <3>; + remote-endpoint = <&lvds_in_vopl>; + }; }; }; @@ -1086,6 +1107,39 @@ }; }; + lvds: lvds@ff96c000 { + compatible = "rockchip,rk3288-lvds"; + reg = <0x0 0xff96c000 0x0 0x4000>; + clocks = <&cru PCLK_LVDS_PHY>; + clock-names = "pclk_lvds"; + pinctrl-names = "lcdc"; + pinctrl-0 = <&lcdc_ctl>; + power-domains = <&power RK3288_PD_VIO>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + lvds_in: port@0 { + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + lvds_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_lvds>; + }; + lvds_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_lvds>; + }; + }; + }; + }; + edp: dp@ff970000 { compatible = "rockchip,rk3288-dp"; reg = <0x0 0xff970000 0x0 0x4000>; @@ -1124,8 +1178,8 @@ reg-io-width = <4>; rockchip,grf = <&grf>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; - clock-names = "iahb", "isfr"; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "cec"; power-domains = <&power RK3288_PD_VIO>; status = "disabled"; @@ -1427,6 +1481,14 @@ }; hdmi { + hdmi_cec_c0: hdmi-cec-c0 { + rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; + }; + + hdmi_cec_c7: hdmi-cec-c7 { + rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>; + }; + hdmi_ddc: hdmi-ddc { rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, <7 20 RK_FUNC_2 &pcfg_pull_none>; @@ -1527,6 +1589,15 @@ }; }; + lcdc { + lcdc_ctl: lcdc-ctl { + rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, + <1 25 RK_FUNC_1 &pcfg_pull_none>, + <1 26 RK_FUNC_1 &pcfg_pull_none>, + <1 27 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_clk: sdmmc-clk { rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 4aa6f60d6a22..49584b6a4195 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -117,6 +117,17 @@ clock-output-names = "xin24m"; }; + gpu: gpu@10090000 { + compatible = "arm,mali-400"; + reg = <0x10090000 0x10000>; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "core", "bus"; + assigned-clocks = <&cru ACLK_GPU>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_GPU>; + status = "disabled"; + }; + L2: l2-cache-controller@10138000 { compatible = "arm,pl310-cache"; reg = <0x10138000 0x1000>; diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts index 86a57f823616..70f0106d1252 100644 --- a/arch/arm/boot/dts/rv1108-evb.dts +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -222,6 +222,10 @@ status = "okay"; }; +&tsadc { + status = "okay"; +}; + &u2phy { status = "okay"; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index e7cd1315db1b..76ea24636feb 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -43,6 +43,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/rv1108-cru.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/thermal/thermal.h> / { #address-cells = <1>; #size-cells = <1>; @@ -70,6 +71,8 @@ compatible = "arm,cortex-a7"; reg = <0xf00>; clocks = <&cru ARMCLK>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <75>; operating-points-v2 = <&cpu_opp_table>; }; }; @@ -329,6 +332,60 @@ status = "disabled"; }; + thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + sustainable-power = <50>; + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + }; + }; + }; + + tsadc: tsadc@10370000 { + compatible = "rockchip,rv1108-tsadc"; + reg = <0x10370000 0x100>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <750000>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + rockchip,hw-tshut-temp = <120000>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + adc: adc@1038c000 { compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; reg = <0x1038c000 0x100>; @@ -740,6 +797,16 @@ }; }; + tsadc { + otp_out: otp-out { + rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; + }; + + otp_gpio: otp-gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index b1a26b42d190..b44e63995583 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -124,7 +124,7 @@ }; }; - ns_sram: sram@00200000 { + ns_sram: sram@200000 { compatible = "mmio-sram"; reg = <0x00200000 0x20000>; }; @@ -135,13 +135,13 @@ #size-cells = <1>; ranges; - nfc_sram: sram@00100000 { + nfc_sram: sram@100000 { compatible = "mmio-sram"; no-memory-wc; reg = <0x00100000 0x2400>; }; - usb0: gadget@00300000 { + usb0: gadget@300000 { #address-cells = <1>; #size-cells = <0>; compatible = "atmel,sama5d3-udc"; @@ -271,7 +271,7 @@ }; }; - usb1: ohci@00400000 { + usb1: ohci@400000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00400000 0x100000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; @@ -280,7 +280,7 @@ status = "disabled"; }; - usb2: ehci@00500000 { + usb2: ehci@500000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00500000 0x100000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; @@ -289,7 +289,7 @@ status = "disabled"; }; - L2: cache-controller@00a00000 { + L2: cache-controller@a00000 { compatible = "arm,pl310-cache"; reg = <0x00a00000 0x1000>; interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 554d0bdedc7a..1889b4dea066 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -79,7 +79,7 @@ }; }; - sram: sram@00300000 { + sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x20000>; }; @@ -1408,7 +1408,7 @@ reg = <0x200000 0x2400>; }; - usb0: gadget@00500000 { + usb0: gadget@500000 { #address-cells = <1>; #size-cells = <0>; compatible = "atmel,sama5d3-udc"; @@ -1525,7 +1525,7 @@ }; }; - usb1: ohci@00600000 { + usb1: ohci@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; @@ -1534,7 +1534,7 @@ status = "disabled"; }; - usb2: ehci@00700000 { + usb2: ehci@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index 6d252ad050f6..7f55050dd405 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -166,14 +166,14 @@ }; }; - usb0: gadget@00500000 { + usb0: gadget@500000 { atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; }; - usb1: ohci@00600000 { + usb1: ohci@600000 { num-ports = <3>; atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH &pioD 26 GPIO_ACTIVE_LOW @@ -182,7 +182,7 @@ status = "okay"; }; - usb2: ehci@00700000 { + usb2: ehci@700000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi index 252e0d35f846..83e3d3e08fd4 100644 --- a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi @@ -253,7 +253,7 @@ }; }; - usb0: gadget@00500000 { + usb0: gadget@500000 { atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 2fa36c525957..b069644ed238 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -113,7 +113,7 @@ }; }; - ns_sram: sram@00210000 { + ns_sram: sram@210000 { compatible = "mmio-sram"; reg = <0x00210000 0x10000>; }; @@ -130,7 +130,7 @@ reg = <0x100000 0x2400>; }; - usb0: gadget@00400000 { + usb0: gadget@400000 { #address-cells = <1>; #size-cells = <0>; compatible = "atmel,sama5d3-udc"; @@ -260,7 +260,7 @@ }; }; - usb1: ohci@00500000 { + usb1: ohci@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; @@ -269,7 +269,7 @@ status = "disabled"; }; - usb2: ehci@00600000 { + usb2: ehci@600000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00600000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; @@ -278,7 +278,7 @@ status = "disabled"; }; - L2: cache-controller@00a00000 { + L2: cache-controller@a00000 { compatible = "arm,pl310-cache"; reg = <0x00a00000 0x1000>; interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 4ea5c5a16c57..88d7e5631d34 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -27,6 +27,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <1196000000>; + clocks = <&cpg_clocks SH73A0_CLK_Z>; power-domains = <&pd_a2sl>; next-level-cache = <&L2>; }; @@ -35,6 +36,7 @@ compatible = "arm,cortex-a9"; reg = <1>; clock-frequency = <1196000000>; + clocks = <&cpg_clocks SH73A0_CLK_Z>; power-domains = <&pd_a2sl>; next-level-cache = <&L2>; }; diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi index 6f720756057d..35e944d8b5c4 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -92,7 +92,7 @@ interrupts = <18 IRQ_TYPE_EDGE_RISING>, <19 IRQ_TYPE_EDGE_RISING>; }; - ak8974@0f { + ak8974@f { /* Magnetometer */ compatible = "asahi-kasei,ak8974"; reg = <0x0f>; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi index 3c9f2f068c2f..0e7d77d719d7 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi @@ -143,7 +143,7 @@ interrupts = <18 IRQ_TYPE_EDGE_RISING>, <19 IRQ_TYPE_EDGE_RISING>; }; - ak8974@0f { + ak8974@f { /* Magnetometer */ compatible = "asahi-kasei,ak8974"; reg = <0x0f>; diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index 34c119a66f14..d0a24d9e517a 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -90,7 +90,7 @@ clock-output-names = "clk-s-icn-reg-0"; }; - clockgen-a@090ff000 { + clockgen-a@90ff000 { compatible = "st,clkgen-c32"; reg = <0x90ff000 0x1000>; @@ -131,7 +131,7 @@ clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ }; - clk_s_c0: clockgen-c@09103000 { + clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -220,7 +220,7 @@ "clk-s-d0-fs0-ch3"; }; - clockgen-d0@09104000 { + clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 12c0757594d7..cf3756976c39 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -72,19 +72,19 @@ }; }; - intc: interrupt-controller@08761000 { + intc: interrupt-controller@8761000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x08761000 0x1000>, <0x08760100 0x100>; }; - scu@08760000 { + scu@8760000 { compatible = "arm,cortex-a9-scu"; reg = <0x08760000 0x1000>; }; - timer@08760200 { + timer@8760200 { interrupt-parent = <&intc>; compatible = "arm,cortex-a9-global-timer"; reg = <0x08760200 0x100>; @@ -555,7 +555,7 @@ status = "disabled"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { compatible = "st,sdhci-stih407", "st,sdhci"; status = "disabled"; reg = <0x09060000 0x7ff>, <0x9061008 0x20>; @@ -570,7 +570,7 @@ bus-width = <8>; }; - mmc1: sdhci@09080000 { + mmc1: sdhci@9080000 { compatible = "st,sdhci-stih407", "st,sdhci"; status = "disabled"; reg = <0x09080000 0x7ff>; @@ -715,14 +715,14 @@ status = "disabled"; }; - rng10: rng@08a89000 { + rng10: rng@8a89000 { compatible = "st,rng"; reg = <0x08a89000 0x1000>; clocks = <&clk_sysin>; status = "okay"; }; - rng11: rng@08a8a000 { + rng11: rng@8a8a000 { compatible = "st,rng"; reg = <0x08a8a000 0x1000>; clocks = <&clk_sysin>; @@ -756,14 +756,14 @@ <&clk_s_c0_flexgen CLK_ETH_PHY>; }; - rng10: rng@08a89000 { + rng10: rng@8a89000 { compatible = "st,rng"; reg = <0x08a89000 0x1000>; clocks = <&clk_sysin>; status = "okay"; }; - rng11: rng@08a8a000 { + rng11: rng@8a8a000 { compatible = "st,rng"; reg = <0x08a8a000 0x1000>; clocks = <&clk_sysin>; diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index bd1a82e8fffe..a29090077fdf 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -56,7 +56,7 @@ interrupt-names = "irqmux"; ranges = <0 0x09610000 0x6000>; - pio0: gpio@09610000 { + pio0: gpio@9610000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -64,7 +64,7 @@ reg = <0x0 0x100>; st,bank-name = "PIO0"; }; - pio1: gpio@09611000 { + pio1: gpio@9611000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -72,7 +72,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO1"; }; - pio2: gpio@09612000 { + pio2: gpio@9612000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -80,7 +80,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO2"; }; - pio3: gpio@09613000 { + pio3: gpio@9613000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -88,7 +88,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO3"; }; - pio4: gpio@09614000 { + pio4: gpio@9614000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -97,7 +97,7 @@ st,bank-name = "PIO4"; }; - pio5: gpio@09615000 { + pio5: gpio@9615000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -380,7 +380,7 @@ interrupt-names = "irqmux"; ranges = <0 0x09200000 0x10000>; - pio10: pio@09200000 { + pio10: pio@9200000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -388,7 +388,7 @@ reg = <0x0 0x100>; st,bank-name = "PIO10"; }; - pio11: pio@09201000 { + pio11: pio@9201000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -396,7 +396,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO11"; }; - pio12: pio@09202000 { + pio12: pio@9202000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -404,7 +404,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO12"; }; - pio13: pio@09203000 { + pio13: pio@9203000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -412,7 +412,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO13"; }; - pio14: pio@09204000 { + pio14: pio@9204000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -420,7 +420,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO14"; }; - pio15: pio@09205000 { + pio15: pio@9205000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -428,7 +428,7 @@ reg = <0x5000 0x100>; st,bank-name = "PIO15"; }; - pio16: pio@09206000 { + pio16: pio@9206000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -436,7 +436,7 @@ reg = <0x6000 0x100>; st,bank-name = "PIO16"; }; - pio17: pio@09207000 { + pio17: pio@9207000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -444,7 +444,7 @@ reg = <0x7000 0x100>; st,bank-name = "PIO17"; }; - pio18: pio@09208000 { + pio18: pio@9208000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -452,7 +452,7 @@ reg = <0x8000 0x100>; st,bank-name = "PIO18"; }; - pio19: pio@09209000 { + pio19: pio@9209000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -940,7 +940,7 @@ interrupt-names = "irqmux"; ranges = <0 0x09210000 0x10000>; - pio20: pio@09210000 { + pio20: pio@9210000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -973,7 +973,7 @@ interrupt-names = "irqmux"; ranges = <0 0x09220000 0x6000>; - pio30: gpio@09220000 { + pio30: gpio@9220000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -981,7 +981,7 @@ reg = <0x0 0x100>; st,bank-name = "PIO30"; }; - pio31: gpio@09221000 { + pio31: gpio@9221000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -989,7 +989,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO31"; }; - pio32: gpio@09222000 { + pio32: gpio@9222000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -997,7 +997,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO32"; }; - pio33: gpio@09223000 { + pio33: gpio@9223000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1005,7 +1005,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO33"; }; - pio34: gpio@09224000 { + pio34: gpio@9224000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1013,7 +1013,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO34"; }; - pio35: gpio@09225000 { + pio35: gpio@9225000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1168,7 +1168,7 @@ interrupt-names = "irqmux"; ranges = <0 0x09230000 0x3000>; - pio40: gpio@09230000 { + pio40: gpio@9230000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1176,7 +1176,7 @@ reg = <0 0x100>; st,bank-name = "PIO40"; }; - pio41: gpio@09231000 { + pio41: gpio@9231000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1184,7 +1184,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO41"; }; - pio42: gpio@09232000 { + pio42: gpio@9232000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts index 83313b51915d..9830be577433 100644 --- a/arch/arm/boot/dts/stih410-b2120.dts +++ b/arch/arm/boot/dts/stih410-b2120.dts @@ -30,7 +30,7 @@ soc { - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { max-frequency = <200000000>; sd-uhs-sdr50; sd-uhs-sdr104; diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts index 93c14d183e29..c663b70c43a7 100644 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -109,14 +109,14 @@ status = "okay"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { pinctrl-0 = <&pinctrl_sd0>; bus-width = <4>; status = "okay"; }; /* high speed expansion connector */ - mmc1: sdhci@09080000 { + mmc1: sdhci@9080000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index 07c8ef9d77f6..fde5df17f575 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -92,7 +92,7 @@ clock-output-names = "clk-s-icn-reg-0"; }; - clockgen-a@090ff000 { + clockgen-a@90ff000 { compatible = "st,clkgen-c32"; reg = <0x90ff000 0x1000>; @@ -134,7 +134,7 @@ clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ }; - clk_s_c0: clockgen-c@09103000 { + clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -230,7 +230,7 @@ "clk-s-d0-fs0-ch3"; }; - clockgen-d0@09104000 { + clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index 21fe72b183d8..cffa50db5d72 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -282,7 +282,7 @@ <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; }; - sti-cec@094a087c { + sti-cec@94a087c { compatible = "st,stih-cec"; reg = <0x94a087c 0x64>; clocks = <&clk_sysin>; diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts index 438e54c585b1..4e6d915c85ff 100644 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ b/arch/arm/boot/dts/stih418-b2199.dts @@ -75,11 +75,11 @@ st,i2c-min-sda-pulse-width-us = <5>; }; - mmc1: sdhci@09080000 { + mmc1: sdhci@9080000 { status = "okay"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { status = "okay"; max-frequency = <200000000>; sd-uhs-sdr50; diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index ee6614b79f7d..9a157c1a99b1 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -92,7 +92,7 @@ clock-output-names = "clk-s-icn-reg-0"; }; - clockgen-a@090ff000 { + clockgen-a@90ff000 { compatible = "st,clkgen-c32"; reg = <0x90ff000 0x1000>; @@ -131,7 +131,7 @@ "clk-s-c0-fs0-ch3"; }; - clk_s_c0: clockgen-c@09103000 { + clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -223,7 +223,7 @@ "clk-s-d0-fs0-ch3"; }; - clockgen-d0@09104000 { + clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi index 965f88160718..e6525ab4d9bb 100644 --- a/arch/arm/boot/dts/stih418.dtsi +++ b/arch/arm/boot/dts/stih418.dtsi @@ -100,7 +100,7 @@ phy-names = "usb"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>; assigned-clock-parents = <&clk_s_c0_pll1 0>; assigned-clock-rates = <200000000>; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index 4b8f62f89664..7f80c2c414c8 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -62,12 +62,12 @@ status = "okay"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { non-removable; status = "okay"; }; - mmc1: sdhci@09080000 { + mmc1: sdhci@9080000 { status = "okay"; }; @@ -102,7 +102,7 @@ fixed-link = <0 1 1000 0 0>; }; - demux@08a20000 { + demux@8a20000 { compatible = "st,stih407-c8sectpfe"; status = "okay"; reg = <0x08a20000 0x10000>, diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index 69a957963fa8..2d4e71717694 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -83,6 +83,13 @@ gpios = <&gpioc 13 0>; }; }; + + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; }; &clk_hse { @@ -93,6 +100,14 @@ status = "okay"; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-names = "default"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + &rtc { status = "okay"; }; @@ -102,3 +117,12 @@ pinctrl-names = "default"; status = "okay"; }; + +&usbotg_hs { + dr_mode = "host"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 7f3560c0211d..ae94d86c53c4 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -40,7 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> +#include <dt-bindings/pinctrl/stm32-pinfunc.h> #include <dt-bindings/mfd/stm32f4-rcc.h> / { @@ -165,35 +165,35 @@ usart1_pins_a: usart1@0 { pins1 { - pinmux = <STM32F429_PA9_FUNC_USART1_TX>; + pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32F429_PA10_FUNC_USART1_RX>; + pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */ bias-disable; }; }; usart3_pins_a: usart3@0 { pins1 { - pinmux = <STM32F429_PB10_FUNC_USART3_TX>; + pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32F429_PB11_FUNC_USART3_RX>; + pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */ bias-disable; }; }; usbotg_fs_pins_a: usbotg_fs@0 { pins { - pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>, - <STM32F429_PA11_FUNC_OTG_FS_DM>, - <STM32F429_PA12_FUNC_OTG_FS_DP>; + pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */ + <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */ + <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */ bias-disable; drive-push-pull; slew-rate = <2>; @@ -202,9 +202,9 @@ usbotg_fs_pins_b: usbotg_fs@1 { pins { - pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>, - <STM32F429_PB14_FUNC_OTG_HS_DM>, - <STM32F429_PB15_FUNC_OTG_HS_DP>; + pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */ + <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */ + <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */ bias-disable; drive-push-pull; slew-rate = <2>; @@ -213,18 +213,18 @@ usbotg_hs_pins_a: usbotg_hs@0 { pins { - pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>, - <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>, - <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>, - <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>, - <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>, - <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>, - <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>, - <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>, - <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>, - <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>, - <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>, - <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>; + pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/ + <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */ + <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */ + <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */ + <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */ + <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */ + <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */ + <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */ + <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */ + <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */ + <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */ + <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */ bias-disable; drive-push-pull; slew-rate = <2>; @@ -233,49 +233,49 @@ ethernet_mii: mii@0 { pins { - pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, - <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, - <STM32F429_PC2_FUNC_ETH_MII_TXD2>, - <STM32F429_PB8_FUNC_ETH_MII_TXD3>, - <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>, - <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, - <STM32F429_PA2_FUNC_ETH_MDIO>, - <STM32F429_PC1_FUNC_ETH_MDC>, - <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, - <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, - <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, - <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>, - <STM32F429_PH6_FUNC_ETH_MII_RXD2>, - <STM32F429_PH7_FUNC_ETH_MII_RXD3>; + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */ + <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */ + <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */ + <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ + <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */ + <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */ + <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */ + <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */ slew-rate = <2>; }; }; adc3_in8_pin: adc@200 { pins { - pinmux = <STM32F429_PF10_FUNC_ANALOG>; + pinmux = <STM32_PINMUX('F', 10, ANALOG)>; }; }; pwm1_pins: pwm@1 { pins { - pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>, - <STM32F429_PB13_FUNC_TIM1_CH1N>, - <STM32F429_PB12_FUNC_TIM1_BKIN>; + pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */ + <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */ + <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */ }; }; pwm3_pins: pwm@3 { pins { - pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>, - <STM32F429_PB5_FUNC_TIM3_CH2>; + pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */ + <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ }; }; i2c1_pins: i2c1@0 { pins { - pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>, - <STM32F429_PB6_FUNC_I2C1_SCL>; + pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */ + <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */ bias-disable; drive-open-drain; slew-rate = <3>; @@ -284,55 +284,55 @@ ltdc_pins: ltdc@0 { pins { - pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>, - <STM32F429_PI13_FUNC_LCD_VSYNC>, - <STM32F429_PI14_FUNC_LCD_CLK>, - <STM32F429_PI15_FUNC_LCD_R0>, - <STM32F429_PJ0_FUNC_LCD_R1>, - <STM32F429_PJ1_FUNC_LCD_R2>, - <STM32F429_PJ2_FUNC_LCD_R3>, - <STM32F429_PJ3_FUNC_LCD_R4>, - <STM32F429_PJ4_FUNC_LCD_R5>, - <STM32F429_PJ5_FUNC_LCD_R6>, - <STM32F429_PJ6_FUNC_LCD_R7>, - <STM32F429_PJ7_FUNC_LCD_G0>, - <STM32F429_PJ8_FUNC_LCD_G1>, - <STM32F429_PJ9_FUNC_LCD_G2>, - <STM32F429_PJ10_FUNC_LCD_G3>, - <STM32F429_PJ11_FUNC_LCD_G4>, - <STM32F429_PJ12_FUNC_LCD_B0>, - <STM32F429_PJ13_FUNC_LCD_B1>, - <STM32F429_PJ14_FUNC_LCD_B2>, - <STM32F429_PJ15_FUNC_LCD_B3>, - <STM32F429_PK0_FUNC_LCD_G5>, - <STM32F429_PK1_FUNC_LCD_G6>, - <STM32F429_PK2_FUNC_LCD_G7>, - <STM32F429_PK3_FUNC_LCD_B4>, - <STM32F429_PK4_FUNC_LCD_B5>, - <STM32F429_PK5_FUNC_LCD_B6>, - <STM32F429_PK6_FUNC_LCD_B7>, - <STM32F429_PK7_FUNC_LCD_DE>; + pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ + <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ + <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ + <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ + <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ + <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ + <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ + <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ + <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/ + <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ + <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ + <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ + <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ + <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ + <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ + <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ + <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ + <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ + <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/ + <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ + <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ + <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ + <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ + <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ + <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ + <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */ + <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */ slew-rate = <2>; }; }; dcmi_pins: dcmi@0 { pins { - pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>, - <STM32F429_PB7_FUNC_DCMI_VSYNC>, - <STM32F429_PA6_FUNC_DCMI_PIXCLK>, - <STM32F429_PC6_FUNC_DCMI_D0>, - <STM32F429_PC7_FUNC_DCMI_D1>, - <STM32F429_PC8_FUNC_DCMI_D2>, - <STM32F429_PC9_FUNC_DCMI_D3>, - <STM32F429_PC11_FUNC_DCMI_D4>, - <STM32F429_PD3_FUNC_DCMI_D5>, - <STM32F429_PB8_FUNC_DCMI_D6>, - <STM32F429_PE6_FUNC_DCMI_D7>, - <STM32F429_PC10_FUNC_DCMI_D8>, - <STM32F429_PC12_FUNC_DCMI_D9>, - <STM32F429_PD6_FUNC_DCMI_D10>, - <STM32F429_PD2_FUNC_DCMI_D11>; + pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */ + <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */ + <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */ + <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */ + <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */ + <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */ + <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */ + <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */ + <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */ + <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */ + <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */ + <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */ + <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */ bias-disable; drive-push-pull; slew-rate = <3>; diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts index 18f656074437..4d85dba59e1d 100644 --- a/arch/arm/boot/dts/stm32f746-disco.dts +++ b/arch/arm/boot/dts/stm32f746-disco.dts @@ -61,6 +61,20 @@ serial0 = &usart1; }; + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + /* This turns on vbus for otg fs for host mode (dwc2) */ + vcc5v_otg_fs: vcc5v-otg-fs-regulator { + compatible = "regulator-fixed"; + gpio = <&gpiod 5 0>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; }; &clk_hse { @@ -72,3 +86,19 @@ pinctrl-names = "default"; status = "okay"; }; + +&usbotg_fs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "host"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 5f9417894059..5f66d151eedb 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -42,7 +42,7 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" -#include <dt-bindings/pinctrl/stm32f746-pinfunc.h> +#include <dt-bindings/pinctrl/stm32-pinfunc.h> #include <dt-bindings/clock/stm32fx-clock.h> #include <dt-bindings/mfd/stm32f7-rcc.h> @@ -82,6 +82,27 @@ status = "disabled"; }; + timers2: timers@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + }; + timer3: timer@40000400 { compatible = "st,stm32-timer"; reg = <0x40000400 0x400>; @@ -90,6 +111,27 @@ status = "disabled"; }; + timers3: timers@40000400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000400 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + timer4: timer@40000800 { compatible = "st,stm32-timer"; reg = <0x40000800 0x400>; @@ -98,6 +140,27 @@ status = "disabled"; }; + timers4: timers@40000800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000800 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + }; + timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; @@ -105,6 +168,27 @@ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; + timers5: timers@40000c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000C00 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + }; + timer6: timer@40001000 { compatible = "st,stm32-timer"; reg = <0x40001000 0x400>; @@ -113,6 +197,22 @@ status = "disabled"; }; + timers6: timers@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; + clock-names = "int"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + timer7: timer@40001400 { compatible = "st,stm32-timer"; reg = <0x40001400 0x400>; @@ -121,6 +221,73 @@ status = "disabled"; }; + timers7: timers@40001400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001400 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; + clock-names = "int"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + timers12: timers@40001800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001800 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timers@40001c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001C00 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + + timers14: timers@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; @@ -167,6 +334,18 @@ status = "disabled"; }; + i2c1: i2c@40005400 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc STM32F7_APB1_RESET(I2C1)>; + clocks = <&rcc 1 CLK_I2C1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cec: cec@40006c00 { compatible = "st,stm32-cec"; reg = <0x40006C00 0x400>; @@ -192,6 +371,48 @@ status = "disabled"; }; + timers1: timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + }; + + timers8: timers@40010400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010400 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + }; + usart1: serial@40011000 { compatible = "st,stm32f7-uart"; reg = <0x40011000 0x400>; @@ -221,6 +442,57 @@ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; }; + timers9: timers@40014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014000 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@8 { + compatible = "st,stm32-timer-trigger"; + reg = <8>; + status = "disabled"; + }; + }; + + timers10: timers@40014400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014400 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + + timers11: timers@40014800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014800 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + pwrcfg: power-config@40007000 { compatible = "syscon"; reg = <0x40007000 0x400>; @@ -347,7 +619,7 @@ cec_pins_a: cec@0 { pins { - pinmux = <STM32F746_PA15_FUNC_HDMI_CEC>; + pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */ slew-rate = <0>; drive-open-drain; bias-disable; @@ -356,27 +628,88 @@ usart1_pins_a: usart1@0 { pins1 { - pinmux = <STM32F746_PA9_FUNC_USART1_TX>; + pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32F746_PA10_FUNC_USART1_RX>; + pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */ bias-disable; }; }; usart1_pins_b: usart1@1 { pins1 { - pinmux = <STM32F746_PA9_FUNC_USART1_TX>; + pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32F746_PB7_FUNC_USART1_RX>; + pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */ + bias-disable; + }; + }; + + i2c1_pins_b: i2c1@0 { + pins { + pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */ + <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + usbotg_hs_pins_a: usbotg-hs@0 { + pins { + pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */ + <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */ + <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */ + <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */ + <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */ + <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */ + <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */ + <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */ + <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */ + <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */ + <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */ + <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_hs_pins_b: usbotg-hs@1 { + pins { + pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */ + <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */ + <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */ + <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */ + <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */ + <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */ + <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */ + <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */ + <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */ + <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */ + <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */ + <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_fs_pins_a: usbotg-fs@0 { + pins { + pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */ + <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */ + <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */ bias-disable; + drive-push-pull; + slew-rate = <2>; }; }; }; @@ -431,6 +764,24 @@ st,mem2mem; status = "disabled"; }; + + usbotg_hs: usb@40040000 { + compatible = "st,stm32f7-hsotg"; + reg = <0x40040000 0x40000>; + interrupts = <77>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; + clock-names = "otg"; + status = "disabled"; + }; + + usbotg_fs: usb@50000000 { + compatible = "st,stm32f4x9-fsotg"; + reg = <0x50000000 0x40000>; + interrupts = <67>; + clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; + clock-names = "otg"; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi index 76bbd6575fae..65c1cd043987 100644 --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi @@ -40,7 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <dt-bindings/pinctrl/stm32h7-pinfunc.h> +#include <dt-bindings/pinctrl/stm32-pinfunc.h> / { soc { @@ -55,7 +55,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x0 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOA_CK>; st,bank-name = "GPIOA"; }; @@ -63,7 +63,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOB_CK>; st,bank-name = "GPIOB"; }; @@ -71,7 +71,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x800 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOC_CK>; st,bank-name = "GPIOC"; }; @@ -79,7 +79,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0xc00 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOD_CK>; st,bank-name = "GPIOD"; }; @@ -87,7 +87,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x1000 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOE_CK>; st,bank-name = "GPIOE"; }; @@ -95,7 +95,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x1400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOF_CK>; st,bank-name = "GPIOF"; }; @@ -103,7 +103,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x1800 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOG_CK>; st,bank-name = "GPIOG"; }; @@ -111,7 +111,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x1c00 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOH_CK>; st,bank-name = "GPIOH"; }; @@ -119,7 +119,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x2000 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOI_CK>; st,bank-name = "GPIOI"; }; @@ -127,7 +127,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x2400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOJ_CK>; st,bank-name = "GPIOJ"; }; @@ -135,32 +135,32 @@ gpio-controller; #gpio-cells = <2>; reg = <0x2800 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOK_CK>; st,bank-name = "GPIOK"; }; usart1_pins: usart1@0 { pins1 { - pinmux = <STM32H7_PB14_FUNC_USART1_TX>; + pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32H7_PB15_FUNC_USART1_RX>; + pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */ bias-disable; }; }; usart2_pins: usart2@0 { pins1 { - pinmux = <STM32H7_PD5_FUNC_USART2_TX>; + pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32H7_PD6_FUNC_USART2_RX>; + pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ bias-disable; }; }; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 26de31578701..bbfcbaca0b36 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -42,6 +42,8 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" +#include <dt-bindings/clock/stm32h7-clks.h> +#include <dt-bindings/mfd/stm32h7-rcc.h> / { clocks { @@ -51,10 +53,16 @@ clock-frequency = <0>; }; - timer_clk: timer-clk { + clk_lse: clk-lse { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <125000000>; + clock-frequency = <32768>; + }; + + clk_i2s: i2s_ckin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; }; }; @@ -63,7 +71,33 @@ compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; - clocks = <&timer_clk>; + clocks = <&rcc TIM5_CK>; + }; + + lptimer1: timer@40002400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40002400 0x400>; + clocks = <&rcc LPTIM1_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; }; usart2: serial@40004400 { @@ -71,13 +105,13 @@ reg = <0x40004400 0x400>; interrupts = <38>; status = "disabled"; - clocks = <&timer_clk>; + clocks = <&rcc USART2_CK>; }; dac: dac@40007400 { compatible = "st,stm32h7-dac-core"; reg = <0x40007400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc DAC12_CK>; clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; @@ -103,8 +137,7 @@ reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; - clocks = <&timer_clk>; - + clocks = <&rcc USART1_CK>; }; dma1: dma@40020000 { @@ -118,9 +151,10 @@ <16>, <17>, <47>; - clocks = <&timer_clk>; + clocks = <&rcc DMA1_CK>; #dma-cells = <4>; st,mem2mem; + dma-requests = <8>; status = "disabled"; }; @@ -135,17 +169,28 @@ <68>, <69>, <70>; - clocks = <&timer_clk>; + clocks = <&rcc DMA2_CK>; #dma-cells = <4>; st,mem2mem; + dma-requests = <8>; status = "disabled"; }; + dmamux1: dma-router@40020800 { + compatible = "st,stm32h7-dmamux"; + reg = <0x40020800 0x1c>; + #dma-cells = <3>; + dma-channels = <16>; + dma-requests = <128>; + dma-masters = <&dma1 &dma2>; + clocks = <&rcc DMA1_CK>; + }; + adc_12: adc@40022000 { compatible = "st,stm32h7-adc-core"; reg = <0x40022000 0x400>; interrupts = <18>; - clocks = <&timer_clk>; + clocks = <&rcc ADC12_CK>; clock-names = "bus"; interrupt-controller; #interrupt-cells = <1>; @@ -172,11 +217,121 @@ }; }; + mdma1: dma@52000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x52000000 0x1000>; + interrupts = <122>; + clocks = <&rcc MDMA_CK>; + #dma-cells = <5>; + dma-channels = <16>; + dma-requests = <32>; + }; + + lptimer2: timer@58002400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002400 0x400>; + clocks = <&rcc LPTIM2_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + + lptimer3: timer@58002800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002800 0x400>; + clocks = <&rcc LPTIM3_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + lptimer4: timer@58002c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002c00 0x400>; + clocks = <&rcc LPTIM4_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + }; + + lptimer5: timer@58003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58003000 0x400>; + clocks = <&rcc LPTIM5_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + }; + + vrefbuf: regulator@58003C00 { + compatible = "st,stm32-vrefbuf"; + reg = <0x58003C00 0x8>; + clocks = <&rcc VREF_CK>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + status = "disabled"; + }; + + rcc: reset-clock-controller@58024400 { + compatible = "st,stm32h743-rcc", "st,stm32-rcc"; + reg = <0x58024400 0x400>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; + st,syscfg = <&pwrcfg>; + }; + + pwrcfg: power-config@58024800 { + compatible = "syscon"; + reg = <0x58024800 0x400>; + }; + adc_3: adc@58026000 { compatible = "st,stm32h7-adc-core"; reg = <0x58026000 0x400>; interrupts = <127>; - clocks = <&timer_clk>; + clocks = <&rcc ADC3_CK>; clock-names = "bus"; interrupt-controller; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts index 6c07786e7ddb..9f0e72c67219 100644 --- a/arch/arm/boot/dts/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/stm32h743i-eval.dts @@ -81,7 +81,7 @@ }; &clk_hse { - clock-frequency = <125000000>; + clock-frequency = <25000000>; }; &usart1 { diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index f80d37ddc4c6..09e909576c61 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -62,8 +62,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a1000>; red { label = "a1000:red:usr"; @@ -79,8 +77,6 @@ reg_emac_3v3: emac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&emac_power_pin_a1000>; regulator-name = "emac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -129,8 +125,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -140,8 +134,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -156,7 +148,7 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -170,8 +162,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -187,18 +177,6 @@ status = "okay"; }; -&pio { - emac_power_pin_a1000: emac_power_pin@0 { - pins = "PH15"; - function = "gpio_out"; - }; - - led_pins_a1000: led_pins@0 { - pins = "PH10", "PH20"; - function = "gpio_out"; - }; -}; - #include "axp209.dtsi" ®_dcdc2 { @@ -236,13 +214,13 @@ &spdif { pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pins_a>; + pinctrl-0 = <&spdif_tx_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts index 6b02de592a02..39ba4ccb9e2e 100644 --- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts +++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts @@ -68,8 +68,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -79,8 +77,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -95,7 +91,7 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -108,8 +104,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -125,12 +119,6 @@ status = "okay"; }; -&pio { - usb2_vbus_pin_a: usb2_vbus_pin@0 { - pins = "PH12"; - }; -}; - ®_usb0_vbus { regulator-boot-on; status = "okay"; @@ -147,7 +135,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts index a7d61994b8fd..dfc88aee4fe3 100644 --- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts @@ -65,8 +65,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -80,14 +78,10 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5306de4: touchscreen@38 { @@ -104,21 +98,21 @@ vref-supply = <®_vcc3v0>; status = "okay"; - button@800 { + button-800 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <800000>; }; - button@1000 { + button-1000 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <1000000>; }; - button@1200 { + button-1200 { label = "Back"; linux,code = <KEY_BACK>; channel = <0>; @@ -127,8 +121,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -141,13 +133,13 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -164,7 +156,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 404ce7694899..1982c8c238c5 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -59,6 +59,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -90,6 +101,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -99,8 +114,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -109,9 +122,17 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -121,14 +142,12 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -141,8 +160,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -163,13 +180,13 @@ }; &pio { - led_pins_cubieboard: led_pins@0 { + led_pins_cubieboard: led-pins { pins = "PH20", "PH21"; function = "gpio_out"; drive-strength = <20>; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; @@ -221,14 +238,14 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts index e0777ae808c7..147cbc5e08ac 100644 --- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts +++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts @@ -58,8 +58,6 @@ backlight: backlight { compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_dsrv9703c>; pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; @@ -77,10 +75,8 @@ max-microvolt = <3000000>; }; - reg_motor: reg_motor { + reg_motor: reg-motor { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&motor_pins>; regulator-name = "vcc-motor"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; @@ -90,8 +86,6 @@ }; &codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ status = "okay"; }; @@ -105,8 +99,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -118,15 +110,11 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; /* pull-ups and devices require AXP209 LDO3 */ status = "failed"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5406ee8: touchscreen@38 { @@ -134,8 +122,6 @@ reg = <0x38>; interrupt-parent = <&pio>; interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_pins>; reset-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; touchscreen-size-x = <1024>; touchscreen-size-y = <768>; @@ -146,14 +132,14 @@ vref-supply = <®_ldo2>; status = "okay"; - button@400 { + button-400 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <400000>; }; - button@800 { + button-800 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; @@ -162,8 +148,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -176,33 +160,13 @@ }; &pio { - bl_en_pin_dsrv9703c: bl_en_pin@0 { - pins = "PH7"; - function = "gpio_out"; - }; - - codec_pa_pin: codec_pa_pin@0 { - pins = "PH15"; - function = "gpio_out"; - }; - - motor_pins: motor_pins@0 { - pins = "PB3"; - function = "gpio_out"; - }; - - touchscreen_pins: touchscreen_pins@0 { - pins = "PB13"; - function = "gpio_out"; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -211,7 +175,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; @@ -250,7 +214,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts index d8bfd7b74916..41ca8bded89f 100644 --- a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts +++ b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts @@ -72,8 +72,6 @@ */ &codec { /* PH15 controls power to external amplifier (ft2012q) */ - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -91,8 +89,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -104,8 +100,6 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; /* Accelerometer */ @@ -122,21 +116,21 @@ status = "okay"; - button@158 { + button-158 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <158730>; }; - button@349 { + button-349 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <349206>; }; - button@1142 { + button-1142 { label = "Esc"; linux,code = <KEY_ESC>; channel = <0>; @@ -145,8 +139,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */ @@ -154,13 +146,6 @@ status = "okay"; }; -&pio { - codec_pa_pin: codec_pa_pin@0 { - pins = "PH15"; - function = "gpio_out"; - }; -}; - ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -197,7 +182,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index 856cfc9128e6..f33e42d6ce8b 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -80,8 +80,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy0>; status = "okay"; }; @@ -92,7 +90,7 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -106,8 +104,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -123,27 +119,11 @@ status = "okay"; }; -&pio { - pinctrl-names = "default"; - pinctrl-0 = <&hackberry_hogs>; - - hackberry_hogs: hogs@0 { - pins = "PH19"; - function = "gpio_out"; - }; - - usb2_vbus_pin_hackberry: usb2_vbus_pin@0 { - pins = "PH12"; - function = "gpio_out"; - }; -}; - ®_usb1_vbus { status = "okay"; }; ®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_hackberry>; gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -156,6 +136,6 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts index 6506595268b2..35c57d065dd8 100644 --- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts +++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts @@ -63,8 +63,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -78,8 +76,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -92,13 +88,13 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -116,7 +112,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts index d51d8c302daf..9482e831a9a1 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet1.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts @@ -58,8 +58,6 @@ backlight: backlight { compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_inet>; pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; @@ -88,8 +86,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -101,8 +97,6 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; /* Accelerometer */ @@ -115,8 +109,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5x: touchscreen@38 { @@ -124,8 +116,6 @@ reg = <0x38>; interrupt-parent = <&pio>; interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_wake_pin>; wake-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* PB13 */ touchscreen-size-x = <600>; touchscreen-size-y = <1024>; @@ -137,21 +127,21 @@ vref-supply = <®_ldo2>; status = "okay"; - button@200 { + button-200 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <200000>; }; - button@1000 { + button-1000 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <1000000>; }; - button@1200 { + button-1200 { label = "Home"; linux,code = <KEY_HOMEPAGE>; channel = <0>; @@ -160,8 +150,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -178,23 +166,13 @@ }; &pio { - bl_en_pin_inet: bl_en_pin@0 { - pins = "PH7"; - function = "gpio_out"; - }; - - touchscreen_wake_pin: touchscreen_wake_pin@0 { - pins = "PB13"; - function = "gpio_out"; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -203,7 +181,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; @@ -246,7 +224,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index a8e479fe43ca..4b5c91c8e85b 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -72,8 +72,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -85,14 +83,10 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5406ee8: touchscreen@38 { @@ -109,35 +103,35 @@ vref-supply = <®_ldo2>; status = "okay"; - button@200 { + button-200 { label = "Menu"; linux,code = <KEY_MENU>; channel = <0>; voltage = <200000>; }; - button@600 { + button-600 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <600000>; }; - button@800 { + button-800 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <800000>; }; - button@1000 { + button-1000 { label = "Home"; linux,code = <KEY_HOMEPAGE>; channel = <0>; voltage = <1000000>; }; - button@1200 { + button-1200 { label = "Esc"; linux,code = <KEY_ESC>; channel = <0>; @@ -146,8 +140,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -160,13 +152,13 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -208,7 +200,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts index 2acb89a87d41..13224f5ac166 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts @@ -59,7 +59,7 @@ stdout-path = "serial0:115200n8"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys-polled"; pinctrl-names = "default"; pinctrl-0 = <&key_pins_inet9f>; @@ -67,7 +67,7 @@ #size-cells = <0>; poll-interval = <20>; - button@0 { + left-joystick-left { label = "Left Joystick Left"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -75,7 +75,7 @@ gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */ }; - button@1 { + left-joystick-right { label = "Left Joystick Right"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -83,7 +83,7 @@ gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */ }; - button@2 { + left-joystick-up { label = "Left Joystick Up"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -91,7 +91,7 @@ gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ }; - button@3 { + left-joystick-down { label = "Left Joystick Down"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -99,7 +99,7 @@ gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ }; - button@4 { + right-joystick-left { label = "Right Joystick Left"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -107,7 +107,7 @@ gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */ }; - button@5 { + right-joystick-right { label = "Right Joystick Right"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -115,7 +115,7 @@ gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */ }; - button@6 { + right-joystick-up { label = "Right Joystick Up"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -123,7 +123,7 @@ gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */ }; - button@7 { + right-joystick-down { label = "Right Joystick Down"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -131,7 +131,7 @@ gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ }; - button@8 { + dpad-left { label = "DPad Left"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -139,7 +139,7 @@ gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */ }; - button@9 { + dpad-right { label = "DPad Right"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -147,7 +147,7 @@ gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */ }; - button@10 { + dpad-up { label = "DPad Up"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -155,7 +155,7 @@ gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */ }; - button@11 { + dpad-down { label = "DPad Down"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -163,49 +163,49 @@ gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ }; - button@12 { + x { label = "Button X"; linux,code = <BTN_X>; gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */ }; - button@13 { + y { label = "Button Y"; linux,code = <BTN_Y>; gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */ }; - button@14 { + a { label = "Button A"; linux,code = <BTN_A>; gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ }; - button@15 { + b { label = "Button B"; linux,code = <BTN_B>; gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */ }; - button@16 { + select { label = "Select Button"; linux,code = <BTN_SELECT>; gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */ }; - button@17 { + start { label = "Start Button"; linux,code = <BTN_START>; gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */ }; - button@18 { + top-left { label = "Top Left Button"; linux,code = <BTN_TL>; gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ }; - button@19 { + top-right { label = "Top Right Button"; linux,code = <BTN_TR>; gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */ @@ -222,8 +222,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -235,8 +233,6 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; /* Accelerometer */ @@ -249,8 +245,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5406ee8: touchscreen@38 { @@ -267,35 +261,35 @@ vref-supply = <®_ldo2>; status = "okay"; - button@200 { + button-200 { label = "Menu"; linux,code = <KEY_MENU>; channel = <0>; voltage = <200000>; }; - button@600 { + button-600 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <600000>; }; - button@800 { + button-800 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <800000>; }; - button@1000 { + button-1000 { label = "Home"; linux,code = <KEY_HOMEPAGE>; channel = <0>; voltage = <1000000>; }; - button@1200 { + button-1200 { label = "Esc"; linux,code = <KEY_ESC>; channel = <0>; @@ -304,8 +298,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -318,7 +310,7 @@ }; &pio { - key_pins_inet9f: key_pins@0 { + key_pins_inet9f: key-pins { pins = "PA0", "PA1", "PA3", "PA4", "PA5", "PA6", "PA8", "PA9", "PA11", "PA12", "PA13", @@ -328,13 +320,13 @@ bias-pull-up; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -376,7 +368,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts index 92e3e030ced3..d22bd79562d8 100644 --- a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts +++ b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts @@ -57,7 +57,7 @@ &emac { pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; + pinctrl-0 = <&emac_pins>; phy = <&phy1>; status = "okay"; }; @@ -67,6 +67,9 @@ }; &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + axp209: pmic@34 { interrupts = <0>; }; @@ -74,19 +77,19 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -100,7 +103,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -114,7 +117,11 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>; status = "okay"; }; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; +}; diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts index 92b2d4af3d21..879141ca6027 100644 --- a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts +++ b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts @@ -62,8 +62,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_q5>; green { label = "q5:green:usr"; @@ -74,8 +72,6 @@ reg_emac_3v3: emac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&emac_power_pin_q5>; regulator-name = "emac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -98,8 +94,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -109,8 +103,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -125,7 +117,7 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -139,8 +131,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -160,18 +150,6 @@ status = "okay"; }; -&pio { - emac_power_pin_q5: emac_power_pin@0 { - pins = "PH19"; - function = "gpio_out"; - }; - - led_pins_q5: led_pins@0 { - pins = "PH20"; - function = "gpio_out"; - }; -}; - ®_usb0_vbus { regulator-boot-on; status = "okay"; @@ -187,7 +165,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts index 0f927da28ee1..435c551aef0f 100644 --- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts @@ -61,8 +61,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_marsboard>; red1 { label = "marsboard:red1:usr"; @@ -107,27 +105,19 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; }; @@ -140,8 +130,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -162,12 +150,7 @@ }; &pio { - led_pins_marsboard: led_pins@0 { - pins = "PB5", "PB6", "PB7", "PB8"; - function = "gpio_out"; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; @@ -184,14 +167,14 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index a5ed9e4e22c6..1b639e5f9172 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -70,8 +70,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -86,18 +84,16 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; -&ir0_rx_pins_a { +&ir0_rx_pins { /* The ir receiver is not always populated */ bias-pull-up; }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -132,7 +128,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts b/arch/arm/boot/dts/sun4i-a10-mk802.dts index 81db6824a2c7..7198b34e2e50 100644 --- a/arch/arm/boot/dts/sun4i-a10-mk802.dts +++ b/arch/arm/boot/dts/sun4i-a10-mk802.dts @@ -71,8 +71,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -88,23 +86,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - pins = "PH4"; - function = "gpio_in"; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - pins = "PH5"; - function = "gpio_in"; - }; - - usb2_vbus_pin_mk802: usb2_vbus_pin@0 { - pins = "PH12"; - function = "gpio_out"; - }; -}; - ®_usb0_vbus { status = "okay"; }; @@ -114,14 +95,13 @@ }; ®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_mk802>; gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; @@ -131,8 +111,6 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts index e74a881fd9a7..e460da2eb139 100644 --- a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts +++ b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts @@ -67,8 +67,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -82,8 +80,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -105,7 +101,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index 462412ee903c..49247fbe6acd 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -58,6 +58,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -89,6 +100,10 @@ cooling-max-level = <2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -98,8 +113,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -108,9 +121,17 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -124,8 +145,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; eeprom: eeprom@50 { @@ -144,8 +163,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -166,24 +183,19 @@ }; &pio { - ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { - pins = "PC3"; - function = "gpio_out"; - }; - - led_pins_olinuxinolime: led_pins@0 { + led_pins_olinuxinolime: led-pin { pins = "PH2"; function = "gpio_out"; drive-strength = <20>; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -191,7 +203,6 @@ }; ®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -210,7 +221,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index 84f55e76df0c..6e140547b638 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -62,8 +62,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_pcduino>; tx { label = "pcduino:green:tx"; @@ -76,26 +74,24 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_pcduino>; #address-cells = <1>; #size-cells = <0>; - button@0 { + back { label = "Key Back"; linux,code = <KEY_BACK>; gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; }; - button@1 { + home { label = "Key Home"; linux,code = <KEY_HOME>; gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; }; - button@2 { + menu { label = "Key Menu"; linux,code = <KEY_MENU>; gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; @@ -116,8 +112,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -127,8 +121,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -146,8 +138,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -168,17 +158,7 @@ }; &pio { - led_pins_pcduino: led_pins@0 { - pins = "PH15", "PH16"; - function = "gpio_out"; - }; - - key_pins_pcduino: key_pins@0 { - pins = "PH17", "PH18", "PH19"; - function = "gpio_in"; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; @@ -214,7 +194,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino2.dts b/arch/arm/boot/dts/sun4i-a10-pcduino2.dts index 811d00ee2ade..bc4f128965ed 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino2.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino2.dts @@ -55,16 +55,7 @@ compatible = "linksprite,a10-pcduino2", "allwinner,sun4i-a10"; }; -&pio { - usb2_vbus_pin_pcduino2: usb2_vbus_pin@0 { - pins = "PD2"; - function = "gpio_out"; - }; -}; - ®_usb2_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_pin_pcduino2>; gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts index c0f8c88b5a7d..5081303f79e7 100644 --- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts @@ -58,8 +58,6 @@ backlight: backlight { compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_protab>; pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; @@ -72,8 +70,6 @@ }; &codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ status = "okay"; }; @@ -87,8 +83,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -100,20 +94,14 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; /* pull-ups and devices require AXP209 LDO3 */ status = "failed"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; - pixcir_ts@5c { - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_pins>; + touchscreen@5c { compatible = "pixcir,pixcir_tangoc"; reg = <0x5c>; interrupt-parent = <&pio>; @@ -132,14 +120,14 @@ vref-supply = <®_ldo2>; status = "okay"; - button@400 { + button-400 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <400000>; }; - button@800 { + button-800 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; @@ -148,8 +136,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ @@ -162,28 +148,13 @@ }; &pio { - bl_en_pin_protab: bl_en_pin@0 { - pins = "PH7"; - function = "gpio_out"; - }; - - codec_pa_pin: codec_pa_pin@0 { - pins = "PH15"; - function = "gpio_out"; - }; - - touchscreen_pins: touchscreen_pins@0 { - pins = "PA5", "PB13"; - function = "gpio_out"; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; @@ -192,7 +163,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; @@ -231,7 +202,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 41c2579143fd..b91300d49a31 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -41,14 +41,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" - #include <dt-bindings/thermal/thermal.h> - -#include <dt-bindings/clock/sun4i-a10-pll2.h> #include <dt-bindings/dma/sun4i-a10.h> +#include <dt-bindings/clock/sun4i-a10-ccu.h> +#include <dt-bindings/reset/sun4i-a10-ccu.h> / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&intc>; aliases { @@ -60,46 +60,48 @@ #size-cells = <1>; ranges; - framebuffer@0 { + framebuffer-lcd0-hdmi { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&de_be0_clk>, - <&tcon0_ch1_clk>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; - framebuffer@1 { + framebuffer-fe0-lcd0-hdmi { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>, - <&dram_gates 25>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>, + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; - framebuffer@2 { + framebuffer-fe0-lcd0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0"; - clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, - <&dram_gates 25>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_TCON0_CH0>, + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; - framebuffer@3 { + framebuffer-fe0-lcd0-tve0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; - clocks = <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, - <&tcon0_ch1_clk>, <&dram_gates 5>, - <&dram_gates 25>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; }; @@ -111,7 +113,7 @@ device_type = "cpu"; compatible = "arm,cortex-a8"; reg = <0x0>; - clocks = <&cpu>; + clocks = <&ccu CLK_CPU>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < /* kHz uV */ @@ -127,7 +129,7 @@ }; thermal-zones { - cpu_thermal { + cpu-thermal { /* milliseconds */ polling-delay-passive = <250>; polling-delay = <1000>; @@ -141,14 +143,14 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <850000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <100000>; hysteresis = <2000>; @@ -158,532 +160,46 @@ }; }; - memory { - reg = <0x40000000 0x80000000>; - }; - clocks { #address-cells = <1>; #size-cells = <1>; ranges; - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { + osc24M: clk-24M { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - osc24M: clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; - osc3M: osc3M_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc3M"; - }; - - osc32k: clk@0 { + osc32k: clk-32k { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; clock-output-names = "osc32k"; }; + }; - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll2: clk@01c20008 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll2-clk"; - reg = <0x01c20008 0x8>; - clocks = <&osc24M>; - clock-output-names = "pll2-1x", "pll2-2x", - "pll2-4x", "pll2-8x"; - }; - - pll3: clk@01c20010 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll3"; - }; - - pll3x2: pll3x2_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll3>; - clock-output-names = "pll3-2x"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6"; - }; - - pll7: clk@01c20030 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll7"; - }; - - pll7x2: pll7x2_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll7>; - clock-output-names = "pll7-2x"; - }; - - /* dummy is 200M */ - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - axi_gates: clk@01c2005c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-axi-gates-clk"; - reg = <0x01c2005c 0x4>; - clocks = <&axi>; - clock-indices = <0>; - clock-output-names = "axi_dram"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>; - clock-output-names = "ahb"; - }; - - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <3>, - <4>, <5>, <6>, - <7>, <8>, <9>, - <10>, <11>, <12>, - <13>, <14>, <16>, - <17>, <18>, <20>, - <21>, <22>, <23>, - <24>, <25>, <26>, - <32>, <33>, <34>, - <35>, <36>, <37>, - <40>, <41>, <43>, - <44>, <45>, - <46>, <47>, - <50>, <52>; - clock-output-names = "ahb_usb0", "ahb_ehci0", - "ahb_ohci0", "ahb_ehci1", - "ahb_ohci1", "ahb_ss", "ahb_dma", - "ahb_bist", "ahb_mmc0", "ahb_mmc1", - "ahb_mmc2", "ahb_mmc3", "ahb_ms", - "ahb_nand", "ahb_sdram", "ahb_ace", - "ahb_emac", "ahb_ts", "ahb_spi0", - "ahb_spi1", "ahb_spi2", "ahb_spi3", - "ahb_pata", "ahb_sata", "ahb_gps", - "ahb_ve", "ahb_tvd", "ahb_tve0", - "ahb_tve1", "ahb_lcd0", "ahb_lcd1", - "ahb_csi0", "ahb_csi1", "ahb_hdmi", - "ahb_de_be0", "ahb_de_be1", - "ahb_de_fe0", "ahb_de_fe1", - "ahb_mp", "ahb_mali400"; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-apb0-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <1>, - <2>, <3>, - <5>, <6>, - <7>, <10>; - clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_iis", - "apb0_pio", "apb0_ir0", - "apb0_ir1", "apb0_keypad"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <4>, - <5>, <6>, - <7>, <16>, - <17>, <18>, - <19>, <20>, - <21>, <22>, - <23>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_can", - "apb1_scr", "apb1_ps20", - "apb1_ps21", "apb1_uart0", - "apb1_uart1", "apb1_uart2", - "apb1_uart3", "apb1_uart4", - "apb1_uart5", "apb1_uart6", - "apb1_uart7"; - }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@01c20094 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20094 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc3", - "mmc3_output", - "mmc3_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - pata_clk: clk@01c200ac { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200ac 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "pata"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - ir1_clk: clk@01c200b4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir1"; - }; - - spdif_clk: clk@01c200c0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200c0 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "spdif"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_ohci1", - "usb_phy"; - }; - - spi3_clk: clk@01c200d4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200d4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi3"; - }; - - dram_gates: clk@01c20100 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-dram-gates-clk"; - reg = <0x01c20100 0x4>; - clocks = <&pll5 0>; - clock-indices = <0>, - <1>, <2>, - <3>, - <4>, - <5>, <6>, - <15>, - <24>, <25>, - <26>, <27>, - <28>, <29>; - clock-output-names = "dram_ve", - "dram_csi0", "dram_csi1", - "dram_ts", - "dram_tvd", - "dram_tve0", "dram_tve1", - "dram_output", - "dram_de_fe1", "dram_de_fe0", - "dram_de_be0", "dram_de_be1", - "dram_de_mp", "dram_ace"; - }; - - de_be0_clk: clk@01c20104 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20104 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be0"; - }; - - de_be1_clk: clk@01c20108 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20108 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be1"; - }; - - de_fe0_clk: clk@01c2010c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c2010c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe0"; - }; - - de_fe1_clk: clk@01c20110 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20110 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe1"; - }; - - - tcon0_ch0_clk: clk@01c20118 { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c20118 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch0-sclk"; - - }; - - tcon1_ch0_clk: clk@01c2011c { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c2011c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch0-sclk"; - - }; - - tcon0_ch1_clk: clk@01c2012c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c2012c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch1-sclk"; - - }; - - tcon1_ch1_clk: clk@01c20130 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c20130 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch1-sclk"; - - }; - - ve_clk: clk@01c2013c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-ve-clk"; - reg = <0x01c2013c 0x4>; - clocks = <&pll4>; - clock-output-names = "ve"; - }; - - codec_clk: clk@01c20140 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-codec-clk"; - reg = <0x01c20140 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "codec"; - }; + de: display-engine { + compatible = "allwinner,sun4i-a10-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + status = "disabled"; }; - soc@01c00000 { + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - sram-controller@01c00000 { + sram-controller@1c00000 { compatible = "allwinner,sun4i-a10-sram-controller"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; ranges; - sram_a: sram@00000000 { + sram_a: sram@0 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; @@ -697,14 +213,14 @@ }; }; - sram_d: sram@00010000 { + sram_d: sram@10000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; - otg_sram: sram-section@0000 { + otg_sram: sram-section@0 { compatible = "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; @@ -712,19 +228,19 @@ }; }; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; interrupts = <27>; - clocks = <&ahb_gates 6>; + clocks = <&ccu CLK_AHB_DMA>; #dma-cells = <2>; }; - nfc: nand@01c03000 { + nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <37>; - clocks = <&ahb_gates 13>, <&nand_clk>; + clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 3>; dma-names = "rxtx"; @@ -733,11 +249,11 @@ #size-cells = <0>; }; - spi0: spi@01c05000 { + spi0: spi@1c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <10>; - clocks = <&ahb_gates 20>, <&spi0_clk>; + clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 27>, <&dma SUN4I_DMA_DEDICATED 26>; @@ -747,30 +263,34 @@ #size-cells = <0>; }; - spi1: spi@01c06000 { + spi1: spi@1c06000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = <11>; - clocks = <&ahb_gates 21>, <&spi1_clk>; + clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 9>, <&dma SUN4I_DMA_DEDICATED 8>; dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - emac: ethernet@01c0b000 { + emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = <55>; - clocks = <&ahb_gates 17>; + clocks = <&ccu CLK_AHB_EMAC>; allwinner,sram = <&emac_sram 1>; + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins>; status = "disabled"; }; - mdio: mdio@01c0b080 { + mdio: mdio@1c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x01c0b080 0x14>; status = "disabled"; @@ -778,78 +298,154 @@ #size-cells = <0>; }; - mmc0: mmc@01c0f000 { + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun4i-a10-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + resets = <&ccu RST_TCON0>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD0>, + <&ccu CLK_TCON0_CH0>, + <&ccu CLK_TCON0_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon0-pixel-clock"; + dmas = <&dma SUN4I_DMA_DEDICATED 14>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + + tcon0_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun4i-a10-tcon"; + reg = <0x01c0d000 0x1000>; + interrupts = <45>; + resets = <&ccu RST_TCON1>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD1>, + <&ccu CLK_TCON1_CH0>, + <&ccu CLK_TCON1_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon1-pixel-clock"; + dmas = <&dma SUN4I_DMA_DEDICATED 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon1>; + }; + + tcon1_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + mmc0: mmc@1c0f000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; interrupts = <32>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; interrupts = <33>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; interrupts = <34>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - mmc3: mmc@01c12000 { + mmc3: mmc@1c12000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c12000 0x1000>; - clocks = <&ahb_gates 11>, - <&mmc3_clk 0>, - <&mmc3_clk 1>, - <&mmc3_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>; + clock-names = "ahb", "mmc"; interrupts = <35>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - usb_otg: usb@01c13000 { + usb_otg: usb@1c13000 { compatible = "allwinner,sun4i-a10-musb"; reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; + clocks = <&ccu CLK_AHB_OTG>; interrupts = <38>; interrupt-names = "mc"; phys = <&usbphy 0>; @@ -859,51 +455,95 @@ status = "disabled"; }; - usbphy: phy@01c13400 { + usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun4i-a10-usb-phy"; reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>; + clocks = <&ccu CLK_USB_PHY>; clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; status = "disabled"; }; - ehci0: usb@01c14000 { + ehci0: usb@1c14000 { compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = <39>; - clocks = <&ahb_gates 1>; + clocks = <&ccu CLK_AHB_EHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - ohci0: usb@01c14400 { + ohci0: usb@1c14400 { compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = <64>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; + clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <86>; - clocks = <&ahb_gates 5>, <&ss_clk>; + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; }; - spi2: spi@01c17000 { + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun4i-a10-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <58>; + clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, + <&ccu 9>, + <&ccu 18>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + spi2: spi@1c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = <12>; - clocks = <&ahb_gates 22>, <&spi2_clk>; + clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 29>, <&dma SUN4I_DMA_DEDICATED 28>; @@ -913,39 +553,39 @@ #size-cells = <0>; }; - ahci: sata@01c18000 { + ahci: sata@1c18000 { compatible = "allwinner,sun4i-a10-ahci"; reg = <0x01c18000 0x1000>; interrupts = <56>; - clocks = <&pll6 0>, <&ahb_gates 25>; + clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; status = "disabled"; }; - ehci1: usb@01c1c000 { + ehci1: usb@1c1c000 { compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; reg = <0x01c1c000 0x100>; interrupts = <40>; - clocks = <&ahb_gates 3>; + clocks = <&ccu CLK_AHB_EHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - ohci1: usb@01c1c400 { + ohci1: usb@1c1c400 { compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <65>; - clocks = <&usb_clk 7>, <&ahb_gates 4>; + clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - spi3: spi@01c1f000 { + spi3: spi@1c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; interrupts = <50>; - clocks = <&ahb_gates 23>, <&spi3_clk>; + clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 31>, <&dma SUN4I_DMA_DEDICATED 30>; @@ -955,30 +595,39 @@ #size-cells = <0>; }; - intc: interrupt-controller@01c20400 { + ccu: clock@1c20000 { + compatible = "allwinner,sun4i-a10-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { compatible = "allwinner,sun4i-a10-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { compatible = "allwinner,sun4i-a10-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <28>; - clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; #gpio-cells = <3>; - can0_pins_a: can0@0 { + can0_ph_pins: can0-ph-pins { pins = "PH20", "PH21"; function = "can"; }; - emac_pins_a: emac0@0 { + emac_pins: emac0-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", "PA10", @@ -987,42 +636,42 @@ function = "emac"; }; - i2c0_pins_a: i2c0@0 { + i2c0_pins: i2c0-pins { pins = "PB0", "PB1"; function = "i2c0"; }; - i2c1_pins_a: i2c1@0 { + i2c1_pins: i2c1-pins { pins = "PB18", "PB19"; function = "i2c1"; }; - i2c2_pins_a: i2c2@0 { + i2c2_pins: i2c2-pins { pins = "PB20", "PB21"; function = "i2c2"; }; - ir0_rx_pins_a: ir0@0 { + ir0_rx_pins: ir0-rx-pin { pins = "PB4"; function = "ir0"; }; - ir0_tx_pins_a: ir0@1 { + ir0_tx_pins: ir0-tx-pin { pins = "PB3"; function = "ir0"; }; - ir1_rx_pins_a: ir1@0 { + ir1_rx_pins: ir1-rx-pin { pins = "PB23"; function = "ir1"; }; - ir1_tx_pins_a: ir1@1 { + ir1_tx_pins: ir1-tx-pin { pins = "PB22"; function = "ir1"; }; - mmc0_pins_a: mmc0@0 { + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -1030,107 +679,107 @@ bias-pull-up; }; - ps20_pins_a: ps20@0 { + ps2_ch0_pins: ps2-ch0-pins { pins = "PI20", "PI21"; function = "ps2"; }; - ps21_pins_a: ps21@0 { + ps2_ch1_ph_pins: ps2-ch1-ph-pins { pins = "PH12", "PH13"; function = "ps2"; }; - pwm0_pins_a: pwm0@0 { + pwm0_pin: pwm0-pin { pins = "PB2"; function = "pwm"; }; - pwm1_pins_a: pwm1@0 { + pwm1_pin: pwm1-pin { pins = "PI3"; function = "pwm"; }; - spdif_tx_pins_a: spdif@0 { + spdif_tx_pin: spdif-tx-pin { pins = "PB13"; function = "spdif"; bias-pull-up; }; - spi0_pins_a: spi0@0 { + spi0_pi_pins: spi0-pi-pins { pins = "PI11", "PI12", "PI13"; function = "spi0"; }; - spi0_cs0_pins_a: spi0_cs0@0 { + spi0_cs0_pi_pin: spi0-cs0-pi-pin { pins = "PI10"; function = "spi0"; }; - spi1_pins_a: spi1@0 { + spi1_pins: spi1-pins { pins = "PI17", "PI18", "PI19"; function = "spi1"; }; - spi1_cs0_pins_a: spi1_cs0@0 { + spi1_cs0_pin: spi1-cs0-pin { pins = "PI16"; function = "spi1"; }; - spi2_pins_a: spi2@0 { - pins = "PC20", "PC21", "PC22"; + spi2_pb_pins: spi2-pb-pins { + pins = "PB15", "PB16", "PB17"; function = "spi2"; }; - spi2_pins_b: spi2@1 { - pins = "PB15", "PB16", "PB17"; + spi2_pc_pins: spi2-pc-pins { + pins = "PC20", "PC21", "PC22"; function = "spi2"; }; - spi2_cs0_pins_a: spi2_cs0@0 { - pins = "PC19"; + spi2_cs0_pb_pin: spi2-cs0-pb-pin { + pins = "PB14"; function = "spi2"; }; - spi2_cs0_pins_b: spi2_cs0@1 { - pins = "PB14"; + spi2_cs0_pc_pins: spi2-cs0-pc-pin { + pins = "PC19"; function = "spi2"; }; - uart0_pins_a: uart0@0 { + uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; }; - uart0_pins_b: uart0@1 { + uart0_pf_pins: uart0-pf-pins { pins = "PF2", "PF4"; function = "uart0"; }; - uart1_pins_a: uart1@0 { + uart1_pins: uart1-pins { pins = "PA10", "PA11"; function = "uart1"; }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <22>; clocks = <&osc24M>; }; - wdt: watchdog@01c20c90 { + wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; - rtc: rtc@01c20d00 { + rtc: rtc@1c20d00 { compatible = "allwinner,sun4i-a10-rtc"; reg = <0x01c20d00 0x20>; interrupts = <24>; }; - pwm: pwm@01c20e00 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun4i-a10-pwm"; reg = <0x01c20e00 0xc>; clocks = <&osc24M>; @@ -1138,12 +787,12 @@ status = "disabled"; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-spdif"; reg = <0x01c21000 0x400>; interrupts = <13>; - clocks = <&apb0_gates 1>, <&spdif_clk>; + clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; clock-names = "apb", "spdif"; dmas = <&dma SUN4I_DMA_NORMAL 2>, <&dma SUN4I_DMA_NORMAL 2>; @@ -1151,37 +800,50 @@ status = "disabled"; }; - ir0: ir@01c21800 { + ir0: ir@1c21800 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 6>, <&ir0_clk>; + clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; clock-names = "apb", "ir"; interrupts = <5>; reg = <0x01c21800 0x40>; status = "disabled"; }; - ir1: ir@01c21c00 { + ir1: ir@1c21c00 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 7>, <&ir1_clk>; + clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; clock-names = "apb", "ir"; interrupts = <6>; reg = <0x01c21c00 0x40>; status = "disabled"; }; - lradc: lradc@01c22800 { + i2s0: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <16>; + clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 3>, + <&dma SUN4I_DMA_NORMAL 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <31>; status = "disabled"; }; - codec: codec@01c22c00 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-codec"; reg = <0x01c22c00 0x40>; interrupts = <30>; - clocks = <&apb0_gates 0>, <&codec_clk>; + clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; clock-names = "apb", "codec"; dmas = <&dma SUN4I_DMA_NORMAL 19>, <&dma SUN4I_DMA_NORMAL 19>; @@ -1189,150 +851,316 @@ status = "disabled"; }; - sid: eeprom@01c23800 { + sid: eeprom@1c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; }; - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun4i-a10-ts"; reg = <0x01c25000 0x100>; interrupts = <29>; #thermal-sensor-cells = <0>; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 16>; + clocks = <&ccu CLK_APB1_UART0>; status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 17>; + clocks = <&ccu CLK_APB1_UART1>; status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <3>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 18>; + clocks = <&ccu CLK_APB1_UART2>; status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 19>; + clocks = <&ccu CLK_APB1_UART3>; status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <17>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 20>; + clocks = <&ccu CLK_APB1_UART4>; status = "disabled"; }; - uart5: serial@01c29400 { + uart5: serial@1c29400 { compatible = "snps,dw-apb-uart"; reg = <0x01c29400 0x400>; interrupts = <18>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 21>; + clocks = <&ccu CLK_APB1_UART5>; status = "disabled"; }; - uart6: serial@01c29800 { + uart6: serial@1c29800 { compatible = "snps,dw-apb-uart"; reg = <0x01c29800 0x400>; interrupts = <19>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 22>; + clocks = <&ccu CLK_APB1_UART6>; status = "disabled"; }; - uart7: serial@01c29c00 { + uart7: serial@1c29c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c29c00 0x400>; interrupts = <20>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 23>; + clocks = <&ccu CLK_APB1_UART7>; status = "disabled"; }; - ps20: ps2@01c2a000 { + ps20: ps2@1c2a000 { compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a000 0x400>; interrupts = <62>; - clocks = <&apb1_gates 6>; + clocks = <&ccu CLK_APB1_PS20>; status = "disabled"; }; - ps21: ps2@01c2a400 { + ps21: ps2@1c2a400 { compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a400 0x400>; interrupts = <63>; - clocks = <&apb1_gates 7>; + clocks = <&ccu CLK_APB1_PS21>; status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <7>; - clocks = <&apb1_gates 0>; + clocks = <&ccu CLK_APB1_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <8>; - clocks = <&apb1_gates 1>; + clocks = <&ccu CLK_APB1_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <9>; - clocks = <&apb1_gates 2>; + clocks = <&ccu CLK_APB1_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - can0: can@01c2bc00 { + can0: can@1c2bc00 { compatible = "allwinner,sun4i-a10-can"; reg = <0x01c2bc00 0x400>; interrupts = <26>; - clocks = <&apb1_gates 4>; + clocks = <&ccu CLK_APB1_CAN>; status = "disabled"; }; + + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun4i-a10-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_DRAM_DE_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; + }; + + fe1: display-frontend@1e20000 { + compatible = "allwinner,sun4i-a10-display-frontend"; + reg = <0x01e20000 0x20000>; + interrupts = <48>; + clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, + <&ccu CLK_DRAM_DE_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe1>; + }; + + fe1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe1>; + }; + }; + }; + }; + + be1: display-backend@1e40000 { + compatible = "allwinner,sun4i-a10-display-backend"; + reg = <0x01e40000 0x10000>; + interrupts = <48>; + clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, + <&ccu CLK_DRAM_DE_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be1>; + }; + + be1_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be1>; + }; + }; + + be1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon1_in_be0>; + }; + + be1_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be1>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + compatible = "allwinner,sun4i-a10-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_DRAM_DE_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + + be0_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + + be0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be0>; + }; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 18f25c5e75ae..6ae4d95e230e 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -76,8 +76,8 @@ allwinner,pipelines = <&fe0>; }; - soc@01c00000 { - hdmi: hdmi@01c16000 { + soc@1c00000 { + hdmi: hdmi@1c16000 { compatible = "allwinner,sun5i-a10s-hdmi"; reg = <0x01c16000 0x1000>; interrupts = <58>; @@ -111,7 +111,7 @@ }; }; - pwm: pwm@01c20e00 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun5i-a10s-pwm"; reg = <0x01c20e00 0xc>; clocks = <&ccu CLK_HOSC>; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 6436bad94404..4e830f5cb7f1 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -88,8 +88,8 @@ allwinner,pipelines = <&fe0>; }; - soc@01c00000 { - pwm: pwm@01c20e00 { + soc@1c00000 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun5i-a13-pwm"; reg = <0x01c20e00 0xc>; clocks = <&ccu CLK_HOSC>; diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi index 3eb56cad0cea..ef0b7446a99d 100644 --- a/arch/arm/boot/dts/sun5i-gr8.dtsi +++ b/arch/arm/boot/dts/sun5i-gr8.dtsi @@ -54,8 +54,8 @@ allwinner,pipelines = <&fe0>; }; - soc@01c00000 { - pwm: pwm@01c20e00 { + soc@1c00000 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun5i-a10s-pwm"; reg = <0x01c20e00 0xc>; clocks = <&ccu CLK_HOSC>; @@ -63,7 +63,7 @@ status = "disabled"; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-spdif"; reg = <0x01c21000 0x400>; @@ -76,7 +76,7 @@ status = "disabled"; }; - i2s0: i2s@01c22400 { + i2s0: i2s@1c22400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22400 0x400>; diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index 8a4d2277826f..49229b3d5492 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -110,6 +110,14 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + &lradc { vref-supply = <®_ldo2>; }; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 98cc00341b00..07f2248ed5f8 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -93,7 +93,7 @@ #size-cells = <1>; ranges; - osc24M: clk@01c20050 { + osc24M: clk@1c20050 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -108,20 +108,20 @@ }; }; - soc@01c00000 { + soc@1c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - sram-controller@01c00000 { + sram-controller@1c00000 { compatible = "allwinner,sun4i-a10-sram-controller"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; ranges; - sram_a: sram@00000000 { + sram_a: sram@0 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; @@ -135,14 +135,14 @@ status = "disabled"; }; - sram_d: sram@00010000 { + sram_d: sram@10000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; - otg_sram: sram-section@0000 { + otg_sram: sram-section@0 { compatible = "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; @@ -150,7 +150,7 @@ }; }; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; interrupts = <27>; @@ -158,7 +158,7 @@ #dma-cells = <2>; }; - nfc: nand@01c03000 { + nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <37>; @@ -171,7 +171,7 @@ #size-cells = <0>; }; - spi0: spi@01c05000 { + spi0: spi@1c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <10>; @@ -185,7 +185,7 @@ #size-cells = <0>; }; - spi1: spi@01c06000 { + spi1: spi@1c06000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = <11>; @@ -199,7 +199,7 @@ #size-cells = <0>; }; - tve0: tv-encoder@01c0a000 { + tve0: tv-encoder@1c0a000 { compatible = "allwinner,sun4i-a10-tv-encoder"; reg = <0x01c0a000 0x1000>; clocks = <&ccu CLK_AHB_TVE>; @@ -217,7 +217,7 @@ }; }; - emac: ethernet@01c0b000 { + emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = <55>; @@ -226,7 +226,7 @@ status = "disabled"; }; - mdio: mdio@01c0b080 { + mdio: mdio@1c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x01c0b080 0x14>; status = "disabled"; @@ -234,7 +234,7 @@ #size-cells = <0>; }; - tcon0: lcd-controller@01c0c000 { + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun5i-a13-tcon"; reg = <0x01c0c000 0x1000>; interrupts = <44>; @@ -278,7 +278,7 @@ }; }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; @@ -289,7 +289,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; @@ -300,7 +300,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; @@ -311,7 +311,7 @@ #size-cells = <0>; }; - usb_otg: usb@01c13000 { + usb_otg: usb@1c13000 { compatible = "allwinner,sun4i-a10-musb"; reg = <0x01c13000 0x0400>; clocks = <&ccu CLK_AHB_OTG>; @@ -324,7 +324,7 @@ status = "disabled"; }; - usbphy: phy@01c13400 { + usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy"; reg = <0x01c13400 0x10 0x01c14800 0x4>; @@ -336,7 +336,7 @@ status = "disabled"; }; - ehci0: usb@01c14000 { + ehci0: usb@1c14000 { compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = <39>; @@ -346,7 +346,7 @@ status = "disabled"; }; - ohci0: usb@01c14400 { + ohci0: usb@1c14400 { compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = <40>; @@ -356,7 +356,7 @@ status = "disabled"; }; - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun5i-a13-crypto", "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; @@ -365,7 +365,7 @@ clock-names = "ahb", "mod"; }; - spi2: spi@01c17000 { + spi2: spi@1c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = <12>; @@ -379,7 +379,7 @@ #size-cells = <0>; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; clock-names = "hosc", "losc"; @@ -387,14 +387,14 @@ #reset-cells = <1>; }; - intc: interrupt-controller@01c20400 { + intc: interrupt-controller@1c20400 { compatible = "allwinner,sun4i-a10-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { reg = <0x01c20800 0x400>; interrupts = <28>; clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; @@ -538,19 +538,19 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <22>; clocks = <&ccu CLK_HOSC>; }; - wdt: watchdog@01c20c90 { + wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; - ir0: ir@01c21800 { + ir0: ir@1c21800 { compatible = "allwinner,sun4i-a10-ir"; clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>; clock-names = "apb", "ir"; @@ -559,14 +559,14 @@ status = "disabled"; }; - lradc: lradc@01c22800 { + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <31>; status = "disabled"; }; - codec: codec@01c22c00 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-codec"; reg = <0x01c22c00 0x40>; @@ -579,19 +579,19 @@ status = "disabled"; }; - sid: eeprom@01c23800 { + sid: eeprom@1c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; }; - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun5i-a13-ts"; reg = <0x01c25000 0x100>; interrupts = <29>; #thermal-sensor-cells = <0>; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <1>; @@ -601,7 +601,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <2>; @@ -611,7 +611,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <3>; @@ -621,7 +621,7 @@ status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <4>; @@ -631,7 +631,7 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <7>; @@ -641,7 +641,7 @@ #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <8>; @@ -651,7 +651,7 @@ #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <9>; @@ -661,14 +661,14 @@ #size-cells = <0>; }; - timer@01c60000 { + timer@1c60000 { compatible = "allwinner,sun5i-a13-hstimer"; reg = <0x01c60000 0x1000>; interrupts = <82>, <83>; clocks = <&ccu CLK_AHB_HSTIMER>; }; - fe0: display-frontend@01e00000 { + fe0: display-frontend@1e00000 { compatible = "allwinner,sun5i-a13-display-frontend"; reg = <0x01e00000 0x20000>; interrupts = <47>; @@ -696,7 +696,7 @@ }; }; - be0: display-backend@01e60000 { + be0: display-backend@1e60000 { compatible = "allwinner,sun5i-a13-display-backend"; reg = <0x01e60000 0x10000>; interrupts = <47>; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 9ecb5f0b3f83..19e382a11297 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -62,6 +62,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + vga-connector { compatible = "vga-connector"; @@ -162,6 +173,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index eef072a21acc..8bfa12b548e0 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -221,7 +221,7 @@ clock-output-names = "gmac_int_tx"; }; - gmac_tx_clk: clk@01c200d0 { + gmac_tx_clk: clk@1c200d0 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-gmac-clk"; reg = <0x01c200d0 0x4>; @@ -236,13 +236,13 @@ status = "disabled"; }; - soc@01c00000 { + soc@1c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun6i-a31-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -251,7 +251,7 @@ #dma-cells = <1>; }; - tcon0: lcd-controller@01c0c000 { + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun6i-a31-tcon"; reg = <0x01c0c000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; @@ -278,17 +278,28 @@ reg = <0>; remote-endpoint = <&drc0_out_tcon0>; }; + + tcon0_in_drc1: endpoint@1 { + reg = <1>; + remote-endpoint = <&drc1_out_tcon0>; + }; }; tcon0_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; }; }; }; - tcon1: lcd-controller@01c0d000 { + tcon1: lcd-controller@1c0d000 { compatible = "allwinner,sun6i-a31-tcon"; reg = <0x01c0d000 0x1000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; @@ -311,6 +322,11 @@ #size-cells = <0>; reg = <0>; + tcon1_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon1>; + }; + tcon1_in_drc1: endpoint@1 { reg = <1>; remote-endpoint = <&drc1_out_tcon1>; @@ -321,11 +337,17 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + allwinner,tcon-channel = <1>; + }; }; }; }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_AHB1_MMC0>, @@ -344,7 +366,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ccu CLK_AHB1_MMC1>, @@ -363,7 +385,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ccu CLK_AHB1_MMC2>, @@ -382,7 +404,7 @@ #size-cells = <0>; }; - mmc3: mmc@01c12000 { + mmc3: mmc@1c12000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c12000 0x1000>; clocks = <&ccu CLK_AHB1_MMC3>, @@ -401,7 +423,50 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun6i-a31-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, + <&ccu CLK_HDMI_DDC>, + <&ccu 7>, + <&ccu 13>; + clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; + resets = <&ccu RST_AHB1_HDMI>; + reset-names = "ahb"; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + dmas = <&dma 13>, <&dma 13>, <&dma 14>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + usb_otg: usb@1c19000 { compatible = "allwinner,sun6i-a31-musb"; reg = <0x01c19000 0x0400>; clocks = <&ccu CLK_AHB1_OTG>; @@ -414,7 +479,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { compatible = "allwinner,sun6i-a31-usb-phy"; reg = <0x01c19400 0x10>, <0x01c1a800 0x4>, @@ -438,7 +503,7 @@ #phy-cells = <1>; }; - ehci0: usb@01c1a000 { + ehci0: usb@1c1a000 { compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; @@ -449,7 +514,7 @@ status = "disabled"; }; - ohci0: usb@01c1a400 { + ohci0: usb@1c1a400 { compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; @@ -460,7 +525,7 @@ status = "disabled"; }; - ehci1: usb@01c1b000 { + ehci1: usb@1c1b000 { compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; @@ -471,7 +536,7 @@ status = "disabled"; }; - ohci1: usb@01c1b400 { + ohci1: usb@1c1b400 { compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1b400 0x100>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; @@ -482,7 +547,7 @@ status = "disabled"; }; - ohci2: usb@01c1c400 { + ohci2: usb@1c1c400 { compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; @@ -491,7 +556,7 @@ status = "disabled"; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { compatible = "allwinner,sun6i-a31-ccu"; reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; @@ -500,7 +565,7 @@ #reset-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -633,7 +698,7 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -644,12 +709,12 @@ clocks = <&osc24M>; }; - wdt1: watchdog@01c20ca0 { + wdt1: watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun6i-a31-spdif"; reg = <0x01c21000 0x400>; @@ -662,21 +727,47 @@ status = "disabled"; }; - lradc: lradc@01c22800 { + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-i2s"; + reg = <0x01c22000 0x400>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>; + resets = <&ccu RST_APB1_DAUDIO0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>; + resets = <&ccu RST_APB1_DAUDIO1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun6i-a31-ts"; reg = <0x01c25000 0x100>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; #thermal-sensor-cells = <0>; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -689,7 +780,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -702,7 +793,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -715,7 +806,7 @@ status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -728,7 +819,7 @@ status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -741,7 +832,7 @@ status = "disabled"; }; - uart5: serial@01c29400 { + uart5: serial@1c29400 { compatible = "snps,dw-apb-uart"; reg = <0x01c29400 0x400>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; @@ -754,7 +845,7 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -765,7 +856,7 @@ #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -776,7 +867,7 @@ #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -787,7 +878,7 @@ #size-cells = <0>; }; - i2c3: i2c@01c2b800 { + i2c3: i2c@1c2b800 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b800 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; @@ -798,7 +889,7 @@ #size-cells = <0>; }; - gmac: ethernet@01c30000 { + gmac: ethernet@1c30000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x01c30000 0x1054>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; @@ -815,7 +906,7 @@ #size-cells = <0>; }; - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun6i-a31-crypto", "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; @@ -826,7 +917,7 @@ reset-names = "ahb"; }; - codec: codec@01c22c00 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun6i-a31-codec"; reg = <0x01c22c00 0x400>; @@ -839,7 +930,7 @@ status = "disabled"; }; - timer@01c60000 { + timer@1c60000 { compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; @@ -851,7 +942,7 @@ resets = <&ccu RST_AHB1_HSTIMER>; }; - spi0: spi@01c68000 { + spi0: spi@1c68000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c68000 0x1000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; @@ -863,7 +954,7 @@ status = "disabled"; }; - spi1: spi@01c69000 { + spi1: spi@1c69000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c69000 0x1000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; @@ -875,7 +966,7 @@ status = "disabled"; }; - spi2: spi@01c6a000 { + spi2: spi@1c6a000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c6a000 0x1000>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; @@ -887,7 +978,7 @@ status = "disabled"; }; - spi3: spi@01c6b000 { + spi3: spi@1c6b000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c6b000 0x1000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; @@ -899,7 +990,7 @@ status = "disabled"; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, @@ -910,7 +1001,7 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; - fe0: display-frontend@01e00000 { + fe0: display-frontend@1e00000 { compatible = "allwinner,sun6i-a31-display-frontend"; reg = <0x01e00000 0x20000>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; @@ -942,7 +1033,7 @@ }; }; - fe1: display-frontend@01e20000 { + fe1: display-frontend@1e20000 { compatible = "allwinner,sun6i-a31-display-frontend"; reg = <0x01e20000 0x20000>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; @@ -974,7 +1065,7 @@ }; }; - be1: display-backend@01e40000 { + be1: display-backend@1e40000 { compatible = "allwinner,sun6i-a31-display-backend"; reg = <0x01e40000 0x10000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; @@ -1020,7 +1111,7 @@ }; }; - drc1: drc@01e50000 { + drc1: drc@1e50000 { compatible = "allwinner,sun6i-a31-drc"; reg = <0x01e50000 0x10000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; @@ -1053,6 +1144,11 @@ #size-cells = <0>; reg = <1>; + drc1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc1>; + }; + drc1_out_tcon1: endpoint@1 { reg = <1>; remote-endpoint = <&tcon1_in_drc1>; @@ -1061,7 +1157,7 @@ }; }; - be0: display-backend@01e60000 { + be0: display-backend@1e60000 { compatible = "allwinner,sun6i-a31-display-backend"; reg = <0x01e60000 0x10000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; @@ -1107,7 +1203,7 @@ }; }; - drc0: drc@01e70000 { + drc0: drc@1e70000 { compatible = "allwinner,sun6i-a31-drc"; reg = <0x01e70000 0x10000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; @@ -1144,11 +1240,16 @@ reg = <0>; remote-endpoint = <&tcon0_in_drc0>; }; + + drc0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_drc0>; + }; }; }; }; - rtc: rtc@01f00000 { + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, @@ -1163,7 +1264,7 @@ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; - prcm@01f01400 { + prcm@1f01400 { compatible = "allwinner,sun6i-a31-prcm"; reg = <0x01f01400 0x200>; @@ -1215,12 +1316,12 @@ }; }; - cpucfg@01f01c00 { + cpucfg@1f01c00 { compatible = "allwinner,sun6i-a31-cpuconfig"; reg = <0x01f01c00 0x300>; }; - ir: ir@01f02000 { + ir: ir@1f02000 { compatible = "allwinner,sun5i-a13-ir"; clocks = <&apb0_gates 1>, <&ir_clk>; clock-names = "apb", "ir"; @@ -1230,7 +1331,7 @@ status = "disabled"; }; - r_pio: pinctrl@01f02c00 { + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun6i-a31-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, @@ -1255,7 +1356,7 @@ }; }; - p2wi: i2c@01f03400 { + p2wi: i2c@1f03400 { compatible = "allwinner,sun6i-a31-p2wi"; reg = <0x01f03400 0x400>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index 4c10123509c4..0cdb38ab3377 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -52,17 +52,42 @@ / { model = "MSI Primo81 tablet"; compatible = "msi,primo81", "allwinner,sun6i-a31s"; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "c"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; }; &cpu0 { cpu-supply = <®_dcdc3>; }; +&de { + status = "okay"; +}; + &ehci0 { /* rtl8188etv wifi is connected here */ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { /* pull-ups and device VDDIO use AXP221 DLDO3 */ pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts index b3d98222bd81..298476485bb4 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts @@ -53,6 +53,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -90,6 +101,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { /* USB 2.0 4 port hub IC */ status = "okay"; @@ -112,6 +127,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index eb55e74232c9..4ed3162e3e5a 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -60,6 +60,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -109,6 +120,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -130,6 +145,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 2a50207618cb..39f43e4eb742 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -61,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -91,6 +102,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -111,6 +126,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 852a0aa24dce..8c9bedc602ec 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -61,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -126,6 +137,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -146,6 +161,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index 004b6ddac813..442f3c755f36 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -61,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -98,6 +109,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -173,6 +188,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -241,6 +266,14 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_ahci_5v { gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ status = "okay"; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts index 2ce1a9f13a17..edf9c3c6c0d7 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -62,6 +62,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -80,6 +91,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -100,6 +115,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index 097bd755764c..ba250189d07f 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -59,6 +59,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -85,6 +96,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -105,6 +120,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts new file mode 100644 index 000000000000..d99e7b193efe --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts @@ -0,0 +1,70 @@ + /* + * Copyright 2017 Olimex Ltd. + * Stefan Mavrodiev <stefan@olimex.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun7i-a20-olinuxino-micro.dts" + +/ { + model = "Olimex A20-OLinuXino-MICRO-eMMC"; + compatible = "olimex,a20-olinuxino-micro-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&mmc2_pwrseq>; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 0b7403e4d687..dffbaa24b3ee 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -66,6 +66,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -92,6 +103,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -102,7 +117,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_pins_mii_a>, <&gmac_txerr>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -112,6 +127,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -229,6 +254,11 @@ }; &pio { + gmac_txerr: gmac_txerr@0 { + pins = "PA17"; + function = "gmac"; + }; + mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { pins = "PH11"; function = "gpio_in"; @@ -256,6 +286,14 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -330,6 +368,10 @@ status = "okay"; }; +&usb_power_supply { + status = "okay"; +}; + &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 96bee776e145..68dfa82544fc 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -46,9 +46,9 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> - -#include <dt-bindings/clock/sun4i-a10-pll2.h> #include <dt-bindings/dma/sun4i-a10.h> +#include <dt-bindings/clock/sun4i-a10-ccu.h> +#include <dt-bindings/reset/sun4i-a10-ccu.h> / { interrupt-parent = <&gic>; @@ -66,9 +66,10 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&de_be0_clk>, - <&tcon0_ch1_clk>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>, + <&ccu CLK_HDMI>; status = "disabled"; }; @@ -76,9 +77,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ahb_gates 36>, <&ahb_gates 44>, - <&de_be0_clk>, <&tcon0_ch0_clk>, - <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>, + <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; @@ -86,10 +87,10 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>, - <&de_be0_clk>, <&tcon0_ch1_clk>, - <&dram_gates 5>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, + <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>, + <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; }; @@ -102,7 +103,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; - clocks = <&cpu>; + clocks = <&ccu CLK_CPU>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < /* kHz uV */ @@ -181,23 +182,13 @@ #size-cells = <1>; ranges; - osc24M: clk@01c20050 { + osc24M: clk@1c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; + compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; - osc3M: osc3M_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <8>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc3M"; - }; - osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -205,528 +196,6 @@ clock-output-names = "osc32k"; }; - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll2: clk@01c20008 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll2-clk"; - reg = <0x01c20008 0x8>; - clocks = <&osc24M>; - clock-output-names = "pll2-1x", "pll2-2x", - "pll2-4x", "pll2-8x"; - }; - - pll3: clk@01c20010 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll3"; - }; - - pll3x2: pll3x2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&pll3>; - clock-div = <1>; - clock-mult = <2>; - clock-output-names = "pll3-2x"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-pll4-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6", - "pll6_div_4"; - }; - - pll7: clk@01c20030 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll7"; - }; - - pll7x2: pll7x2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&pll7>; - clock-div = <1>; - clock-mult = <2>; - clock-output-names = "pll7-2x"; - }; - - pll8: clk@01c20040 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-pll4-clk"; - reg = <0x01c20040 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll8"; - }; - - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>, <&pll6 3>, <&pll6 1>; - clock-output-names = "ahb"; - /* - * Use PLL6 as parent, instead of CPU/AXI - * which has rate changes due to cpufreq - */ - assigned-clocks = <&ahb>; - assigned-clock-parents = <&pll6 3>; - }; - - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, <8>, - <9>, <10>, <11>, <12>, - <13>, <14>, <16>, - <17>, <18>, <20>, <21>, - <22>, <23>, <25>, - <28>, <32>, <33>, <34>, - <35>, <36>, <37>, <40>, - <41>, <42>, <43>, - <44>, <45>, <46>, - <47>, <49>, <50>, - <52>; - clock-output-names = "ahb_usb0", "ahb_ehci0", - "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", - "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", - "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", - "ahb_nand", "ahb_sdram", "ahb_ace", - "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", - "ahb_spi2", "ahb_spi3", "ahb_sata", - "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", - "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", - "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", - "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", - "ahb_de_fe1", "ahb_gmac", "ahb_mp", - "ahb_mali"; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-apb0-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, - <8>, <10>; - clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_i2s0", "apb0_i2s1", - "apb0_pio", "apb0_ir0", "apb0_ir1", - "apb0_i2s2", "apb0_keypad"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, - <15>, <16>, <17>, - <18>, <19>, <20>, - <21>, <22>, <23>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_i2c3", "apb1_can", - "apb1_scr", "apb1_ps20", "apb1_ps21", - "apb1_i2c4", "apb1_uart0", "apb1_uart1", - "apb1_uart2", "apb1_uart3", "apb1_uart4", - "apb1_uart5", "apb1_uart6", "apb1_uart7"; - }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@01c20094 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20094 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc3", - "mmc3_output", - "mmc3_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - pata_clk: clk@01c200ac { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200ac 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "pata"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - ir1_clk: clk@01c200b4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir1"; - }; - - i2s0_clk: clk@01c200b8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200b8 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s0"; - }; - - ac97_clk: clk@01c200bc { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200bc 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "ac97"; - }; - - spdif_clk: clk@01c200c0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200c0 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "spdif"; - }; - - keypad_clk: clk@01c200c4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200c4 0x4>; - clocks = <&osc24M>; - clock-output-names = "keypad"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_ohci1", - "usb_phy"; - }; - - spi3_clk: clk@01c200d4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200d4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi3"; - }; - - i2s1_clk: clk@01c200d8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200d8 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s1"; - }; - - i2s2_clk: clk@01c200dc { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200dc 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s2"; - }; - - dram_gates: clk@01c20100 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-dram-gates-clk"; - reg = <0x01c20100 0x4>; - clocks = <&pll5 0>; - clock-indices = <0>, - <1>, <2>, - <3>, - <4>, - <5>, <6>, - <15>, - <24>, <25>, - <26>, <27>, - <28>, <29>; - clock-output-names = "dram_ve", - "dram_csi0", "dram_csi1", - "dram_ts", - "dram_tvd", - "dram_tve0", "dram_tve1", - "dram_output", - "dram_de_fe1", "dram_de_fe0", - "dram_de_be0", "dram_de_be1", - "dram_de_mp", "dram_ace"; - }; - - de_be0_clk: clk@01c20104 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20104 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be0"; - }; - - de_be1_clk: clk@01c20108 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20108 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be1"; - }; - - de_fe0_clk: clk@01c2010c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c2010c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe0"; - }; - - de_fe1_clk: clk@01c20110 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20110 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe1"; - }; - - tcon0_ch0_clk: clk@01c20118 { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c20118 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch0-sclk"; - - }; - - tcon1_ch0_clk: clk@01c2011c { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c2011c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch0-sclk"; - - }; - - tcon0_ch1_clk: clk@01c2012c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c2012c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch1-sclk"; - - }; - - tcon1_ch1_clk: clk@01c20130 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c20130 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch1-sclk"; - - }; - - ve_clk: clk@01c2013c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-ve-clk"; - reg = <0x01c2013c 0x4>; - clocks = <&pll4>; - clock-output-names = "ve"; - }; - - codec_clk: clk@01c20140 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-codec-clk"; - reg = <0x01c20140 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "codec"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; - clock-output-names = "mbus"; - }; - /* * The following two are dummy clocks, placeholders * used in the gmac_tx clock. The gmac driver will @@ -736,71 +205,50 @@ * The actual TX clock rate is not controlled by the * gmac_tx clock. */ - mii_phy_tx_clk: clk@2 { + mii_phy_tx_clk: clk@1 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; clock-output-names = "mii_phy_tx"; }; - gmac_int_tx_clk: clk@3 { + gmac_int_tx_clk: clk@2 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <125000000>; clock-output-names = "gmac_int_tx"; }; - gmac_tx_clk: clk@01c20164 { + gmac_tx_clk: clk@1c20164 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-gmac-clk"; reg = <0x01c20164 0x4>; clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; clock-output-names = "gmac_tx"; }; + }; - /* - * Dummy clock used by output clocks - */ - osc24M_32k: clk@1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <750>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc24M_32k"; - }; - clk_out_a: clk@01c201f0 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-out-clk"; - reg = <0x01c201f0 0x4>; - clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; - clock-output-names = "clk_out_a"; - }; - - clk_out_b: clk@01c201f4 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-out-clk"; - reg = <0x01c201f4 0x4>; - clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; - clock-output-names = "clk_out_b"; - }; + de: display-engine { + compatible = "allwinner,sun7i-a20-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + status = "disabled"; }; - soc@01c00000 { + soc@1c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - sram-controller@01c00000 { + sram-controller@1c00000 { compatible = "allwinner,sun4i-a10-sram-controller"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; ranges; - sram_a: sram@00000000 { + sram_a: sram@0 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; @@ -814,14 +262,14 @@ }; }; - sram_d: sram@00010000 { + sram_d: sram@10000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; - otg_sram: sram-section@0000 { + otg_sram: sram-section@0 { compatible = "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; @@ -829,7 +277,7 @@ }; }; - nmi_intc: interrupt-controller@01c00030 { + nmi_intc: interrupt-controller@1c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; #interrupt-cells = <2>; @@ -837,19 +285,19 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 6>; + clocks = <&ccu CLK_AHB_DMA>; #dma-cells = <2>; }; - nfc: nand@01c03000 { + nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 13>, <&nand_clk>; + clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 3>; dma-names = "rxtx"; @@ -858,11 +306,11 @@ #size-cells = <0>; }; - spi0: spi@01c05000 { + spi0: spi@1c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 20>, <&spi0_clk>; + clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 27>, <&dma SUN4I_DMA_DEDICATED 26>; @@ -873,11 +321,11 @@ num-cs = <4>; }; - spi1: spi@01c06000 { + spi1: spi@1c06000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 21>, <&spi1_clk>; + clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 9>, <&dma SUN4I_DMA_DEDICATED 8>; @@ -888,16 +336,16 @@ num-cs = <1>; }; - emac: ethernet@01c0b000 { + emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 17>; + clocks = <&ccu CLK_AHB_EMAC>; allwinner,sram = <&emac_sram 1>; status = "disabled"; }; - mdio: mdio@01c0b080 { + mdio: mdio@1c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x01c0b080 0x14>; status = "disabled"; @@ -905,13 +353,111 @@ #size-cells = <0>; }; - mmc0: mmc@01c0f000 { + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun7i-a20-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_TCON0>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD0>, + <&ccu CLK_TCON0_CH0>, + <&ccu CLK_TCON0_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon0-pixel-clock"; + dmas = <&dma SUN4I_DMA_DEDICATED 14>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + + tcon0_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun7i-a20-tcon"; + reg = <0x01c0d000 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_TCON1>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD1>, + <&ccu CLK_TCON1_CH0>, + <&ccu CLK_TCON1_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon1-pixel-clock"; + dmas = <&dma SUN4I_DMA_DEDICATED 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon1>; + }; + + tcon1_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; + clocks = <&ccu CLK_AHB_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -922,13 +468,13 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; + clocks = <&ccu CLK_AHB_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -939,13 +485,13 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; + clocks = <&ccu CLK_AHB_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -956,13 +502,13 @@ #size-cells = <0>; }; - mmc3: mmc@01c12000 { + mmc3: mmc@1c12000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c12000 0x1000>; - clocks = <&ahb_gates 11>, - <&mmc3_clk 0>, - <&mmc3_clk 1>, - <&mmc3_clk 2>; + clocks = <&ccu CLK_AHB_MMC3>, + <&ccu CLK_MMC3>, + <&ccu CLK_MMC3_OUTPUT>, + <&ccu CLK_MMC3_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -973,10 +519,10 @@ #size-cells = <0>; }; - usb_otg: usb@01c13000 { + usb_otg: usb@1c13000 { compatible = "allwinner,sun4i-a10-musb"; reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; + clocks = <&ccu CLK_AHB_OTG>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mc"; phys = <&usbphy 0>; @@ -986,52 +532,97 @@ status = "disabled"; }; - usbphy: phy@01c13400 { + usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun7i-a20-usb-phy"; reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>; + clocks = <&ccu CLK_USB_PHY>; clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; status = "disabled"; }; - ehci0: usb@01c14000 { + ehci0: usb@1c14000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 1>; + clocks = <&ccu CLK_AHB_EHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - ohci0: usb@01c14400 { + ohci0: usb@1c14400 { compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; + clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun7i-a20-crypto", "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 5>, <&ss_clk>; + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; }; - spi2: spi@01c17000 { + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun7i-a20-hdmi", + "allwinner,sun5i-a10s-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, + <&ccu 9>, + <&ccu 18>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + spi2: spi@1c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 22>, <&spi2_clk>; + clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 29>, <&dma SUN4I_DMA_DEDICATED 28>; @@ -1042,39 +633,39 @@ num-cs = <1>; }; - ahci: sata@01c18000 { + ahci: sata@1c18000 { compatible = "allwinner,sun4i-a10-ahci"; reg = <0x01c18000 0x1000>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pll6 0>, <&ahb_gates 25>; + clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; status = "disabled"; }; - ehci1: usb@01c1c000 { + ehci1: usb@1c1c000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c1c000 0x100>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 3>; + clocks = <&ccu CLK_AHB_EHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - ohci1: usb@01c1c400 { + ohci1: usb@1c1c400 { compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clk 7>, <&ahb_gates 4>; + clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - spi3: spi@01c1f000 { + spi3: spi@1c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 23>, <&spi3_clk>; + clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 31>, <&dma SUN4I_DMA_DEDICATED 30>; @@ -1085,11 +676,20 @@ num-cs = <1>; }; - pio: pinctrl@01c20800 { + ccu: clock@1c20000 { + compatible = "allwinner,sun7i-a20-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { compatible = "allwinner,sun7i-a20-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -1324,7 +924,7 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, @@ -1336,18 +936,18 @@ clocks = <&osc24M>; }; - wdt: watchdog@01c20c90 { + wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; - rtc: rtc@01c20d00 { + rtc: rtc@1c20d00 { compatible = "allwinner,sun7i-a20-rtc"; reg = <0x01c20d00 0x20>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; }; - pwm: pwm@01c20e00 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun7i-a20-pwm"; reg = <0x01c20e00 0xc>; clocks = <&osc24M>; @@ -1355,12 +955,12 @@ status = "disabled"; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-spdif"; reg = <0x01c21000 0x400>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 1>, <&spdif_clk>; + clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; clock-names = "apb", "spdif"; dmas = <&dma SUN4I_DMA_NORMAL 2>, <&dma SUN4I_DMA_NORMAL 2>; @@ -1368,30 +968,30 @@ status = "disabled"; }; - ir0: ir@01c21800 { + ir0: ir@1c21800 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 6>, <&ir0_clk>; + clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; clock-names = "apb", "ir"; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01c21800 0x40>; status = "disabled"; }; - ir1: ir@01c21c00 { + ir1: ir@1c21c00 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 7>, <&ir1_clk>; + clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; clock-names = "apb", "ir"; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01c21c00 0x40>; status = "disabled"; }; - i2s1: i2s@01c22000 { + i2s1: i2s@1c22000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22000 0x400>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 4>, <&i2s1_clk>; + clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 4>, <&dma SUN4I_DMA_NORMAL 4>; @@ -1399,12 +999,12 @@ status = "disabled"; }; - i2s0: i2s@01c22400 { + i2s0: i2s@1c22400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22400 0x400>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 3>, <&i2s0_clk>; + clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 3>, <&dma SUN4I_DMA_NORMAL 3>; @@ -1412,19 +1012,19 @@ status = "disabled"; }; - lradc: lradc@01c22800 { + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - codec: codec@01c22c00 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun7i-a20-codec"; reg = <0x01c22c00 0x40>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&codec_clk>; + clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; clock-names = "apb", "codec"; dmas = <&dma SUN4I_DMA_NORMAL 19>, <&dma SUN4I_DMA_NORMAL 19>; @@ -1432,17 +1032,17 @@ status = "disabled"; }; - sid: eeprom@01c23800 { + sid: eeprom@1c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; }; - i2s2: i2s@01c24400 { + i2s2: i2s@1c24400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c24400 0x400>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 8>, <&i2s2_clk>; + clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 6>, <&dma SUN4I_DMA_NORMAL 6>; @@ -1450,179 +1050,179 @@ status = "disabled"; }; - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun5i-a13-ts"; reg = <0x01c25000 0x100>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #thermal-sensor-cells = <0>; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 16>; + clocks = <&ccu CLK_APB1_UART0>; status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 17>; + clocks = <&ccu CLK_APB1_UART1>; status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 18>; + clocks = <&ccu CLK_APB1_UART2>; status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 19>; + clocks = <&ccu CLK_APB1_UART3>; status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 20>; + clocks = <&ccu CLK_APB1_UART4>; status = "disabled"; }; - uart5: serial@01c29400 { + uart5: serial@1c29400 { compatible = "snps,dw-apb-uart"; reg = <0x01c29400 0x400>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 21>; + clocks = <&ccu CLK_APB1_UART5>; status = "disabled"; }; - uart6: serial@01c29800 { + uart6: serial@1c29800 { compatible = "snps,dw-apb-uart"; reg = <0x01c29800 0x400>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 22>; + clocks = <&ccu CLK_APB1_UART6>; status = "disabled"; }; - uart7: serial@01c29c00 { + uart7: serial@1c29c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c29c00 0x400>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 23>; + clocks = <&ccu CLK_APB1_UART7>; status = "disabled"; }; - ps20: ps2@01c2a000 { + ps20: ps2@1c2a000 { compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a000 0x400>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 6>; + clocks = <&ccu CLK_APB1_PS20>; status = "disabled"; }; - ps21: ps2@01c2a400 { + ps21: ps2@1c2a400 { compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a400 0x400>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 7>; + clocks = <&ccu CLK_APB1_PS21>; status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 0>; + clocks = <&ccu CLK_APB1_I2C0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 1>; + clocks = <&ccu CLK_APB1_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 2>; + clocks = <&ccu CLK_APB1_I2C2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c3: i2c@01c2b800 { + i2c3: i2c@1c2b800 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b800 0x400>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 3>; + clocks = <&ccu CLK_APB1_I2C3>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - can0: can@01c2bc00 { + can0: can@1c2bc00 { compatible = "allwinner,sun7i-a20-can", "allwinner,sun4i-a10-can"; reg = <0x01c2bc00 0x400>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 4>; + clocks = <&ccu CLK_APB1_CAN>; status = "disabled"; }; - i2c4: i2c@01c2c000 { + i2c4: i2c@1c2c000 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2c000 0x400>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 15>; + clocks = <&ccu CLK_APB1_I2C4>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - gmac: ethernet@01c50000 { + gmac: ethernet@1c50000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x01c50000 0x10000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; - clocks = <&ahb_gates 49>, <&gmac_tx_clk>; + clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; clock-names = "stmmaceth", "allwinner_gmac_tx"; snps,pbl = <2>; snps,fixed-burst; @@ -1632,17 +1232,17 @@ #size-cells = <0>; }; - hstimer@01c60000 { + hstimer@1c60000 { compatible = "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 28>; + clocks = <&ccu CLK_AHB_HSTIMER>; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, @@ -1653,5 +1253,164 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun7i-a20-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_DRAM_DE_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; + }; + + fe1: display-frontend@1e20000 { + compatible = "allwinner,sun7i-a20-display-frontend"; + reg = <0x01e20000 0x20000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, + <&ccu CLK_DRAM_DE_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe1>; + }; + + fe1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe1>; + }; + }; + }; + }; + + be1: display-backend@1e40000 { + compatible = "allwinner,sun7i-a20-display-backend"; + reg = <0x01e40000 0x10000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, + <&ccu CLK_DRAM_DE_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be1>; + }; + + be1_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be1>; + }; + }; + + be1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon1_in_be0>; + }; + + be1_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be1>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + compatible = "allwinner,sun7i-a20-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_DRAM_DE_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + + be0_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + + be0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be0>; + }; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index ea50dda75adc..971f9be699a7 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -118,13 +118,13 @@ }; }; - soc@01c00000 { + soc@1c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun8i-a23-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -133,7 +133,7 @@ #dma-cells = <1>; }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_BUS_MMC0>, @@ -152,7 +152,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ccu CLK_BUS_MMC1>, @@ -171,7 +171,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ccu CLK_BUS_MMC2>, @@ -190,7 +190,7 @@ #size-cells = <0>; }; - nfc: nand@01c03000 { + nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; @@ -203,7 +203,7 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + usb_otg: usb@1c19000 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c19000 0x0400>; clocks = <&ccu CLK_BUS_OTG>; @@ -216,7 +216,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { /* * compatible and address regions get set in * SoC specific dtsi file @@ -233,7 +233,7 @@ #phy-cells = <1>; }; - ehci0: usb@01c1a000 { + ehci0: usb@1c1a000 { compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; @@ -244,7 +244,7 @@ status = "disabled"; }; - ohci0: usb@01c1a400 { + ohci0: usb@1c1a400 { compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; @@ -255,7 +255,7 @@ status = "disabled"; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; @@ -263,7 +263,7 @@ #reset-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>; /* interrupts get set in SoC specific dtsi file */ @@ -344,7 +344,7 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -352,13 +352,13 @@ clocks = <&osc24M>; }; - wdt0: watchdog@01c20ca0 { + wdt0: watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; }; - pwm: pwm@01c21400 { + pwm: pwm@1c21400 { compatible = "allwinner,sun7i-a20-pwm"; reg = <0x01c21400 0xc>; clocks = <&osc24M>; @@ -366,14 +366,14 @@ status = "disabled"; }; - lradc: lradc@01c22800 { + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -386,7 +386,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -399,7 +399,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -412,7 +412,7 @@ status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -425,7 +425,7 @@ status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -438,7 +438,7 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -449,7 +449,7 @@ #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -460,7 +460,7 @@ #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -498,7 +498,7 @@ assigned-clock-rates = <384000000>; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, @@ -509,7 +509,7 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; - rtc: rtc@01f00000 { + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, @@ -527,7 +527,7 @@ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; - prcm@01f01400 { + prcm@1f01400 { compatible = "allwinner,sun8i-a23-prcm"; reg = <0x01f01400 0x200>; @@ -575,12 +575,12 @@ }; }; - cpucfg@01f01c00 { + cpucfg@1f01c00 { compatible = "allwinner,sun8i-a23-cpuconfig"; reg = <0x01f01c00 0x300>; }; - r_uart: serial@01f02800 { + r_uart: serial@1f02800 { compatible = "snps,dw-apb-uart"; reg = <0x01f02800 0x400>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -591,7 +591,7 @@ status = "disabled"; }; - r_pio: pinctrl@01f02c00 { + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-a23-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -618,7 +618,7 @@ }; }; - r_rsb: rsb@01f03400 { + r_rsb: rsb@1f03400 { compatible = "allwinner,sun8i-a23-rsb"; reg = <0x01f03400 0x400>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 4d1f929780a8..58e6585b504b 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -49,8 +49,8 @@ reg = <0x40000000 0x40000000>; }; - soc@01c00000 { - codec: codec@01c22c00 { + soc@1c00000 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-a23-codec"; reg = <0x01c22c00 0x400>; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 22660919bd08..50eb84fa246a 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -203,8 +203,8 @@ }; }; - soc@01c00000 { - tcon0: lcd-controller@01c0c000 { + soc@1c00000 { + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun8i-a33-tcon"; reg = <0x01c0c000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; @@ -240,7 +240,7 @@ }; }; - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; @@ -250,7 +250,7 @@ reset-names = "ahb"; }; - dai: dai@01c22c00 { + dai: dai@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun6i-a31-i2s"; reg = <0x01c22c00 0x200>; @@ -263,7 +263,7 @@ status = "disabled"; }; - codec: codec@01c22e00 { + codec: codec@1c22e00 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x400>; @@ -273,14 +273,14 @@ status = "disabled"; }; - ths: ths@01c25000 { + ths: ths@1c25000 { compatible = "allwinner,sun8i-a33-ths"; reg = <0x01c25000 0x100>; #thermal-sensor-cells = <0>; #io-channel-cells = <0>; }; - fe0: display-frontend@01e00000 { + fe0: display-frontend@1e00000 { compatible = "allwinner,sun8i-a33-display-frontend"; reg = <0x01e00000 0x20000>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; @@ -308,7 +308,7 @@ }; }; - be0: display-backend@01e60000 { + be0: display-backend@1e60000 { compatible = "allwinner,sun8i-a33-display-backend"; reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; reg-names = "be", "sat"; @@ -350,7 +350,7 @@ }; }; - drc0: drc@01e70000 { + drc0: drc@1e70000 { compatible = "allwinner,sun8i-a33-drc"; reg = <0x01e70000 0x10000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index 1f0d60afb25b..5091cecbcd1e 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -43,7 +43,8 @@ /dts-v1/; #include "sun8i-a83t.dtsi" -#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> / { model = "Allwinner A83T H8Homlet Proto Dev Board v2.0"; @@ -56,6 +57,26 @@ chosen { stdout-path = "serial0:115200n8"; }; + + reg_usb0_vbus: reg-usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + }; + + reg_usb1_vbus: reg-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + }; }; &ehci0 { @@ -65,7 +86,7 @@ &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v0>; + vmmc-supply = <®_dcdc1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ bus-width = <4>; cd-inverted; @@ -75,7 +96,8 @@ &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_emmc_pins>; - vmmc-supply = <®_vcc3v0>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; bus-width = <8>; non-removable; cap-mmc-hw-reset; @@ -86,16 +108,6 @@ status = "okay"; }; -®_usb0_vbus { - gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - status = "okay"; -}; - &r_rsb { status = "okay"; @@ -104,6 +116,8 @@ reg = <0x3a3>; interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + swin-supply = <®_dcdc1>; }; ac100: codec@e89 { @@ -131,6 +145,113 @@ }; }; +#include "axp81x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dram-pll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-sys"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-mipi"; +}; + +®_dldo4 { + /* + * The PHY requires 20ms after all voltages are applied until core + * logic is ready and 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ephy"; +}; + +®_fldo1 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd12-hsic"; +}; + +®_fldo2 { + /* + * Despite the embedded CPUs core not being used in any way, + * this must remain on or the system will hang. + */ + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +®_sw { + regulator-name = "vcc-wifi"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts index 2bafd7e99ef7..c606af3dbfed 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -44,7 +44,6 @@ /dts-v1/; #include "sun8i-a83t.dtsi" -#include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -59,6 +58,27 @@ chosen { stdout-path = "serial0:115200n8"; }; + + reg_usb1_vbus: reg-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* The WiFi low power clock must be 32768 Hz */ + assigned-clocks = <&ac100_rtc 1>; + assigned-clock-rates = <32768>; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; }; &ehci0 { @@ -71,17 +91,35 @@ &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ cd-inverted; status = "okay"; }; +&mmc1 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_emmc_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; bus-width = <8>; non-removable; cap-mmc-hw-reset; @@ -96,6 +134,10 @@ reg = <0x3a3>; interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + fldoin-supply = <®_dcdc5>; + swin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; }; ac100: codec@e89 { @@ -123,17 +165,126 @@ }; }; -®_usb1_vbus { - gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ +#include "axp81x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dram-pll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + /* schematics says 3.1V but FEX file says 3.3V */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + /* + * This powers both the WiFi/BT module's main power, I/O supply, + * and external pull-ups on all the data lines. It should be set + * to the same voltage as the I/O supply (DCDC1 in this case) to + * avoid any leakage or mismatch. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pd"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; status = "okay"; }; -®_vcc3v0 { - status = "disabled"; +®_fldo1 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd12-hsic"; +}; + +®_fldo2 { + /* + * Despite the embedded CPUs core not being used in any way, + * this must remain on or the system will hang. + */ + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; }; -®_vcc5v0 { - status = "disabled"; +®_sw { + /* + * The PHY requires 20ms after all voltages + * are applied until core logic is ready and + * 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC + * ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-name = "vcc-ephy"; }; &uart0 { diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index 716a205c6dbb..7f0a3f6d0cf2 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -44,7 +44,6 @@ /dts-v1/; #include "sun8i-a83t.dtsi" -#include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -95,6 +94,26 @@ refclk-frequency = <19200000>; }; + reg_usb1_vbus: reg-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */ + }; + + reg_usb2_vbus: reg-usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb2-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "On-board SPDIF"; @@ -112,6 +131,17 @@ #sound-dai-cells = <0>; compatible = "linux,spdif-dit"; }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* The WiFi low power clock must be 32768 Hz */ + assigned-clocks = <&ac100_rtc 1>; + assigned-clock-rates = <32768>; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; }; &ehci0 { @@ -127,17 +157,26 @@ &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ cd-inverted; status = "okay"; }; +&mmc1 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_sw>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_emmc_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; bus-width = <8>; non-removable; cap-mmc-hw-reset; @@ -152,6 +191,9 @@ reg = <0x3a3>; interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + swin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; }; ac100: codec@e89 { @@ -179,22 +221,143 @@ }; }; -®_usb1_vbus { - gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */ - status = "okay"; +#include "axp81x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dram-pll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; }; -®_usb2_vbus { - gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ +®_dcdc1 { + /* + * The schematics say this should be 3.3V, but the FEX file says + * it should be 3V. The latter makes sense, as the WiFi module's + * I/O is indirectly powered from DCDC1, through SW. It is rated + * at 2.98V maximum. + */ + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-sys"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "dp-pwr"; +}; + +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "ephy-io"; +}; + +®_dldo4 { + /* + * The PHY requires 20ms after all voltages are applied until core + * logic is ready and 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ephy"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; status = "okay"; }; -®_vcc3v0 { - status = "disabled"; +®_eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "dp-bridge-1"; +}; + +®_eldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "dp-bridge-2"; +}; + +®_fldo1 { + /* TODO should be handled by USB PHY */ + regulator-always-on; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd12-hsic"; +}; + +®_fldo2 { + /* + * Despite the embedded CPUs core not being used in any way, + * this must remain on or the system will hang. + */ + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; }; -®_vcc5v0 { - status = "disabled"; +®_sw { + regulator-name = "vcc-wifi-io"; }; &spdif { diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts new file mode 100644 index 000000000000..98715538932f --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -0,0 +1,349 @@ +/* + * Copyright (C) 2017 Touchless Biometric Systems AG + * Tomas Novotny <tomas@novotny.cz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a83t.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "TBS A711 Tablet"; + compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vbat: reg-vbat { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + reg_vmain: reg-vmain { + compatible = "regulator-fixed"; + regulator-name = "vmain"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vbat>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + + /* + * This is actually Bluetooth's clock, but we have to + * hook it up somewheere + */ + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + }; +}; + +/* + * An USB-2 hub is connected here, which also means we don't need to + * enable the OHCI controller. + */ +&ehci0 { + status = "okay"; +}; + +/* + * There's a modem connected here that needs to be initialised before + * being able to be enumerated. + */ +&ehci1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc1 { + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_dldo1>; + non-removable; + wakeup-source; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 WL_WAKE_UP */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-0 = <&mmc2_8bit_emmc_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp81x: pmic@3a3 { + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + swin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 12 IRQ_TYPE_LEVEL_LOW>; /* PL12 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; + +}; + +#include "axp81x.dtsi" + +®_aldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1.8"; +}; + +®_aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-name = "vdd-drampll"; +}; + +®_aldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + regulator-name = "vcc-io"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-name = "vdd-cpu-A"; +}; + +®_dcdc3 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-name = "vdd-cpu-B"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <4200000>; + regulator-name = "vcc-mipi"; +}; + +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-csi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-csi-r"; +}; + +®_eldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dsi"; +}; + +®_eldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-csi-f"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-hsic"; +}; + +®_fldo2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-name = "vdd-cpus"; +}; + +®_ldo_io0 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-ctp"; + status = "okay"; +}; + +®_ldo_io1 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-vb"; + status = "okay"; +}; + +®_sw { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-lcd"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +/* There's the BT part of the AP6210 connected to that UART */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus_supply = <®_vmain>; + usb2_vbus_supply = <®_vmain>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index f996bd343e50..19acae1b4089 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -54,12 +54,6 @@ #address-cells = <1>; #size-cells = <1>; - aliases { - }; - - chosen { - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -218,6 +212,8 @@ resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -242,7 +238,7 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-a83t-musb", "allwinner,sun8i-a33-musb"; reg = <0x01c19000 0x0400>; @@ -348,6 +344,14 @@ bias-pull-up; }; + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", @@ -371,6 +375,16 @@ pins = "PF2", "PF4"; function = "uart0"; }; + + uart1_pins: uart1-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + uart1_rts_cts_pins: uart1-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; }; timer@1c20c00 { @@ -404,7 +418,7 @@ status = "disabled"; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -415,6 +429,17 @@ status = "disabled"; }; + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts index b1502df7b509..6713d0f2b3f4 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts @@ -56,6 +56,8 @@ aliases { serial0 = &uart0; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &xr819; }; @@ -102,6 +104,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index a337af1de322..f2292deaa590 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -52,6 +52,7 @@ compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -63,7 +64,6 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&pwr_led_bpi_m2p>; pwr_led { label = "bananapi-m2-plus:red:pwr"; @@ -75,7 +75,6 @@ gpio_keys { compatible = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <&sw_r_bpi_m2p>; sw4 { label = "power"; @@ -97,7 +96,6 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; - pinctrl-0 = <&wifi_en_bpi_m2p>; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ }; }; @@ -114,6 +112,24 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -171,23 +187,6 @@ status = "okay"; }; -&r_pio { - pwr_led_bpi_m2p: led_pins@0 { - pins = "PL10"; - function = "gpio_out"; - }; - - sw_r_bpi_m2p: key_pins@0 { - pins = "PL3"; - function = "gpio_in"; - }; - - wifi_en_bpi_m2p: wifi_en_pin { - pins = "PL7"; - function = "gpio_out"; - }; -}; - ®_usb0_vbus { gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */ status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts index 8ddd1b2cc097..0a8b79cf5954 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts @@ -45,6 +45,27 @@ / { model = "FriendlyArm NanoPi M1 Plus"; compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3"; + + aliases { + serial1 = &uart3; + ethernet1 = &sdio_wifi; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + }; }; &ehci1 { @@ -55,6 +76,50 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: sdio_wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + &ohci1 { status = "okay"; }; @@ -62,3 +127,9 @@ &ohci2 { status = "okay"; }; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts index ec63d104b404..3a2ccdb28afd 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts @@ -55,6 +55,12 @@ status = "okay"; }; +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + &ohci1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts index 8d2cc6e9a03f..78f6c24952dd 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts @@ -46,3 +46,10 @@ model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; }; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi index c6decee41a27..7646e331bd29 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -81,7 +81,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sw_r_npi>; - k1@0 { + k1 { label = "k1"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -108,19 +108,19 @@ }; &pio { - leds_npi: led_pins@0 { + leds_npi: led_pins { pins = "PA10"; function = "gpio_out"; }; }; &r_pio { - leds_r_npi: led_pins@0 { + leds_r_npi: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_npi: key_pins@0 { + sw_r_npi: key_pins { pins = "PL3"; function = "gpio_in"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 8ff71b1bb45b..b20be95b49d5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -54,6 +54,7 @@ aliases { serial0 = &uart0; /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &rtl8189; }; @@ -117,6 +118,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -152,24 +160,24 @@ }; &pio { - leds_opc: led_pins@0 { + leds_opc: led_pins { pins = "PA15"; function = "gpio_out"; }; }; &r_pio { - leds_r_opc: led_pins@0 { + leds_r_opc: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_opc: key_pins@0 { + sw_r_opc: key_pins { pins = "PL3", "PL4"; function = "gpio_in"; }; - wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin@0 { + wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin { pins = "PL7"; function = "gpio_out"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts index 9b47a0def740..a70a1daf4e2c 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts @@ -141,19 +141,19 @@ }; &pio { - leds_opc: led_pins@0 { + leds_opc: led_pins { pins = "PA15"; function = "gpio_out"; }; }; &r_pio { - leds_r_opc: led_pins@0 { + leds_r_opc: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_opc: key_pins@0 { + sw_r_opc: key_pins { pins = "PL3"; function = "gpio_in"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 5fea430e0eb1..82e5d28cd698 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -97,6 +98,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; @@ -116,19 +124,19 @@ }; &pio { - leds_opc: led_pins@0 { + leds_opc: led_pins { pins = "PA15"; function = "gpio_out"; }; }; &r_pio { - leds_r_opc: led_pins@0 { + leds_r_opc: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_opc: key_pins@0 { + sw_r_opc: key_pins { pins = "PL3"; function = "gpio_in"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts index 8b93f5c781a7..a10281b455f5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts @@ -53,6 +53,11 @@ }; }; +&emac { + /* LEDs changed to active high on the plus */ + /delete-property/ allwinner,leds-active-low; +}; + &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index 1a044b17d6c6..d22546df1b82 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -113,6 +114,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -146,19 +154,19 @@ }; &pio { - leds_opc: led_pins@0 { + leds_opc: led_pins { pins = "PA15"; function = "gpio_out"; }; }; &r_pio { - leds_r_opc: led_pins@0 { + leds_r_opc: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_opc: key_pins@0 { + sw_r_opc: key_pins { pins = "PL3"; function = "gpio_in"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index 828ae7a526d9..cbc499b04de4 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -47,6 +47,10 @@ model = "Xunlong Orange Pi Plus / Plus 2"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + aliases { + ethernet0 = &emac; + }; + reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; regulator-name = "gmac-3v3"; @@ -74,6 +78,24 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; @@ -92,7 +114,7 @@ }; &pio { - usb3_vbus_pin_a: usb3_vbus_pin@0 { + usb3_vbus_pin_a: usb3_vbus_pin { pins = "PG11"; function = "gpio_out"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts index 97920b12a944..6dbf7b2e0c13 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts @@ -61,3 +61,19 @@ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ }; }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts new file mode 100644 index 000000000000..8c5efe2a9881 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-r40.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Banana Pi BPI-M2-Ultra"; + compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr-led { + label = "bananapi:red:pwr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led-green { + label = "bananapi:green:user"; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; + }; + + user-led-blue { + label = "bananapi:blue:user"; + gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo2>; + vqmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi new file mode 100644 index 000000000000..173dcc1652d2 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -0,0 +1,473 @@ +/* + * Copyright 2017 Chen-Yu Tsai <wens@csie.org> + * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun8i-r40-ccu.h> +#include <dt-bindings/reset/sun8i-r40-ccu.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + nmi_intc: interrupt-controller@1c00030 { + compatible = "allwinner,sun7i-a20-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun8i-r40-emmc", + "allwinner,sun50i-a64-emmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + pinctrl-0 = <&mmc2_pins>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc3: mmc@1c12000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC3>; + reset-names = "ahb"; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbphy: phy@1c13400 { + compatible = "allwinner,sun8i-r40-usb-phy"; + reg = <0x01c13400 0x14>, + <0x01c14800 0x4>, + <0x01c19800 0x4>, + <0x01c1c800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@1c19000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c19000 0x100>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI1>; + resets = <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c19400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c19400 0x100>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@1c1c000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI2>; + resets = <&ccu RST_BUS_EHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@1c1c400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_BUS_OHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,sun8i-r40-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun8i-r40-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + i2c0_pins: i2c0-pins { + pins = "PB0", "PB1"; + function = "i2c0"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc1_pg_pins: mmc1-pg-pins { + pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins = "PC5", "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", "PC14", + "PC15", "PC24"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB22", "PB23"; + function = "uart0"; + }; + }; + + wdt: watchdog@1c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + uart5: serial@1c29400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29400 0x400>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + status = "disabled"; + }; + + uart6: serial@1c29800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29800 0x400>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART6>; + resets = <&ccu RST_BUS_UART6>; + status = "disabled"; + }; + + uart7: serial@1c29c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29c00 0x400>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART7>; + resets = <&ccu RST_BUS_UART7>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@1c2b800 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b800 0x400>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4: i2c@1c2c000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2c000 0x400>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C4>; + resets = <&ccu RST_BUS_I2C4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 3a06dc5b3746..443b083c6adc 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -178,7 +178,7 @@ }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_BUS_MMC0>, @@ -197,7 +197,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ccu CLK_BUS_MMC1>, @@ -218,7 +218,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ccu CLK_BUS_MMC2>, @@ -237,7 +237,7 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x0400>; clocks = <&ccu CLK_BUS_OTG>; @@ -250,7 +250,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { compatible = "allwinner,sun8i-v3s-usb-phy"; reg = <0x01c19400 0x2c>, <0x01c1a800 0x4>; @@ -264,7 +264,7 @@ #phy-cells = <1>; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; @@ -273,14 +273,14 @@ #reset-cells = <1>; }; - rtc: rtc@01c20400 { + rtc: rtc@1c20400 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01c20400 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { compatible = "allwinner,sun8i-v3s-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, @@ -324,7 +324,7 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -332,7 +332,7 @@ clocks = <&osc24M>; }; - wdt0: watchdog@01c20ca0 { + wdt0: watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; @@ -345,7 +345,7 @@ status = "disabled"; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -356,7 +356,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -367,7 +367,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -378,7 +378,7 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -391,7 +391,7 @@ #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -416,7 +416,7 @@ #size-cells = <0>; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, <0x01c82000 0x1000>, diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts new file mode 100644 index 000000000000..fe16fc0eb518 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-r40.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Banana Pi M2 Berry"; + compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr-led { + label = "bananapi:red:pwr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led { + label = "bananapi:green:user"; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ + }; +}; + +&i2c0 { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo2>; + vqmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 3741ac71c3d6..4024639aa005 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -62,8 +62,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cubieboard4>; green { label = "cubieboard4:green:usr"; @@ -76,7 +74,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&ac100_rtc 1>; clock-names = "ext_clock"; @@ -87,7 +85,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_cubieboard4>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */ @@ -97,7 +95,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>, <&wifi_en_pin_cubieboard4>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_dldo1>; vqmmc-supply = <®_cldo3>; mmc-pwrseq = <&wifi_pwrseq>; @@ -130,30 +128,10 @@ clocks = <&ac100_rtc 0>; }; -&pio { - led_pins_cubieboard4: led-pins@0 { - pins = "PH6", "PH17"; - function = "gpio_out"; - }; - - mmc0_cd_pin_cubieboard4: mmc0_cd_pin@0 { - pins = "PH18"; - function = "gpio_in"; - bias-pull-up; - }; -}; - &r_ir { status = "okay"; }; -&r_pio { - wifi_en_pin_cubieboard4: wifi_en_pin@0 { - pins = "PL2"; - function = "gpio_out"; - }; -}; - &r_rsb { status = "okay"; @@ -427,6 +405,6 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 85f1ad670310..a9b807be99a0 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -62,11 +62,8 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_optimus>, <&led_r_pins_optimus>; /* The LED names match those found on the board */ - led2 { label = "optimus:led2:usr"; gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; @@ -86,8 +83,6 @@ reg_usb1_vbus: usb1-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_optimus>; - regulator-name = "usb1-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; @@ -97,15 +92,13 @@ reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&usb3_vbus_pin_optimus>; - regulator-name = "usb3-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&ac100_rtc 1>; clock-names = "ext_clock"; @@ -129,7 +122,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_optimus>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */ @@ -139,7 +132,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>, <&wifi_en_pin_optimus>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_dldo1>; vqmmc-supply = <®_cldo3>; mmc-pwrseq = <&wifi_pwrseq>; @@ -180,45 +173,10 @@ clocks = <&ac100_rtc 0>; }; -&pio { - led_pins_optimus: led-pins@0 { - pins = "PH0", "PH1"; - function = "gpio_out"; - }; - - mmc0_cd_pin_optimus: mmc0_cd_pin@0 { - pins = "PH18"; - function = "gpio_in"; - bias-pull-up; - }; - - usb1_vbus_pin_optimus: usb1_vbus_pin@1 { - pins = "PH4"; - function = "gpio_out"; - }; - - usb3_vbus_pin_optimus: usb3_vbus_pin@1 { - pins = "PH5"; - function = "gpio_out"; - }; -}; - &r_ir { status = "okay"; }; -&r_pio { - led_r_pins_optimus: led-pins@1 { - pins = "PM15"; - function = "gpio_out"; - }; - - wifi_en_pin_optimus: wifi_en_pin@0 { - pins = "PL2"; - function = "gpio_out"; - }; -}; - &r_rsb { status = "okay"; @@ -492,7 +450,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 759a72317eb8..90eac0b2a193 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -42,8 +42,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton64.dtsi" - #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun9i-a80-ccu.h> @@ -54,6 +52,8 @@ #include <dt-bindings/reset/sun9i-a80-usb.h> / { + #address-cells = <2>; + #size-cells = <2>; interrupt-parent = <&gic>; cpus { @@ -109,11 +109,6 @@ }; }; - memory { - /* 8GB max. with LPAE */ - reg = <0 0x20000000 0x02 0>; - }; - timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -144,7 +139,7 @@ * would also throw all the PLL clock rates off, or just the * downstream clocks in the PRCM. */ - osc24M: osc24M_clk { + osc24M: clk-24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -156,7 +151,7 @@ * AC100 codec/RTC chip. This serves as a placeholder for * board dts files to specify the source. */ - osc32k: osc32k_clk { + osc32k: clk-32k { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <1>; @@ -164,7 +159,7 @@ clock-output-names = "osc32k"; }; - cpus_clk: clk@08001410 { + cpus_clk: clk@8001410 { compatible = "allwinner,sun9i-a80-cpus-clk"; reg = <0x08001410 0x4>; #clock-cells = <0>; @@ -174,7 +169,7 @@ clock-output-names = "cpus"; }; - ahbs: ahbs_clk { + ahbs: clk-ahbs { compatible = "fixed-factor-clock"; #clock-cells = <0>; clock-div = <1>; @@ -183,7 +178,7 @@ clock-output-names = "ahbs"; }; - apbs: clk@0800141c { + apbs: clk@800141c { compatible = "allwinner,sun8i-a23-apb0-clk"; reg = <0x0800141c 0x4>; #clock-cells = <0>; @@ -191,7 +186,7 @@ clock-output-names = "apbs"; }; - apbs_gates: clk@08001428 { + apbs_gates: clk@8001428 { compatible = "allwinner,sun9i-a80-apbs-gates-clk"; reg = <0x08001428 0x4>; #clock-cells = <1>; @@ -212,7 +207,7 @@ "apbs_i2s1", "apbs_twd"; }; - r_1wire_clk: clk@08001450 { + r_1wire_clk: clk@8001450 { reg = <0x08001450 0x4>; #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; @@ -220,7 +215,7 @@ clock-output-names = "r_1wire"; }; - r_ir_clk: clk@08001454 { + r_ir_clk: clk@8001454 { reg = <0x08001454 0x4>; #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; @@ -239,7 +234,7 @@ */ ranges = <0 0 0 0x20000000>; - ehci0: usb@00a00000 { + ehci0: usb@a00000 { compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; reg = <0x00a00000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; @@ -250,7 +245,7 @@ status = "disabled"; }; - ohci0: usb@00a00400 { + ohci0: usb@a00400 { compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; reg = <0x00a00400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; @@ -262,7 +257,7 @@ status = "disabled"; }; - usbphy1: phy@00a00800 { + usbphy1: phy@a00800 { compatible = "allwinner,sun9i-a80-usb-phy"; reg = <0x00a00800 0x4>; clocks = <&usb_clocks CLK_USB0_PHY>; @@ -273,7 +268,7 @@ #phy-cells = <0>; }; - ehci1: usb@00a01000 { + ehci1: usb@a01000 { compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; reg = <0x00a01000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; @@ -284,7 +279,7 @@ status = "disabled"; }; - usbphy2: phy@00a01800 { + usbphy2: phy@a01800 { compatible = "allwinner,sun9i-a80-usb-phy"; reg = <0x00a01800 0x4>; clocks = <&usb_clocks CLK_USB1_HSIC>, @@ -303,7 +298,7 @@ phy_type = "hsic"; }; - ehci2: usb@00a02000 { + ehci2: usb@a02000 { compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; reg = <0x00a02000 0x100>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; @@ -314,7 +309,7 @@ status = "disabled"; }; - ohci2: usb@00a02400 { + ohci2: usb@a02400 { compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; reg = <0x00a02400 0x100>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; @@ -326,7 +321,7 @@ status = "disabled"; }; - usbphy3: phy@00a02800 { + usbphy3: phy@a02800 { compatible = "allwinner,sun9i-a80-usb-phy"; reg = <0x00a02800 0x4>; clocks = <&usb_clocks CLK_USB2_HSIC>, @@ -343,7 +338,7 @@ #phy-cells = <0>; }; - usb_clocks: clock@00a08000 { + usb_clocks: clock@a08000 { compatible = "allwinner,sun9i-a80-usb-clks"; reg = <0x00a08000 0x8>; clocks = <&ccu CLK_BUS_USB>, <&osc24M>; @@ -352,7 +347,7 @@ #reset-cells = <1>; }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>, @@ -367,7 +362,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c10000 0x1000>; clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>, @@ -382,7 +377,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c11000 0x1000>; clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>, @@ -397,7 +392,7 @@ #size-cells = <0>; }; - mmc3: mmc@01c12000 { + mmc3: mmc@1c12000 { compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c12000 0x1000>; clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>, @@ -412,7 +407,7 @@ #size-cells = <0>; }; - mmc_config_clk: clk@01c13000 { + mmc_config_clk: clk@1c13000 { compatible = "allwinner,sun9i-a80-mmc-config-clk"; reg = <0x01c13000 0x10>; clocks = <&ccu CLK_BUS_MMC>; @@ -425,7 +420,7 @@ "mmc2_config", "mmc3_config"; }; - gic: interrupt-controller@01c41000 { + gic: interrupt-controller@1c41000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c41000 0x1000>, <0x01c42000 0x2000>, @@ -436,7 +431,7 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; - de_clocks: clock@03000000 { + de_clocks: clock@3000000 { compatible = "allwinner,sun9i-a80-de-clks"; reg = <0x03000000 0x30>; clocks = <&ccu CLK_DE>, @@ -450,7 +445,7 @@ #reset-cells = <1>; }; - ccu: clock@06000000 { + ccu: clock@6000000 { compatible = "allwinner,sun9i-a80-ccu"; reg = <0x06000000 0x800>; clocks = <&osc24M>, <&osc32k>; @@ -459,7 +454,7 @@ #reset-cells = <1>; }; - timer@06000c00 { + timer@6000c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x06000c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -472,13 +467,13 @@ clocks = <&osc24M>; }; - wdt: watchdog@06000ca0 { + wdt: watchdog@6000ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x06000ca0 0x20>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; }; - pio: pinctrl@06000800 { + pio: pinctrl@6000800 { compatible = "allwinner,sun9i-a80-pinctrl"; reg = <0x06000800 0x400>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -494,12 +489,12 @@ #size-cells = <0>; #gpio-cells = <3>; - i2c3_pins_a: i2c3@0 { + i2c3_pins: i2c3-pins { pins = "PG10", "PG11"; function = "i2c3"; }; - mmc0_pins: mmc0 { + mmc0_pins: mmc0-pins { pins = "PF0", "PF1" ,"PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -507,7 +502,7 @@ bias-pull-up; }; - mmc1_pins: mmc1 { + mmc1_pins: mmc1-pins { pins = "PG0", "PG1" ,"PG2", "PG3", "PG4", "PG5"; function = "mmc1"; @@ -515,7 +510,7 @@ bias-pull-up; }; - mmc2_8bit_pins: mmc2_8bit { + mmc2_8bit_pins: mmc2-8bit-pins { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", @@ -525,18 +520,18 @@ bias-pull-up; }; - uart0_pins_a: uart0@0 { + uart0_ph_pins: uart0-ph-pins { pins = "PH12", "PH13"; function = "uart0"; }; - uart4_pins_a: uart4@0 { + uart4_pins: uart4-pins { pins = "PG12", "PG13", "PG14", "PG15"; function = "uart4"; }; }; - uart0: serial@07000000 { + uart0: serial@7000000 { compatible = "snps,dw-apb-uart"; reg = <0x07000000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -547,7 +542,7 @@ status = "disabled"; }; - uart1: serial@07000400 { + uart1: serial@7000400 { compatible = "snps,dw-apb-uart"; reg = <0x07000400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -558,7 +553,7 @@ status = "disabled"; }; - uart2: serial@07000800 { + uart2: serial@7000800 { compatible = "snps,dw-apb-uart"; reg = <0x07000800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -569,7 +564,7 @@ status = "disabled"; }; - uart3: serial@07000c00 { + uart3: serial@7000c00 { compatible = "snps,dw-apb-uart"; reg = <0x07000c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -580,7 +575,7 @@ status = "disabled"; }; - uart4: serial@07001000 { + uart4: serial@7001000 { compatible = "snps,dw-apb-uart"; reg = <0x07001000 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -591,7 +586,7 @@ status = "disabled"; }; - uart5: serial@07001400 { + uart5: serial@7001400 { compatible = "snps,dw-apb-uart"; reg = <0x07001400 0x400>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; @@ -602,7 +597,7 @@ status = "disabled"; }; - i2c0: i2c@07002800 { + i2c0: i2c@7002800 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07002800 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -613,7 +608,7 @@ #size-cells = <0>; }; - i2c1: i2c@07002c00 { + i2c1: i2c@7002c00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07002c00 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -624,7 +619,7 @@ #size-cells = <0>; }; - i2c2: i2c@07003000 { + i2c2: i2c@7003000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07003000 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -635,7 +630,7 @@ #size-cells = <0>; }; - i2c3: i2c@07003400 { + i2c3: i2c@7003400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07003400 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; @@ -646,7 +641,7 @@ #size-cells = <0>; }; - i2c4: i2c@07003800 { + i2c4: i2c@7003800 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07003800 0x400>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; @@ -657,19 +652,19 @@ #size-cells = <0>; }; - r_wdt: watchdog@08001000 { + r_wdt: watchdog@8001000 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x08001000 0x20>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; }; - apbs_rst: reset@080014b0 { + apbs_rst: reset@80014b0 { reg = <0x080014b0 0x4>; compatible = "allwinner,sun6i-a31-clock-reset"; #reset-cells = <1>; }; - nmi_intc: interrupt-controller@080015a0 { + nmi_intc: interrupt-controller@80015a0 { compatible = "allwinner,sun9i-a80-nmi"; interrupt-controller; #interrupt-cells = <2>; @@ -677,7 +672,7 @@ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; - r_ir: ir@08002000 { + r_ir: ir@8002000 { compatible = "allwinner,sun5i-a13-ir"; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; @@ -689,7 +684,7 @@ status = "disabled"; }; - r_uart: serial@08002800 { + r_uart: serial@8002800 { compatible = "snps,dw-apb-uart"; reg = <0x08002800 0x400>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -700,7 +695,7 @@ status = "disabled"; }; - r_pio: pinctrl@08002c00 { + r_pio: pinctrl@8002c00 { compatible = "allwinner,sun9i-a80-r-pinctrl"; reg = <0x08002c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, @@ -713,12 +708,12 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - r_ir_pins: r_ir { + r_ir_pins: r-ir-pins { pins = "PL6"; function = "s_cir_rx"; }; - r_rsb_pins: r_rsb { + r_rsb_pins: r-rsb-pins { pins = "PN0", "PN1"; function = "s_rsb"; drive-strength = <20>; @@ -726,7 +721,7 @@ }; }; - r_rsb: i2c@08003400 { + r_rsb: i2c@8003400 { compatible = "allwinner,sun8i-a23-rsb"; reg = <0x08003400 0x400>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 11240a8313c2..8d40c00d64bb 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -91,7 +91,7 @@ reg = <0x01c00000 0x1000>; }; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun8i-h3-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -100,7 +100,7 @@ #dma-cells = <1>; }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { /* compatible and clocks are in per SoC .dtsi file */ reg = <0x01c0f000 0x1000>; resets = <&ccu RST_BUS_MMC0>; @@ -111,7 +111,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { /* compatible and clocks are in per SoC .dtsi file */ reg = <0x01c10000 0x1000>; resets = <&ccu RST_BUS_MMC1>; @@ -122,7 +122,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { /* compatible and clocks are in per SoC .dtsi file */ reg = <0x01c11000 0x1000>; resets = <&ccu RST_BUS_MMC2>; @@ -133,7 +133,7 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x400>; clocks = <&ccu CLK_BUS_OTG>; @@ -146,7 +146,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { compatible = "allwinner,sun8i-h3-usb-phy"; reg = <0x01c19400 0x2c>, <0x01c1a800 0x4>, @@ -178,7 +178,7 @@ #phy-cells = <1>; }; - ehci0: usb@01c1a000 { + ehci0: usb@1c1a000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; @@ -187,7 +187,7 @@ status = "disabled"; }; - ohci0: usb@01c1a400 { + ohci0: usb@1c1a400 { compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; @@ -197,7 +197,7 @@ status = "disabled"; }; - ehci1: usb@01c1b000 { + ehci1: usb@1c1b000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; @@ -208,7 +208,7 @@ status = "disabled"; }; - ohci1: usb@01c1b400 { + ohci1: usb@1c1b400 { compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; reg = <0x01c1b400 0x100>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; @@ -220,7 +220,7 @@ status = "disabled"; }; - ehci2: usb@01c1c000 { + ehci2: usb@1c1c000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1c000 0x100>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; @@ -231,7 +231,7 @@ status = "disabled"; }; - ohci2: usb@01c1c400 { + ohci2: usb@1c1c400 { compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; @@ -243,7 +243,7 @@ status = "disabled"; }; - ehci3: usb@01c1d000 { + ehci3: usb@1c1d000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1d000 0x100>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; @@ -254,7 +254,7 @@ status = "disabled"; }; - ohci3: usb@01c1d400 { + ohci3: usb@1c1d400 { compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; reg = <0x01c1d400 0x100>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; @@ -266,7 +266,7 @@ status = "disabled"; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { /* compatible is in per SoC .dtsi file */ reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; @@ -275,7 +275,7 @@ #reset-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { /* compatible is in per SoC .dtsi file */ reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -310,7 +310,7 @@ function = "i2c2"; }; - mmc0_pins_a: mmc0@0 { + mmc0_pins_a: mmc0 { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -318,13 +318,13 @@ bias-pull-up; }; - mmc0_cd_pin: mmc0_cd_pin@0 { + mmc0_cd_pin: mmc0_cd_pin { pins = "PF6"; function = "gpio_in"; bias-pull-up; }; - mmc1_pins_a: mmc1@0 { + mmc1_pins_a: mmc1 { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "mmc1"; @@ -342,7 +342,7 @@ bias-pull-up; }; - spdif_tx_pins_a: spdif@0 { + spdif_tx_pins_a: spdif { pins = "PA17"; function = "spdif"; }; @@ -357,7 +357,7 @@ function = "spi1"; }; - uart0_pins_a: uart0@0 { + uart0_pins_a: uart0 { pins = "PA4", "PA5"; function = "uart0"; }; @@ -381,9 +381,14 @@ pins = "PA13", "PA14"; function = "uart3"; }; + + uart3_rts_cts_pins: uart3_rts_cts { + pins = "PA15", "PA16"; + function = "uart3"; + }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -391,7 +396,56 @@ clocks = <&osc24M>; }; - spi0: spi@01c68000 { + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + mdio-parent-bus = <&mdio>; + /* Only one MDIO is usable at the time */ + internal_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + + external_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + spi0: spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; @@ -407,7 +461,7 @@ #size-cells = <0>; }; - spi1: spi@01c69000 { + spi1: spi@1c69000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c69000 0x1000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; @@ -423,13 +477,13 @@ #size-cells = <0>; }; - wdt0: watchdog@01c20ca0 { + wdt0: watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-h3-spdif"; reg = <0x01c21000 0x400>; @@ -442,7 +496,7 @@ status = "disabled"; }; - pwm: pwm@01c21400 { + pwm: pwm@1c21400 { compatible = "allwinner,sun8i-h3-pwm"; reg = <0x01c21400 0x8>; clocks = <&osc24M>; @@ -450,7 +504,33 @@ status = "disabled"; }; - codec: codec@01c22c00 { + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-i2s"; + reg = <0x01c22000 0x400>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + resets = <&ccu RST_BUS_I2S0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + resets = <&ccu RST_BUS_I2S1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-h3-codec"; reg = <0x01c22c00 0x400>; @@ -464,7 +544,7 @@ status = "disabled"; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -477,7 +557,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -490,7 +570,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -503,7 +583,7 @@ status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -516,7 +596,7 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -529,7 +609,7 @@ #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -542,9 +622,9 @@ #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; + reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>; @@ -555,7 +635,7 @@ #size-cells = <0>; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, @@ -566,7 +646,7 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; - rtc: rtc@01f00000 { + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, @@ -583,12 +663,12 @@ #reset-cells = <1>; }; - codec_analog: codec-analog@01f015c0 { + codec_analog: codec-analog@1f015c0 { compatible = "allwinner,sun8i-h3-codec-analog"; reg = <0x01f015c0 0x4>; }; - ir: ir@01f02000 { + ir: ir@1f02000 { compatible = "allwinner,sun5i-a13-ir"; clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; clock-names = "apb", "ir"; @@ -598,7 +678,7 @@ status = "disabled"; }; - r_pio: pinctrl@01f02c00 { + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -609,7 +689,7 @@ interrupt-controller; #interrupt-cells = <3>; - ir_pins_a: ir@0 { + ir_pins_a: ir { pins = "PL11"; function = "s_cir_rx"; }; diff --git a/arch/arm/boot/dts/sunxi-itead-core-common.dtsi b/arch/arm/boot/dts/sunxi-itead-core-common.dtsi index 2565d5137a17..ddf4e722ea93 100644 --- a/arch/arm/boot/dts/sunxi-itead-core-common.dtsi +++ b/arch/arm/boot/dts/sunxi-itead-core-common.dtsi @@ -65,8 +65,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -75,8 +73,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi index 12ab6e0c0331..0ec1b0a317b4 100644 --- a/arch/arm/boot/dts/tango4-common.dtsi +++ b/arch/arm/boot/dts/tango4-common.dtsi @@ -160,7 +160,7 @@ #address-cells = <1>; #size-cells = <1>; - irq0: irq0@000 { + irq0: irq0@0 { reg = <0x000 0x100>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index e8e777b8ef1b..d112f85e66ed 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -68,6 +68,10 @@ }; }; + cec@70015000 { + status = "okay"; + }; + gpu@0,57000000 { /* * Node left disabled on purpose - the bootloader will enable diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index a7e43dcbf744..174092bfac90 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -125,7 +125,7 @@ nvidia,head = <1>; }; - hdmi@54280000 { + hdmi: hdmi@54280000 { compatible = "nvidia,tegra124-hdmi"; reg = <0x0 0x54280000 0x0 0x00040000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; @@ -853,6 +853,16 @@ status = "disabled"; }; + cec@70015000 { + compatible = "nvidia,tegra124-cec"; + reg = <0x0 0x70015000 0x0 0x00001000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_CEC>; + clock-names = "cec"; + status = "disabled"; + hdmi-phandle = <&hdmi>; + }; + soctherm: thermal-sensor@700e2000 { compatible = "nvidia,tegra124-soctherm"; reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts index b3aaab354f3e..0056852c4fb0 100644 --- a/arch/arm/boot/dts/uniphier-ld4-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts @@ -38,7 +38,7 @@ }; ðsc { - interrupts = <0 49 4>; + interrupts = <1 8>; }; &serial0 { @@ -53,6 +53,14 @@ status = "okay"; }; +&gpio { + xirq1 { + gpio-hog; + gpios = <121 0>; + input; + }; +}; + &i2c0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 93586faf950f..01fc3e16e2bd 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -37,7 +37,7 @@ clock-frequency = <24576000>; }; - arm_timer_clk: arm_timer_clk { + arm_timer_clk: arm-timer { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; @@ -71,6 +71,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; }; serial1: serial@54006900 { @@ -81,6 +82,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; }; serial2: serial@54006a00 { @@ -91,6 +93,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; }; serial3: serial@54006b00 { @@ -101,6 +104,21 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <136>; + socionext,interrupt-ranges = <0 48 13>, <14 62 2>; }; i2c0: i2c@58400000 { @@ -113,6 +131,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; clock-frequency = <100000>; }; @@ -126,6 +145,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; clock-frequency = <100000>; }; @@ -139,6 +159,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; clock-frequency = <400000>; }; @@ -152,6 +173,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; clock-frequency = <100000>; }; @@ -305,6 +327,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; clocks = <&sys_clk 2>; + resets = <&sys_rst 2>; }; }; }; diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts index 2188d114d79b..0e510a725976 100644 --- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts @@ -40,7 +40,7 @@ }; ðsc { - interrupts = <0 52 4>; + interrupts = <4 8>; }; &serial0 { @@ -55,6 +55,14 @@ status = "okay"; }; +&gpio { + xirq4 { + gpio-hog; + gpios = <124 0>; + input; + }; +}; + &i2c0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi index be82cddc4072..de481c372467 100644 --- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi @@ -8,117 +8,117 @@ */ &pinctrl { - pinctrl_aout: aout_grp { + pinctrl_aout: aout { groups = "aout"; function = "aout"; }; - pinctrl_emmc: emmc_grp { + pinctrl_emmc: emmc { groups = "emmc", "emmc_dat8"; function = "emmc"; }; - pinctrl_ether_mii: ether_mii_grp { + pinctrl_ether_mii: ether-mii { groups = "ether_mii"; function = "ether_mii"; }; - pinctrl_ether_rgmii: ether_rgmii_grp { + pinctrl_ether_rgmii: ether-rgmii { groups = "ether_rgmii"; function = "ether_rgmii"; }; - pinctrl_ether_rmii: ether_rmii_grp { + pinctrl_ether_rmii: ether-rmii { groups = "ether_rmii"; function = "ether_rmii"; }; - pinctrl_i2c0: i2c0_grp { + pinctrl_i2c0: i2c0 { groups = "i2c0"; function = "i2c0"; }; - pinctrl_i2c1: i2c1_grp { + pinctrl_i2c1: i2c1 { groups = "i2c1"; function = "i2c1"; }; - pinctrl_i2c2: i2c2_grp { + pinctrl_i2c2: i2c2 { groups = "i2c2"; function = "i2c2"; }; - pinctrl_i2c3: i2c3_grp { + pinctrl_i2c3: i2c3 { groups = "i2c3"; function = "i2c3"; }; - pinctrl_i2c4: i2c4_grp { + pinctrl_i2c4: i2c4 { groups = "i2c4"; function = "i2c4"; }; - pinctrl_nand: nand_grp { + pinctrl_nand: nand { groups = "nand"; function = "nand"; }; - pinctrl_nand2cs: nand2cs_grp { + pinctrl_nand2cs: nand2cs { groups = "nand", "nand_cs1"; function = "nand"; }; - pinctrl_sd: sd_grp { + pinctrl_sd: sd { groups = "sd"; function = "sd"; }; - pinctrl_sd1: sd1_grp { + pinctrl_sd1: sd1 { groups = "sd1"; function = "sd1"; }; - pinctrl_system_bus: system_bus_grp { + pinctrl_system_bus: system-bus { groups = "system_bus", "system_bus_cs1"; function = "system_bus"; }; - pinctrl_uart0: uart0_grp { + pinctrl_uart0: uart0 { groups = "uart0"; function = "uart0"; }; - pinctrl_uart1: uart1_grp { + pinctrl_uart1: uart1 { groups = "uart1"; function = "uart1"; }; - pinctrl_uart2: uart2_grp { + pinctrl_uart2: uart2 { groups = "uart2"; function = "uart2"; }; - pinctrl_uart3: uart3_grp { + pinctrl_uart3: uart3 { groups = "uart3"; function = "uart3"; }; - pinctrl_usb0: usb0_grp { + pinctrl_usb0: usb0 { groups = "usb0"; function = "usb0"; }; - pinctrl_usb1: usb1_grp { + pinctrl_usb1: usb1 { groups = "usb1"; function = "usb1"; }; - pinctrl_usb2: usb2_grp { + pinctrl_usb2: usb2 { groups = "usb2"; function = "usb2"; }; - pinctrl_usb3: usb3_grp { + pinctrl_usb3: usb3 { groups = "usb3"; function = "usb3"; }; diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts index 903df6348e77..be99467ac6bb 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ref.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts @@ -40,7 +40,7 @@ }; ðsc { - interrupts = <0 50 4>; + interrupts = <2 8>; }; &serial0 { @@ -55,6 +55,14 @@ status = "okay"; }; +&gpio { + xirq2 { + gpio-hog; + gpios = <122 0>; + input; + }; +}; + &i2c0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index 2a9bd7f9f5db..7955c3a49e65 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -45,7 +45,7 @@ clock-frequency = <25000000>; }; - arm_timer_clk: arm_timer_clk { + arm_timer_clk: arm-timer { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; @@ -79,6 +79,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; }; serial1: serial@54006900 { @@ -89,6 +90,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; }; serial2: serial@54006a00 { @@ -99,6 +101,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; }; serial3: serial@54006b00 { @@ -109,6 +112,21 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <248>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>; }; i2c0: i2c@58780000 { @@ -121,6 +139,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; clock-frequency = <100000>; }; @@ -134,6 +153,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; clock-frequency = <100000>; }; @@ -147,6 +167,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; clock-frequency = <100000>; }; @@ -160,6 +181,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; clock-frequency = <100000>; }; @@ -173,6 +195,7 @@ #size-cells = <0>; interrupts = <0 25 4>; clocks = <&peri_clk 9>; + resets = <&peri_rst 9>; clock-frequency = <400000>; }; @@ -184,6 +207,7 @@ #size-cells = <0>; interrupts = <0 26 4>; clocks = <&peri_clk 10>; + resets = <&peri_rst 10>; clock-frequency = <400000>; }; @@ -324,6 +348,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clocks = <&sys_clk 2>; + resets = <&sys_rst 2>; }; }; }; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index b026bcd42a06..6589b8a2c65c 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -37,7 +37,7 @@ }; }; - cpu_opp: opp_table { + cpu_opp: opp-table { compatible = "operating-points-v2"; opp-shared; @@ -119,7 +119,7 @@ clock-frequency = <20000000>; }; - arm_timer_clk: arm_timer_clk { + arm_timer_clk: arm-timer { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; @@ -166,6 +166,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; }; serial1: serial@54006900 { @@ -176,6 +177,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; }; serial2: serial@54006a00 { @@ -186,6 +188,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; }; serial3: serial@54006b00 { @@ -196,6 +199,21 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <248>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>; }; i2c0: i2c@58780000 { @@ -208,6 +226,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; clock-frequency = <100000>; }; @@ -221,6 +240,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; clock-frequency = <100000>; }; @@ -234,6 +254,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; clock-frequency = <100000>; }; @@ -247,6 +268,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; clock-frequency = <100000>; }; @@ -260,6 +282,7 @@ #size-cells = <0>; interrupts = <0 25 4>; clocks = <&peri_clk 9>; + resets = <&peri_rst 9>; clock-frequency = <400000>; }; @@ -271,6 +294,7 @@ #size-cells = <0>; interrupts = <0 26 4>; clocks = <&peri_clk 10>; + resets = <&peri_rst 10>; clock-frequency = <400000>; }; @@ -385,6 +409,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; clocks = <&sys_clk 2>; + resets = <&sys_rst 2>; }; }; }; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 90b020c95083..d82d6d872131 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -7,6 +7,8 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#include <dt-bindings/thermal/thermal.h> + / { compatible = "socionext,uniphier-pxs2"; #address-cells = <1>; @@ -16,7 +18,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; @@ -24,9 +26,10 @@ enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu_opp>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; @@ -36,7 +39,7 @@ operating-points-v2 = <&cpu_opp>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; @@ -46,7 +49,7 @@ operating-points-v2 = <&cpu_opp>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; @@ -57,7 +60,7 @@ }; }; - cpu_opp: opp_table { + cpu_opp: opp-table { compatible = "operating-points-v2"; opp-shared; @@ -107,13 +110,42 @@ clock-frequency = <25000000>; }; - arm_timer_clk: arm_timer_clk { + arm_timer_clk: arm-timer { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + thermal-sensors = <&pvtctl>; + + trips { + cpu_crit: cpu-crit { + temperature = <95000>; /* 95C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu-alert { + temperature = <85000>; /* 85C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map { + trip = <&cpu_alert>; + cooling-device = <&cpu0 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -141,6 +173,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; }; serial1: serial@54006900 { @@ -151,6 +184,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; }; serial2: serial@54006a00 { @@ -161,6 +195,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; }; serial3: serial@54006b00 { @@ -171,6 +206,24 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 96 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1"; + ngpios = <232>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>, + <21 217 3>; }; i2c0: i2c@58780000 { @@ -183,6 +236,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; clock-frequency = <100000>; }; @@ -196,6 +250,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; clock-frequency = <100000>; }; @@ -209,6 +264,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; clock-frequency = <100000>; }; @@ -222,6 +278,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; clock-frequency = <100000>; }; @@ -233,6 +290,7 @@ #size-cells = <0>; interrupts = <0 45 4>; clocks = <&peri_clk 8>; + resets = <&peri_rst 8>; clock-frequency = <400000>; }; @@ -244,6 +302,7 @@ #size-cells = <0>; interrupts = <0 25 4>; clocks = <&peri_clk 9>; + resets = <&peri_rst 9>; clock-frequency = <400000>; }; @@ -255,6 +314,7 @@ #size-cells = <0>; interrupts = <0 26 4>; clocks = <&peri_clk 10>; + resets = <&peri_rst 10>; clock-frequency = <400000>; }; @@ -358,6 +418,13 @@ compatible = "socionext,uniphier-pxs2-reset"; #reset-cells = <1>; }; + + pvtctl: pvtctl { + compatible = "socionext,uniphier-pxs2-thermal"; + interrupts = <0 3 4>; + #thermal-sensor-cells = <0>; + socionext,tmod-calibration = <0x0f86 0x6844>; + }; }; nand: nand@68000000 { @@ -369,6 +436,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; clocks = <&sys_clk 2>; + resets = <&sys_rst 2>; }; }; }; diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts index 5accd3cc76e4..1c0e7077a560 100644 --- a/arch/arm/boot/dts/uniphier-sld8-ref.dts +++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts @@ -38,7 +38,7 @@ }; ðsc { - interrupts = <0 48 4>; + interrupts = <0 8>; }; &serial0 { @@ -53,6 +53,14 @@ status = "okay"; }; +&gpio { + xirq0 { + gpio-hog; + gpios = <120 0>; + input; + }; +}; + &i2c0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index ebd0c3f63e7f..71885366cd23 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -37,7 +37,7 @@ clock-frequency = <25000000>; }; - arm_timer_clk: arm_timer_clk { + arm_timer_clk: arm-timer { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; @@ -71,6 +71,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; }; serial1: serial@54006900 { @@ -81,6 +82,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; }; serial2: serial@54006a00 { @@ -91,6 +93,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; }; serial3: serial@54006b00 { @@ -101,6 +104,25 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 104 0 0>, + <&pinctrl 112 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1", + "gpio_range2"; + ngpios = <136>; + socionext,interrupt-ranges = <0 48 13>, <14 62 2>; }; i2c0: i2c@58400000 { @@ -113,6 +135,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; clock-frequency = <100000>; }; @@ -126,6 +149,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; clock-frequency = <100000>; }; @@ -139,6 +163,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; clock-frequency = <400000>; }; @@ -152,6 +177,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; clock-frequency = <100000>; }; @@ -305,6 +331,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; clocks = <&sys_clk 2>; + resets = <&sys_rst 2>; }; }; }; diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi index 6c825f192e65..e4e7e1bb9172 100644 --- a/arch/arm/boot/dts/uniphier-support-card.dtsi +++ b/arch/arm/boot/dts/uniphier-support-card.dtsi @@ -11,11 +11,12 @@ status = "okay"; ranges = <1 0x00000000 0x42000000 0x02000000>; - support_card: support_card@1,1f00000 { + support_card: support-card@1,1f00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 1 0x01f00000 0x00100000>; + interrupt-parent = <&gpio>; ethsc: ethernet@0 { compatible = "smsc,lan9118", "smsc,lan9115"; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index 482381c1c962..7b1125be99c4 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -128,7 +128,7 @@ }; }; - usb0: ohci@00a00000 { + usb0: ohci@a00000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi index 088c2c3685ab..81c3fe0465d9 100644 --- a/arch/arm/boot/dts/usb_a9g20_common.dtsi +++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi @@ -20,8 +20,8 @@ }; i2c-gpio-0 { - rv3029c2@56 { - compatible = "rv3029c2"; + rtc@56 { + compatible = "microcrystal,rv3029"; reg = <0x56>; }; }; diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index 53e3b8b250c6..6f787e67bd2e 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -198,7 +198,7 @@ pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; - codec: sgtl5000@0a { + codec: sgtl5000@a { #sound-dai-cells = <0>; compatible = "fsl,sgtl5000"; reg = <0x0a>; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts index db3b408ea55a..02a6227c717c 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts @@ -359,7 +359,7 @@ }; &i2c1 { - at24mac602@00 { + at24mac602@0 { compatible = "atmel,24c02"; reg = <0x50>; read-only; diff --git a/arch/arm/boot/dts/zx296702.dtsi b/arch/arm/boot/dts/zx296702.dtsi index 752d28e0f9b0..8a74efdb6360 100644 --- a/arch/arm/boot/dts/zx296702.dtsi +++ b/arch/arm/boot/dts/zx296702.dtsi @@ -38,7 +38,7 @@ reg = <0x00400000 0x1000>; }; - intc: interrupt-controller@00801000 { + intc: interrupt-controller@801000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <1>; @@ -48,7 +48,7 @@ <0x00800100 0x100>; }; - global_timer: timer@008000200 { + global_timer: timer@8000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x00800200 0x20>; interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 34e8277fce0d..70a5de76b7db 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -152,7 +152,7 @@ #size-cells = <0>; reg = <2>; eeprom@54 { - compatible = "at,24c08"; + compatible = "atmel,24c08"; reg = <0x54>; }; }; diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index 7ebc8c5ae39d..cdc326ec3335 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -108,7 +108,7 @@ #size-cells = <0>; reg = <2>; eeprom@54 { - compatible = "at,24c08"; + compatible = "atmel,24c08"; reg = <0x54>; }; }; diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index 5699ce39e64f..f06db6700ab2 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -54,6 +54,7 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("ti,da830-usb-phy", 0x01c1417c, "da8xx-usb-phy", NULL), OF_DEV_AUXDATA("ti,da850-ahci", 0x01e18000, "ahci_da850", NULL), OF_DEV_AUXDATA("ti,da850-vpif", 0x01e17000, "vpif", NULL), + OF_DEV_AUXDATA("ti,da850-dsp", 0x11800000, "davinci-rproc.0", NULL), {} }; diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 1d03ef54295a..084f70c2ba48 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -104,6 +104,7 @@ config ARCH_MESON select PINCTRL_MESON select COMMON_CLK_AMLOGIC select COMMON_CLK_GXBB + select MESON_IRQ_GPIO help This enables support for the Amlogic S905 SoCs. @@ -187,6 +188,12 @@ config ARCH_R8A7796 help This enables support for the Renesas R-Car M3-W SoC. +config ARCH_R8A77970 + bool "Renesas R-Car V3M SoC Platform" + depends on ARCH_RENESAS + help + This enables support for the Renesas R-Car V3M SoC. + config ARCH_R8A77995 bool "Renesas R-Car D3 SoC Platform" depends on ARCH_RENESAS diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts index a0c3484dbd12..21ca80f9941c 100644 --- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts @@ -24,6 +24,12 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + uart5_clk: uart5-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; }; &timer { @@ -32,4 +38,5 @@ &uart5 { status = "okay"; + clocks = <&uart5_clk>; }; diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 7d3acb355ff3..f505227b0250 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -9,3 +9,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index d347f52e27f6..45bdbfb96126 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -51,6 +51,7 @@ compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -69,6 +70,14 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -79,6 +88,13 @@ bias-pull-up; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts index f82ccf332c0f..24f1aac366d6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts @@ -48,3 +48,18 @@ /* TODO: Camera, touchscreen, etc. */ }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index d06e34b5d192..806442d3e846 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -51,6 +51,7 @@ compatible = "pine64,pine64", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -71,6 +72,15 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + phy-mode = "rmii"; + phy-handle = <&ext_rmii_phy1>; + status = "okay"; + +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -81,6 +91,13 @@ bias-pull-up; }; +&mdio { + ext_rmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 17ccc12b58df..0eb2acedf8c3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -53,6 +53,7 @@ "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -76,6 +77,21 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 8c8db1b057df..d783d164b9c3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -136,6 +136,17 @@ reg = <0x01c00000 0x1000>; }; + dma: dma-controller@1c02000 { + compatible = "allwinner,sun50i-a64-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DMA>; + dma-channels = <8>; + dma-requests = <27>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun50i-a64-mmc"; reg = <0x01c0f000 0x1000>; @@ -178,7 +189,7 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-a33-musb"; reg = <0x01c19000 0x0400>; clocks = <&ccu CLK_BUS_OTG>; @@ -191,7 +202,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { compatible = "allwinner,sun50i-a64-usb-phy"; reg = <0x01c19400 0x14>, <0x01c1a800 0x4>, @@ -211,7 +222,7 @@ #phy-cells = <1>; }; - ehci0: usb@01c1a000 { + ehci0: usb@1c1a000 { compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; @@ -223,7 +234,7 @@ status = "disabled"; }; - ohci0: usb@01c1a400 { + ohci0: usb@1c1a400 { compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; @@ -233,7 +244,7 @@ status = "disabled"; }; - ehci1: usb@01c1b000 { + ehci1: usb@1c1b000 { compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; @@ -247,7 +258,7 @@ status = "disabled"; }; - ohci1: usb@01c1b400 { + ohci1: usb@1c1b400 { compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; reg = <0x01c1b400 0x100>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; @@ -259,7 +270,7 @@ status = "disabled"; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { compatible = "allwinner,sun50i-a64-ccu"; reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; @@ -325,7 +336,17 @@ drive-strength = <40>; }; - uart0_pins_a: uart0@0 { + spi0_pins: spi0 { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; + + spi1_pins: spi1 { + pins = "PD0", "PD1", "PD2", "PD3"; + function = "spi1"; + }; + + uart0_pins_a: uart0 { pins = "PB8", "PB9"; function = "uart0"; }; @@ -449,6 +470,62 @@ #size-cells = <0>; }; + + spi0: spi@1c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c69000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c69000 0x1000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 24>, <&dma 24>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + emac: ethernet@1c30000 { + compatible = "allwinner,sun50i-a64-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, @@ -486,7 +563,7 @@ #reset-cells = <1>; }; - r_pio: pinctrl@01f02c00 { + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -497,7 +574,7 @@ interrupt-controller; #interrupt-cells = <3>; - r_rsb_pins: rsb@0 { + r_rsb_pins: rsb { pins = "PL0", "PL1"; function = "s_rsb"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts new file mode 100644 index 000000000000..7c028af58f47 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2017 Antony Antony <antony@phenome.org> + * Copyright (C) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun50i-h5.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "FriendlyARM NanoPi NEO Plus2"; + compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr { + label = "nanopi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status { + label = "nanopi:red:status"; + gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_cpux: gpio-regulator { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <1100000 0x0 + 1300000 0x1>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + post-power-on-delay-ms = <200>; + }; +}; + +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + /* USB Type-A ports' VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts index 1c2387bd5df6..6eb8092d8e57 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts @@ -50,6 +50,7 @@ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -108,6 +109,22 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index 4f77c8470f6c..a0ca925175aa 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -59,6 +59,7 @@ }; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -136,6 +137,22 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts index 6be06873e5af..b47790650144 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts @@ -54,6 +54,7 @@ compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -143,6 +144,22 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index c2b9bcb0ef61..7c9bdc7ab50b 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -15,6 +15,8 @@ */ /dts-v1/; +#include <dt-bindings/reset/altr,rst-mgr-s10.h> +#include <dt-bindings/gpio/gpio.h> / { compatible = "altr,socfpga-stratix10"; @@ -75,10 +77,10 @@ compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x0 0xfffc1000 0x1000>, - <0x0 0xfffc2000 0x2000>, - <0x0 0xfffc4000 0x2000>, - <0x0 0xfffc6000 0x2000>; + reg = <0x0 0xfffc1000 0x0 0x1000>, + <0x0 0xfffc2000 0x0 0x2000>, + <0x0 0xfffc4000 0x0 0x2000>, + <0x0 0xfffc6000 0x0 0x2000>; }; soc { @@ -100,6 +102,8 @@ interrupts = <0 90 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; status = "disabled"; }; @@ -109,6 +113,8 @@ interrupts = <0 91 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; status = "disabled"; }; @@ -118,6 +124,8 @@ interrupts = <0 92 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC2_RESET>; + reset-names = "stmmaceth"; status = "disabled"; }; @@ -126,6 +134,7 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xffc03200 0x100>; + resets = <&rst GPIO0_RESET>; status = "disabled"; porta: gpio-controller@0 { @@ -145,6 +154,7 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xffc03300 0x100>; + resets = <&rst GPIO1_RESET>; status = "disabled"; portb: gpio-controller@0 { @@ -155,7 +165,7 @@ reg = <0>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 110 4>; + interrupts = <0 111 4>; }; }; @@ -165,6 +175,7 @@ compatible = "snps,designware-i2c"; reg = <0xffc02800 0x100>; interrupts = <0 103 4>; + resets = <&rst I2C0_RESET>; status = "disabled"; }; @@ -174,6 +185,7 @@ compatible = "snps,designware-i2c"; reg = <0xffc02900 0x100>; interrupts = <0 104 4>; + resets = <&rst I2C1_RESET>; status = "disabled"; }; @@ -183,6 +195,7 @@ compatible = "snps,designware-i2c"; reg = <0xffc02a00 0x100>; interrupts = <0 105 4>; + resets = <&rst I2C2_RESET>; status = "disabled"; }; @@ -192,6 +205,7 @@ compatible = "snps,designware-i2c"; reg = <0xffc02b00 0x100>; interrupts = <0 106 4>; + resets = <&rst I2C3_RESET>; status = "disabled"; }; @@ -201,6 +215,7 @@ compatible = "snps,designware-i2c"; reg = <0xffc02c00 0x100>; interrupts = <0 107 4>; + resets = <&rst I2C4_RESET>; status = "disabled"; }; @@ -211,6 +226,8 @@ reg = <0xff808000 0x1000>; interrupts = <0 96 4>; fifo-depth = <0x400>; + resets = <&rst SDMMC_RESET>; + reset-names = "reset"; status = "disabled"; }; @@ -223,6 +240,7 @@ #reset-cells = <1>; compatible = "altr,rst-mgr"; reg = <0xffd11000 0x1000>; + altr,modrst-offset = <0x20>; }; spi0: spi@ffda4000 { @@ -291,6 +309,7 @@ interrupts = <0 108 4>; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst UART0_RESET>; status = "disabled"; }; @@ -300,6 +319,7 @@ interrupts = <0 109 4>; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst UART1_RESET>; status = "disabled"; }; @@ -315,6 +335,8 @@ interrupts = <0 93 4>; phys = <&usbphy0>; phy-names = "usb2-phy"; + resets = <&rst USB0_RESET>; + reset-names = "dwc2"; status = "disabled"; }; @@ -324,6 +346,8 @@ interrupts = <0 94 4>; phys = <&usbphy0>; phy-names = "usb2-phy"; + resets = <&rst USB1_RESET>; + reset-names = "dwc2"; status = "disabled"; }; @@ -331,6 +355,7 @@ compatible = "snps,dw-wdt"; reg = <0xffd00200 0x100>; interrupts = <0 117 4>; + resets = <&rst WATCHDOG0_RESET>; status = "disabled"; }; @@ -338,6 +363,7 @@ compatible = "snps,dw-wdt"; reg = <0xffd00300 0x100>; interrupts = <0 118 4>; + resets = <&rst WATCHDOG1_RESET>; status = "disabled"; }; @@ -345,6 +371,7 @@ compatible = "snps,dw-wdt"; reg = <0xffd00400 0x100>; interrupts = <0 125 4>; + resets = <&rst WATCHDOG2_RESET>; status = "disabled"; }; @@ -352,6 +379,7 @@ compatible = "snps,dw-wdt"; reg = <0xffd00500 0x100>; interrupts = <0 126 4>; + resets = <&rst WATCHDOG3_RESET>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 41ea2dba2fce..a37c46112876 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -14,7 +14,7 @@ * this program. If not, see <http://www.gnu.org/licenses/>. */ -/include/ "socfpga_stratix10.dtsi" +#include "socfpga_stratix10.dtsi" / { model = "SoCFPGA Stratix 10 SoCDK"; @@ -27,6 +27,24 @@ stdout-path = "serial0:115200n8"; }; + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + memory { device_type = "memory"; /* We expect the bootloader to fill in the reg */ @@ -34,6 +52,48 @@ }; }; +&gpio1 { + status = "okay"; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <3800>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&mmc { + status = "okay"; + num-slots = <1>; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index f84b83bb9809..34dd0e9b5cbb 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb @@ -16,7 +17,9 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts new file mode 100644 index 000000000000..70eca1f8736a --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "meson-axg.dtsi" + +/ { + compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg"; + model = "Amlogic Meson AXG S400 Development Board"; + + aliases { + serial0 = &uart_AO; + }; +}; + +&uart_AO { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi new file mode 100644 index 000000000000..b932a784b02a --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "amlogic,meson-axg"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 16 MiB reserved for Hardware ROM Firmware */ + hwrom_reserved: hwrom@0 { + reg = <0x0 0x0 0x0 0x1000000>; + no-map; + }; + + /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cbus: cbus@ffd00000 { + compatible = "simple-bus"; + reg = <0x0 0xffd00000 0x0 0x25000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; + + uart_A: serial@24000 { + compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; + reg = <0x0 0x24000 0x0 0x14>; + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + uart_B: serial@23000 { + compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; + reg = <0x0 0x23000 0x0 0x14>; + interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, + <0x0 0xffc02000 0 0x2000>, + <0x0 0xffc04000 0 0x2000>, + <0x0 0xffc06000 0 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + mailbox: mailbox@ff63dc00 { + compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; + reg = <0 0xff63dc00 0 0x400>; + interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; + #mbox-cells = <1>; + }; + + sram: sram@fffc0000 { + compatible = "amlogic,meson-axg-sram", "mmio-sram"; + reg = <0x0 0xfffc0000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xfffc0000 0x20000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "amlogic,meson-axg-scp-shmem"; + reg = <0x13000 0x400>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "amlogic,meson-axg-scp-shmem"; + reg = <0x13400 0x400>; + }; + }; + + aobus: aobus@ff800000 { + compatible = "simple-bus"; + reg = <0x0 0xff800000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; + + uart_AO: serial@3000 { + compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; + reg = <0x0 0x3000 0x0 0x18>; + interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_AO_B: serial@4000 { + compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; + reg = <0x0 0x4000 0x0 0x18>; + interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi index 4157987f4a3d..7d4b95e49993 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi @@ -213,7 +213,7 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; pinctrl-1 = <&emmc_clk_gate_pins>; pinctrl-names = "default", "clk-gate"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index f175db846286..ab7ce1644cdc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -218,6 +218,15 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; + gpio_intc: interrupt-controller@9880 { + compatible = "amlogic,meson-gpio-intc"; + reg = <0x0 0x9880 0x0 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + status = "disabled"; + }; + reset: reset-controller@4404 { compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; reg = <0x0 0x04404 0x0 0x20>; @@ -225,18 +234,16 @@ }; uart_A: serial@84c0 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson-gx-uart"; reg = <0x0 0x84c0 0x0 0x14>; interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>; status = "disabled"; }; uart_B: serial@84dc { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson-gx-uart"; reg = <0x0 0x84dc 0x0 0x14>; interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>; status = "disabled"; }; @@ -279,10 +286,9 @@ }; uart_C: serial@8700 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson-gx-uart"; reg = <0x0 0x8700 0x0 0x14>; interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>; status = "disabled"; }; @@ -391,14 +397,14 @@ }; uart_AO: serial@4c0 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x004c0 0x0 0x14>; interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; uart_AO_B: serial@4e0 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x004e0 0x0 0x14>; interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; status = "disabled"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index 4b17a76959b2..4a4251001bfd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -168,6 +168,8 @@ eth_phy0: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ reg = <0>; + interrupt-parent = <&gpio_intc>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -183,7 +185,9 @@ "VCCK En", "CON1 Header Pin31", "I2S Header Pin6", "IR In", "I2S Header Pin7", "I2S Header Pin3", "I2S Header Pin4", - "I2S Header Pin5", "HDMI CEC", "SYS LED"; + "I2S Header Pin5", "HDMI CEC", "SYS LED", + /* GPIO_TEST_N */ + ""; }; &pinctrl_periphs { @@ -229,11 +233,9 @@ "Bluetooth UART TX", "Bluetooth UART RX", "Bluetooth UART CTS", "Bluetooth UART RTS", "", "", "", "WIFI 32K", "Bluetooth Enable", - "Bluetooth WAKE HOST", + "Bluetooth WAKE HOST", "", /* Bank GPIOCLK */ - "", "CON1 Header Pin35", "", "", - /* GPIO_TEST_N */ - ""; + "", "CON1 Header Pin35", "", ""; }; &pwm_ef { @@ -302,7 +304,7 @@ /* eMMC */ &sd_emmc_c { status = "disabled"; - pinctrl-0 = <&emmc_pins>; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; pinctrl-1 = <&emmc_clk_gate_pins>; pinctrl-names = "default", "clk-gate"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts index 38dfdde5c147..818954b1d57f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts @@ -88,6 +88,18 @@ }; }; + usb_pwr: regulator-usb-pwrs { + compatible = "regulator-fixed"; + + regulator-name = "USB_PWR"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + vddio_card: gpio-regulator { compatible = "regulator-gpio"; @@ -272,7 +284,7 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; pinctrl-1 = <&emmc_clk_gate_pins>; pinctrl-names = "default", "clk-gate"; @@ -294,3 +306,20 @@ pinctrl-0 = <&uart_ao_a_pins>; pinctrl-names = "default"; }; + +&usb0_phy { + status = "okay"; + phy-supply = <&usb_pwr>; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 1ffa1c238a72..f8d221463c60 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -157,6 +157,8 @@ eth_phy0: ethernet-phy@0 { reg = <0>; + interrupt-parent = <&gpio_intc>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; eee-broken-1000t; }; }; @@ -194,7 +196,9 @@ "USB HUB nRESET", "USB OTG Power En", "J7 Header Pin2", "IR In", "J7 Header Pin4", "J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7", - "HDMI CEC", "SYS LED"; + "HDMI CEC", "SYS LED", + /* GPIO_TEST_N */ + ""; }; &pinctrl_periphs { @@ -233,11 +237,9 @@ "J2 Header Pin12", "J2 Header Pin13", "J2 Header Pin8", "J2 Header Pin10", "", "", "", "", "", - "J2 Header Pin11", "", "J2 Header Pin7", + "J2 Header Pin11", "", "J2 Header Pin7", "", /* Bank GPIOCLK */ - "", "", "", "", - /* GPIO_TEST_N */ - ""; + "", "", "", ""; }; &saradc { @@ -271,7 +273,7 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; pinctrl-1 = <&emmc_clk_gate_pins>; pinctrl-names = "default", "clk-gate"; @@ -301,6 +303,7 @@ &usb1_phy { status = "okay"; + phy-supply = <&usb_otg_pwr>; }; &usb0 { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts index 2054a474e0a9..9bf16bb7c491 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts @@ -117,6 +117,8 @@ eth_phy0: ethernet-phy@3 { /* Micrel KSZ9031 (0x00221620) */ reg = <3>; + interrupt-parent = <&gpio_intc>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index 23c08c3afd0a..932158a778ef 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -242,7 +242,7 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; pinctrl-1 = <&emmc_clk_gate_pins>; pinctrl-names = "default", "clk-gate"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index f2bc6dea1fc6..1fe8e24cf675 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -199,7 +199,7 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; pinctrl-1 = <&emmc_clk_gate_pins>; pinctrl-names = "default", "clk-gate"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index af834cdbba79..ead895a4e9a5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -323,6 +323,12 @@ clock-names = "stmmaceth", "clkin0", "clkin1"; }; +&gpio_intc { + compatible = "amlogic,meson-gpio-intc", + "amlogic,meson-gxbb-gpio-intc"; + status = "okay"; +}; + &hdmi_tx { compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; resets = <&reset RESET_HDMITX_CAPB3>, @@ -379,15 +385,21 @@ reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 14 120>; + gpio-ranges = <&pinctrl_periphs 0 0 119>; }; emmc_pins: emmc { mux { groups = "emmc_nand_d07", "emmc_cmd", - "emmc_clk", - "emmc_ds"; + "emmc_clk"; + function = "emmc"; + }; + }; + + emmc_ds_pins: emmc-ds { + mux { + groups = "emmc_ds"; function = "emmc"; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts index 6827f235d7cf..4f3f03fc31b0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts @@ -128,6 +128,8 @@ compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22"; reg = <0>; max-speed = <1000>; + interrupt-parent = <&gpio_intc>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts index 977b4240f3c1..e82582574160 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts @@ -141,7 +141,7 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; pinctrl-1 = <&emmc_clk_gate_pins>; pinctrl-names = "default", "clk-gate"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index edc512ad0bac..71a6e1ce7ad5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -122,7 +122,9 @@ "J9 Header Pin33", "IR In", "HDMI CEC", - "SYS LED"; + "SYS LED", + /* GPIO_TEST_N */ + ""; }; &pinctrl_periphs { @@ -163,9 +165,7 @@ "WIFI 32K", "Bluetooth Enable", "Bluetooth WAKE HOST", /* Bank GPIOCLK */ - "", "J9 Header Pin39", - /* GPIO_TEST_N */ - ""; + "", "J9 Header Pin39"; }; &pwm_AO_ab { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts index 64c54c92e214..dc9c3b8216c2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -96,6 +96,13 @@ regulator-settling-time-down-us = <50000>; }; + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vddio_boot: regulator-vddio_boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; @@ -121,6 +128,11 @@ status = "okay"; }; +&internal_phy { + pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; + pinctrl-names = "default"; +}; + &ir { status = "okay"; pinctrl-0 = <&remote_input_ao_pins>; @@ -149,7 +161,9 @@ "7J1 Header Pin12", "IR In", "9J3 Switch HDMI CEC/7J1 Header Pin11", - "7J1 Header Pin13"; + "7J1 Header Pin13", + /* GPIO_TEST_N */ + "7J1 Header Pin15"; }; &pinctrl_periphs { @@ -191,9 +205,12 @@ "7J1 Header Pin32", "7J1 Header Pin29", "7J1 Header Pin31", /* Bank GPIOCLK */ - "7J1 Header Pin7", "", - /* GPIO_TEST_N */ - "7J1 Header Pin15"; + "7J1 Header Pin7", ""; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; }; /* SD card */ @@ -221,7 +238,7 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; pinctrl-1 = <&emmc_clk_gate_pins>; pinctrl-names = "default", "clk-gate"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts index 1b8f32867aa1..271f14279180 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts @@ -229,7 +229,7 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; pinctrl-1 = <&emmc_clk_gate_pins>; pinctrl-names = "default", "clk-gate"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi index 129af9068814..ff09df1fd5a3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi @@ -135,7 +135,7 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; pinctrl-1 = <&emmc_clk_gate_pins>; pinctrl-names = "default", "clk-gate"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index d8dd3298b15c..8ed981f59e5a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -49,6 +49,14 @@ / { compatible = "amlogic,meson-gxl"; + + reserved-memory { + /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved_alt: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + }; }; ðmac { @@ -217,6 +225,12 @@ compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; }; +&gpio_intc { + compatible = "amlogic,meson-gpio-intc", + "amlogic,meson-gxl-gpio-intc"; + status = "okay"; +}; + &hdmi_tx { compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; resets = <&reset RESET_HDMITX_CAPB3>, @@ -268,15 +282,21 @@ reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 10 101>; + gpio-ranges = <&pinctrl_periphs 0 0 100>; }; emmc_pins: emmc { mux { groups = "emmc_nand_d07", "emmc_cmd", - "emmc_clk", - "emmc_ds"; + "emmc_clk"; + function = "emmc"; + }; + }; + + emmc_ds_pins: emmc-ds { + mux { + groups = "emmc_ds"; function = "emmc"; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts new file mode 100644 index 000000000000..34a41b26a4ed --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -0,0 +1,400 @@ +/* + * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Copyright (c) 2017 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/thermal/thermal.h> + +#include "meson-gxm.dtsi" + +/ { + compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm"; + model = "Khadas VIM2"; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_AO_B; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1710000>; + + button-function { + label = "Function"; + linux,code = <KEY_FN>; + press-threshold-microvolt = <10000>; + }; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + gpio_fan: gpio-fan { + compatible = "gpio-fan"; + gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH + &gpio GPIODV_15 GPIO_ACTIVE_HIGH>; + /* Dummy RPM values since fan is optional */ + gpio-fan,speed-map = <0 0 + 1 1 + 2 2 + 3 3>; + cooling-min-level = <0>; + cooling-max-level = <3>; + #cooling-cells = <2>; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + button@0 { + label = "power"; + linux,code = <KEY_POWER>; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + power { + label = "vim:red:power"; + pwms = <&pwm_AO_ab 1 7812500 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&scpi_sensors 0>; + + trips { + cpu_alert0: cpu-alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + + cpu_alert1: cpu-alert1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>; + }; + + map1 { + trip = <&cpu_alert1>; + cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>; + }; + + map2 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map3 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; +}; + +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cpu0 { + cooling-min-level = <0>; + cooling-max-level = <6>; + #cooling-cells = <2>; +}; + +&cpu4 { + cooling-min-level = <0>; + cooling-max-level = <4>; + #cooling-cells = <2>; +}; + +ðmac { + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; + + /* Select external PHY by default */ + phy-handle = <&external_phy>; + + amlogic,tx-delay-ns = <2>; + + /* External PHY reset is shared with internal PHY Led signals */ + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + /* External PHY is in RGMII */ + phy-mode = "rgmii"; + + status = "okay"; +}; + +&external_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + }; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&i2c_A { + status = "okay"; + pinctrl-0 = <&i2c_a_pins>; + pinctrl-names = "default"; +}; + +&i2c_B { + status = "okay"; + pinctrl-0 = <&i2c_b_pins>; + pinctrl-names = "default"; + + rtc: rtc@51 { + /* has to be enabled manually when a battery is connected: */ + status = "disabled"; + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; + linux,rc-map-name = "rc-geekbox"; +}; + +&pwm_AO_ab { + status = "okay"; + pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; + +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* + * EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe + * Remove emmc_ds_pins from sd_emmc_c pinctrl-0 then spifc can be enabled + */ +&spifc { + status = "disabled"; + pinctrl-0 = <&nor_pins>; + pinctrl-names = "default"; + + w25q32: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q16", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <3000000>; + }; +}; + +/* This one is connected to the Bluetooth module */ +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>; + pinctrl-names = "default"; +}; + +/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ +&uart_AO_B { + status = "okay"; + pinctrl-0 = <&uart_ao_b_pins>; + pinctrl-names = "default"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts index 22c697732f66..e7a228f6cc7e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts @@ -193,7 +193,7 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; pinctrl-1 = <&emmc_clk_gate_pins>; pinctrl-names = "default", "clk-gate"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts index b65776b01911..66c6da7e112c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts @@ -110,6 +110,8 @@ compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22"; reg = <0>; max-speed = <1000>; + interrupt-parent = <&gpio_intc>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts index 470f72bb863c..a5e9b955d5ed 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts @@ -216,7 +216,7 @@ /* eMMC */ &sd_emmc_c { status = "okay"; - pinctrl-0 = <&emmc_pins>; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; pinctrl-names = "default"; bus-width = <8>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts new file mode 100644 index 000000000000..dc37eecb9514 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * Copyright (c) 2017 Oleg <balbes-150@yandex.ru> + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "meson-gxm.dtsi" +#include "meson-gx-p23x-q20x.dtsi" + +/ { + compatible = "tronsmart,vega-s96", "amlogic,s912", "amlogic,meson-gxm"; + model = "Tronsmart Vega S96"; + +}; + +ðmac { + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; + + /* Select external PHY by default */ + phy-handle = <&external_phy>; + + amlogic,tx-delay-ns = <2>; + + /* External PHY is in RGMII */ + phy-mode = "rgmii"; +}; + +&external_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index c9ffffb96e43..d8ecd1661461 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -19,7 +19,7 @@ #address-cells = <2>; #size-cells = <0>; - cpu@000 { + cpu@0 { device_type = "cpu"; compatible = "apm,strega", "arm,armv8"; reg = <0x0 0x000>; @@ -29,7 +29,7 @@ #clock-cells = <1>; clocks = <&pmd0clk 0>; }; - cpu@001 { + cpu@1 { device_type = "cpu"; compatible = "apm,strega", "arm,armv8"; reg = <0x0 0x001>; @@ -125,7 +125,7 @@ <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */ <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */ <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */ - v2m0: v2m@00000 { + v2m0: v2m@0 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x0 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index c09a36fed917..00e82b8e9a19 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -19,7 +19,7 @@ #address-cells = <2>; #size-cells = <0>; - cpu@000 { + cpu@0 { device_type = "cpu"; compatible = "apm,potenza", "arm,armv8"; reg = <0x0 0x000>; @@ -27,7 +27,7 @@ cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_0>; }; - cpu@001 { + cpu@1 { device_type = "cpu"; compatible = "apm,potenza", "arm,armv8"; reg = <0x0 0x001>; diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 4256bae99925..5b45144b371a 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb foundation-v8-gicv3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += \ + foundation-v8.dtb foundation-v8-psci.dtb \ + foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi new file mode 100644 index 000000000000..851abf34fc80 --- /dev/null +++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi @@ -0,0 +1,19 @@ +/* + * ARM Ltd. + * + * ARMv8 Foundation model DTS (GICv2 configuration) + */ + +/ { + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <2>; + interrupt-controller; + reg = <0x0 0x2c001000 0 0x1000>, + <0x0 0x2c002000 0 0x2000>, + <0x0 0x2c004000 0 0x2000>, + <0x0 0x2c006000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; +}; diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3-psci.dts b/arch/arm64/boot/dts/arm/foundation-v8-gicv3-psci.dts new file mode 100644 index 000000000000..e096e670bec3 --- /dev/null +++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv3-psci.dts @@ -0,0 +1,9 @@ +/* + * ARM Ltd. + * + * ARMv8 Foundation model DTS (GICv3+PSCI configuration) + */ + +#include "foundation-v8.dtsi" +#include "foundation-v8-gicv3.dtsi" +#include "foundation-v8-psci.dtsi" diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts index 4825cdbdcf46..c87380e87f59 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts +++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts @@ -6,26 +6,5 @@ */ #include "foundation-v8.dtsi" - -/ { - gic: interrupt-controller@2f000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - reg = <0x0 0x2f000000 0x0 0x10000>, - <0x0 0x2f100000 0x0 0x200000>, - <0x0 0x2c000000 0x0 0x2000>, - <0x0 0x2c010000 0x0 0x2000>, - <0x0 0x2c02f000 0x0 0x2000>; - interrupts = <1 9 4>; - - its: its@2f020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x2f020000 0x0 0x20000>; - }; - }; -}; +#include "foundation-v8-gicv3.dtsi" +#include "foundation-v8-spin-table.dtsi" diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi new file mode 100644 index 000000000000..91fc5c60d88b --- /dev/null +++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi @@ -0,0 +1,28 @@ +/* + * ARM Ltd. + * + * ARMv8 Foundation model DTS (GICv3 configuration) + */ + +/ { + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2f000000 0x0 0x10000>, + <0x0 0x2f100000 0x0 0x200000>, + <0x0 0x2c000000 0x0 0x2000>, + <0x0 0x2c010000 0x0 0x2000>, + <0x0 0x2c02f000 0x0 0x2000>; + interrupts = <1 9 4>; + + its: its@2f020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x2f020000 0x0 0x20000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/arm/foundation-v8-psci.dts b/arch/arm64/boot/dts/arm/foundation-v8-psci.dts new file mode 100644 index 000000000000..723f23c7cd31 --- /dev/null +++ b/arch/arm64/boot/dts/arm/foundation-v8-psci.dts @@ -0,0 +1,9 @@ +/* + * ARM Ltd. + * + * ARMv8 Foundation model DTS (GICv2+PSCI configuration) + */ + +#include "foundation-v8.dtsi" +#include "foundation-v8-gicv2.dtsi" +#include "foundation-v8-psci.dtsi" diff --git a/arch/arm64/boot/dts/arm/foundation-v8-psci.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-psci.dtsi new file mode 100644 index 000000000000..16cdf395728b --- /dev/null +++ b/arch/arm64/boot/dts/arm/foundation-v8-psci.dtsi @@ -0,0 +1,28 @@ +/* + * ARM Ltd. + * + * ARMv8 Foundation model DTS (PSCI configuration) + */ + +/ { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; +}; + +&cpu0 { + enable-method = "psci"; +}; + +&cpu1 { + enable-method = "psci"; +}; + +&cpu2 { + enable-method = "psci"; +}; + +&cpu3 { + enable-method = "psci"; +}; diff --git a/arch/arm64/boot/dts/arm/foundation-v8-spin-table.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-spin-table.dtsi new file mode 100644 index 000000000000..4d4186ba0e8c --- /dev/null +++ b/arch/arm64/boot/dts/arm/foundation-v8-spin-table.dtsi @@ -0,0 +1,25 @@ +/* + * ARM Ltd. + * + * ARMv8 Foundation model DTS (spin table configuration) + */ + +&cpu0 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; +}; + +&cpu1 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; +}; + +&cpu2 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; +}; + +&cpu3 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; +}; diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dts b/arch/arm64/boot/dts/arm/foundation-v8.dts index 8a9136f4ab74..b17347d75ec6 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dts +++ b/arch/arm64/boot/dts/arm/foundation-v8.dts @@ -6,17 +6,5 @@ */ #include "foundation-v8.dtsi" - -/ { - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <2>; - interrupt-controller; - reg = <0x0 0x2c001000 0 0x1000>, - <0x0 0x2c002000 0 0x2000>, - <0x0 0x2c004000 0 0x2000>, - <0x0 0x2c006000 0 0x2000>; - interrupts = <1 9 0xf04>; - }; -}; +#include "foundation-v8-gicv2.dtsi" +#include "foundation-v8-spin-table.dtsi" diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index f0b67e439f58..e080277d27ae 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -29,36 +29,28 @@ #address-cells = <2>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; next-level-cache = <&L2_0>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; next-level-cache = <&L2_0>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; next-level-cache = <&L2_0>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; next-level-cache = <&L2_0>; }; @@ -98,7 +90,7 @@ timeout-sec = <30>; }; - smb@08000000 { + smb@8000000 { compatible = "arm,vexpress,v2m-p1", "simple-bus"; arm,v2m-memory-map = "rs1"; #address-cells = <2>; /* SMB chipselect number and offset */ @@ -190,12 +182,12 @@ #size-cells = <1>; ranges = <0 3 0 0x200000>; - v2m_sysreg: sysreg@010000 { + v2m_sysreg: sysreg@10000 { compatible = "arm,vexpress-sysreg"; reg = <0x010000 0x1000>; }; - v2m_serial0: uart@090000 { + v2m_serial0: uart@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -203,7 +195,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@0a0000 { + v2m_serial1: uart@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -211,7 +203,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@0b0000 { + v2m_serial2: uart@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -219,7 +211,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@0c0000 { + v2m_serial3: uart@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; @@ -227,7 +219,7 @@ clock-names = "uartclk", "apb_pclk"; }; - virtio-block@0130000 { + virtio-block@130000 { compatible = "virtio,mmio"; reg = <0x130000 0x200>; interrupts = <42>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts index 7810632d3438..06c8117e812a 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts +++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts @@ -105,7 +105,7 @@ <0 63 4>; }; - smb@08000000 { + smb@8000000 { compatible = "simple-bus"; #address-cells = <2>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index e18fe006cc2a..1134e5d8df18 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -61,14 +61,14 @@ #size-cells = <1>; ranges = <0 3 0 0x200000>; - v2m_sysreg: sysreg@010000 { + v2m_sysreg: sysreg@10000 { compatible = "arm,vexpress-sysreg"; reg = <0x010000 0x1000>; gpio-controller; #gpio-cells = <2>; }; - v2m_sysctl: sysctl@020000 { + v2m_sysctl: sysctl@20000 { compatible = "arm,sp810", "arm,primecell"; reg = <0x020000 0x1000>; clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; @@ -79,7 +79,7 @@ assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; }; - aaci@040000 { + aaci@40000 { compatible = "arm,pl041", "arm,primecell"; reg = <0x040000 0x1000>; interrupts = <11>; @@ -87,7 +87,7 @@ clock-names = "apb_pclk"; }; - mmci@050000 { + mmci@50000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x050000 0x1000>; interrupts = <9 10>; @@ -99,7 +99,7 @@ clock-names = "mclk", "apb_pclk"; }; - kmi@060000 { + kmi@60000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x060000 0x1000>; interrupts = <12>; @@ -107,7 +107,7 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - kmi@070000 { + kmi@70000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x070000 0x1000>; interrupts = <13>; @@ -115,7 +115,7 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - v2m_serial0: uart@090000 { + v2m_serial0: uart@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -123,7 +123,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@0a0000 { + v2m_serial1: uart@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -131,7 +131,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@0b0000 { + v2m_serial2: uart@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -139,7 +139,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@0c0000 { + v2m_serial3: uart@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; @@ -147,7 +147,7 @@ clock-names = "uartclk", "apb_pclk"; }; - wdt@0f0000 { + wdt@f0000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0f0000 0x1000>; interrupts = <0>; @@ -220,7 +220,7 @@ }; }; - virtio-block@0130000 { + virtio-block@130000 { compatible = "virtio,mmio"; reg = <0x130000 0x200>; interrupts = <42>; diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts index 2cb604957808..1c9eadc2d71e 100644 --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts @@ -129,7 +129,7 @@ }; }; - smb@08000000 { + smb@8000000 { compatible = "simple-bus"; #address-cells = <2>; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts index ab4ae1a32fab..f00c21e0767e 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts @@ -114,7 +114,7 @@ reg = <0x04000000 0x06400000>; /* 100MB */ }; - partition@0a400000{ + partition@a400000{ label = "ncustfs"; reg = <0x0a400000 0x35c00000>; /* 860MB */ }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 35c8457e3d1f..4a2a6af8e752 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -77,7 +77,7 @@ next-level-cache = <&CLUSTER0_L2>; }; - CLUSTER0_L2: l2-cache@000 { + CLUSTER0_L2: l2-cache@0 { compatible = "cache"; }; }; @@ -367,7 +367,7 @@ #size-cells = <1>; ranges = <0 0x652e0000 0x80000>; - v2m0: v2m@00000 { + v2m0: v2m@0 { compatible = "arm,gic-v2m-frame"; interrupt-parent = <&gic>; msi-controller; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi index cbc43376e25e..3a4d4524b5ed 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi @@ -46,7 +46,7 @@ clock-mult = <1>; }; - genpll0: genpll0@0001d104 { + genpll0: genpll0@1d104 { #clock-cells = <1>; compatible = "brcm,sr-genpll0"; reg = <0x0001d104 0x32>, @@ -58,7 +58,7 @@ "clk_paxc_axi"; }; - genpll3: genpll3@0001d1e0 { + genpll3: genpll3@1d1e0 { #clock-cells = <1>; compatible = "brcm,sr-genpll3"; reg = <0x0001d1e0 0x32>, @@ -68,7 +68,7 @@ "clk_sdio"; }; - genpll4: genpll4@0001d214 { + genpll4: genpll4@1d214 { #clock-cells = <1>; compatible = "brcm,sr-genpll4"; reg = <0x0001d214 0x32>, @@ -80,7 +80,7 @@ "clk_bridge_fscpu"; }; - genpll5: genpll5@0001d248 { + genpll5: genpll5@1d248 { #clock-cells = <1>; compatible = "brcm,sr-genpll5"; reg = <0x0001d248 0x32>, @@ -90,7 +90,7 @@ "crypto_ae_clk", "raid_ae_clk"; }; - lcpll0: lcpll0@0001d0c4 { + lcpll0: lcpll0@1d0c4 { #clock-cells = <1>; compatible = "brcm,sr-lcpll0"; reg = <0x0001d0c4 0x3c>, @@ -101,7 +101,7 @@ "clk_sata_500"; }; - lcpll1: lcpll1@0001d138 { + lcpll1: lcpll1@1d138 { #clock-cells = <1>; compatible = "brcm,sr-lcpll1"; reg = <0x0001d138 0x3c>, diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi index 8bf1dc6b46ca..9666969c8c88 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi @@ -36,7 +36,7 @@ #size-cells = <1>; ranges = <0x0 0x0 0x67000000 0x00800000>; - crypto_mbox: crypto_mbox@00000000 { + crypto_mbox: crypto_mbox@0 { compatible = "brcm,iproc-flexrm-mbox"; reg = <0x00000000 0x200000>; msi-parent = <&gic_its 0x4100>; @@ -44,7 +44,7 @@ dma-coherent; }; - raid_mbox: raid_mbox@00400000 { + raid_mbox: raid_mbox@400000 { compatible = "brcm,iproc-flexrm-mbox"; reg = <0x00400000 0x200000>; dma-coherent; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi index 15214d05fec1..8a3a770e8f2c 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi @@ -32,7 +32,7 @@ #include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h> - pinconf: pinconf@00140000 { + pinconf: pinconf@140000 { compatible = "pinconf-single"; reg = <0x00140000 0x250>; pinctrl-single,register-width = <32>; @@ -40,7 +40,7 @@ /* pinconf functions */ }; - pinmux: pinmux@0014029c { + pinmux: pinmux@14029c { compatible = "pinctrl-single"; reg = <0x0014029c 0x250>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi index a774709388df..4b5465da81d8 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi @@ -36,7 +36,7 @@ #size-cells = <1>; ranges = <0x0 0x0 0x67d00000 0x00800000>; - sata0: ahci@00210000 { + sata0: ahci@210000 { compatible = "brcm,iproc-ahci", "generic-ahci"; reg = <0x00210000 0x1000>; reg-names = "ahci"; @@ -52,7 +52,7 @@ }; }; - sata_phy0: sata_phy@00212100 { + sata_phy0: sata_phy@212100 { compatible = "brcm,iproc-sr-sata-phy"; reg = <0x00212100 0x1000>; reg-names = "phy"; @@ -66,7 +66,7 @@ }; }; - sata1: ahci@00310000 { + sata1: ahci@310000 { compatible = "brcm,iproc-ahci", "generic-ahci"; reg = <0x00310000 0x1000>; reg-names = "ahci"; @@ -82,7 +82,7 @@ }; }; - sata_phy1: sata_phy@00312100 { + sata_phy1: sata_phy@312100 { compatible = "brcm,iproc-sr-sata-phy"; reg = <0x00312100 0x1000>; reg-names = "phy"; @@ -96,7 +96,7 @@ }; }; - sata2: ahci@00120000 { + sata2: ahci@120000 { compatible = "brcm,iproc-ahci", "generic-ahci"; reg = <0x00120000 0x1000>; reg-names = "ahci"; @@ -112,7 +112,7 @@ }; }; - sata_phy2: sata_phy@00122100 { + sata_phy2: sata_phy@122100 { compatible = "brcm,iproc-sr-sata-phy"; reg = <0x00122100 0x1000>; reg-names = "phy"; @@ -126,7 +126,7 @@ }; }; - sata3: ahci@00130000 { + sata3: ahci@130000 { compatible = "brcm,iproc-ahci", "generic-ahci"; reg = <0x00130000 0x1000>; reg-names = "ahci"; @@ -142,7 +142,7 @@ }; }; - sata_phy3: sata_phy@00132100 { + sata_phy3: sata_phy@132100 { compatible = "brcm,iproc-sr-sata-phy"; reg = <0x00132100 0x1000>; reg-names = "phy"; @@ -156,7 +156,7 @@ }; }; - sata4: ahci@00330000 { + sata4: ahci@330000 { compatible = "brcm,iproc-ahci", "generic-ahci"; reg = <0x00330000 0x1000>; reg-names = "ahci"; @@ -172,7 +172,7 @@ }; }; - sata_phy4: sata_phy@00332100 { + sata_phy4: sata_phy@332100 { compatible = "brcm,iproc-sr-sata-phy"; reg = <0x00332100 0x1000>; reg-names = "phy"; @@ -186,7 +186,7 @@ }; }; - sata5: ahci@00400000 { + sata5: ahci@400000 { compatible = "brcm,iproc-ahci", "generic-ahci"; reg = <0x00400000 0x1000>; reg-names = "ahci"; @@ -202,7 +202,7 @@ }; }; - sata_phy5: sata_phy@00402100 { + sata_phy5: sata_phy@402100 { compatible = "brcm,iproc-sr-sata-phy"; reg = <0x00402100 0x1000>; reg-names = "phy"; @@ -216,7 +216,7 @@ }; }; - sata6: ahci@00410000 { + sata6: ahci@410000 { compatible = "brcm,iproc-ahci", "generic-ahci"; reg = <0x00410000 0x1000>; reg-names = "ahci"; @@ -232,7 +232,7 @@ }; }; - sata_phy6: sata_phy@00412100 { + sata_phy6: sata_phy@412100 { compatible = "brcm,iproc-sr-sata-phy"; reg = <0x00412100 0x1000>; reg-names = "phy"; @@ -246,7 +246,7 @@ }; }; - sata7: ahci@00420000 { + sata7: ahci@420000 { compatible = "brcm,iproc-ahci", "generic-ahci"; reg = <0x00420000 0x1000>; reg-names = "ahci"; @@ -262,7 +262,7 @@ }; }; - sata_phy7: sata_phy@00422100 { + sata_phy7: sata_phy@422100 { compatible = "brcm,iproc-sr-sata-phy"; reg = <0x00422100 0x1000>; reg-names = "phy"; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index e6f75c633623..99aaff0b6d72 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -42,7 +42,7 @@ #address-cells = <2>; #size-cells = <0>; - cpu@000 { + cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x0>; @@ -50,7 +50,7 @@ next-level-cache = <&CLUSTER0_L2>; }; - cpu@001 { + cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x1>; @@ -106,7 +106,7 @@ next-level-cache = <&CLUSTER3_L2>; }; - CLUSTER0_L2: l2-cache@000 { + CLUSTER0_L2: l2-cache@0 { compatible = "cache"; }; @@ -152,13 +152,13 @@ #size-cells = <1>; ranges = <0x0 0x0 0x61000000 0x05000000>; - ccn: ccn@00000000 { + ccn: ccn@0 { compatible = "arm,ccn-502"; reg = <0x00000000 0x900000>; interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; }; - gic: interrupt-controller@02c00000 { + gic: interrupt-controller@2c00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <1>; @@ -177,7 +177,7 @@ }; }; - smmu: mmu@03000000 { + smmu: mmu@3000000 { compatible = "arm,mmu-500"; reg = <0x03000000 0x80000>; #global-interrupts = <1>; @@ -258,7 +258,7 @@ #include "stingray-clock.dtsi" - gpio_crmu: gpio@00024800 { + gpio_crmu: gpio@24800 { compatible = "brcm,iproc-gpio"; reg = <0x00024800 0x4c>; ngpios = <6>; @@ -278,7 +278,7 @@ #include "stingray-pinctrl.dtsi" - mdio_mux_iproc: mdio-mux@0002023c { + mdio_mux_iproc: mdio-mux@2023c { compatible = "brcm,mdio-mux-iproc"; reg = <0x0002023c 0x14>; #address-cells = <1>; @@ -309,7 +309,7 @@ }; }; - pwm: pwm@00010000 { + pwm: pwm@10000 { compatible = "brcm,iproc-pwm"; reg = <0x00010000 0x1000>; clocks = <&crmu_ref25m>; @@ -317,7 +317,7 @@ status = "disabled"; }; - timer0: timer@00030000 { + timer0: timer@30000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00030000 0x1000>; interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; @@ -328,7 +328,7 @@ status = "disabled"; }; - timer1: timer@00040000 { + timer1: timer@40000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00040000 0x1000>; interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; @@ -338,7 +338,7 @@ clock-names = "timer1", "timer2", "apb_pclk"; }; - timer2: timer@00050000 { + timer2: timer@50000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00050000 0x1000>; interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; @@ -349,7 +349,7 @@ status = "disabled"; }; - timer3: timer@00060000 { + timer3: timer@60000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00060000 0x1000>; interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; @@ -360,7 +360,7 @@ status = "disabled"; }; - timer4: timer@00070000 { + timer4: timer@70000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00070000 0x1000>; interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; @@ -371,7 +371,7 @@ status = "disabled"; }; - timer5: timer@00080000 { + timer5: timer@80000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00080000 0x1000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; @@ -382,7 +382,7 @@ status = "disabled"; }; - timer6: timer@00090000 { + timer6: timer@90000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x00090000 0x1000>; interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; @@ -393,7 +393,7 @@ status = "disabled"; }; - timer7: timer@000a0000 { + timer7: timer@a0000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x000a0000 0x1000>; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; @@ -404,7 +404,7 @@ status = "disabled"; }; - i2c0: i2c@000b0000 { + i2c0: i2c@b0000 { compatible = "brcm,iproc-i2c"; reg = <0x000b0000 0x100>; #address-cells = <1>; @@ -414,7 +414,7 @@ status = "disabled"; }; - wdt0: watchdog@000c0000 { + wdt0: watchdog@c0000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x000c0000 0x1000>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; @@ -422,7 +422,7 @@ clock-names = "wdogclk", "apb_pclk"; }; - gpio_hsls: gpio@000d0000 { + gpio_hsls: gpio@d0000 { compatible = "brcm,iproc-gpio"; reg = <0x000d0000 0x864>; ngpios = <151>; @@ -448,7 +448,7 @@ <&pinmux 151 91 4>; }; - i2c1: i2c@000e0000 { + i2c1: i2c@e0000 { compatible = "brcm,iproc-i2c"; reg = <0x000e0000 0x100>; #address-cells = <1>; @@ -458,7 +458,7 @@ status = "disabled"; }; - uart0: uart@00100000 { + uart0: uart@100000 { device_type = "serial"; compatible = "snps,dw-apb-uart"; reg = <0x00100000 0x1000>; @@ -469,7 +469,7 @@ status = "disabled"; }; - uart1: uart@00110000 { + uart1: uart@110000 { device_type = "serial"; compatible = "snps,dw-apb-uart"; reg = <0x00110000 0x1000>; @@ -480,7 +480,7 @@ status = "disabled"; }; - uart2: uart@00120000 { + uart2: uart@120000 { device_type = "serial"; compatible = "snps,dw-apb-uart"; reg = <0x00120000 0x1000>; @@ -491,7 +491,7 @@ status = "disabled"; }; - uart3: uart@00130000 { + uart3: uart@130000 { device_type = "serial"; compatible = "snps,dw-apb-uart"; reg = <0x00130000 0x1000>; @@ -502,7 +502,7 @@ status = "disabled"; }; - ssp0: ssp@00180000 { + ssp0: ssp@180000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x00180000 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; @@ -514,7 +514,7 @@ status = "disabled"; }; - ssp1: ssp@00190000 { + ssp1: ssp@190000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x00190000 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; @@ -526,12 +526,12 @@ status = "disabled"; }; - hwrng: hwrng@00220000 { + hwrng: hwrng@220000 { compatible = "brcm,iproc-rng200"; reg = <0x00220000 0x28>; }; - dma0: dma@00310000 { + dma0: dma@310000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x00310000 0x1000>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, @@ -551,7 +551,7 @@ iommus = <&smmu 0x6000 0x0000>; }; - enet: ethernet@00340000{ + enet: ethernet@340000{ compatible = "brcm,amac"; reg = <0x00340000 0x1000>; reg-names = "amac_base"; @@ -560,7 +560,7 @@ status= "disabled"; }; - nand: nand@00360000 { + nand: nand@360000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x00360000 0x600>, <0x0050a408 0x600>, @@ -573,7 +573,7 @@ status = "disabled"; }; - sdio0: sdhci@003f1000 { + sdio0: sdhci@3f1000 { compatible = "brcm,sdhci-iproc"; reg = <0x003f1000 0x100>; interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; @@ -583,7 +583,7 @@ status = "disabled"; }; - sdio1: sdhci@003f2000 { + sdio1: sdhci@3f2000 { compatible = "brcm,sdhci-iproc"; reg = <0x003f2000 0x100>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dts b/arch/arm64/boot/dts/cavium/thunder-88xx.dts index 800ba65991f7..5ec2bfa5f714 100644 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dts +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dts @@ -60,7 +60,7 @@ serial1 = &uaa1; }; - memory@00000000 { + memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x0 0x80000000>; }; diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi index 04dc8a8d1539..1a9103b269cb 100644 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi @@ -62,97 +62,97 @@ #address-cells = <2>; #size-cells = <0>; - cpu@000 { + cpu@0 { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x000>; enable-method = "psci"; }; - cpu@001 { + cpu@1 { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x001>; enable-method = "psci"; }; - cpu@002 { + cpu@2 { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x002>; enable-method = "psci"; }; - cpu@003 { + cpu@3 { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x003>; enable-method = "psci"; }; - cpu@004 { + cpu@4 { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x004>; enable-method = "psci"; }; - cpu@005 { + cpu@5 { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x005>; enable-method = "psci"; }; - cpu@006 { + cpu@6 { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x006>; enable-method = "psci"; }; - cpu@007 { + cpu@7 { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x007>; enable-method = "psci"; }; - cpu@008 { + cpu@8 { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x008>; enable-method = "psci"; }; - cpu@009 { + cpu@9 { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x009>; enable-method = "psci"; }; - cpu@00a { + cpu@a { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x00a>; enable-method = "psci"; }; - cpu@00b { + cpu@b { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x00b>; enable-method = "psci"; }; - cpu@00c { + cpu@c { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x00c>; enable-method = "psci"; }; - cpu@00d { + cpu@d { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x00d>; enable-method = "psci"; }; - cpu@00e { + cpu@e { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x00e>; enable-method = "psci"; }; - cpu@00f { + cpu@f { device_type = "cpu"; compatible = "cavium,thunder", "arm,armv8"; reg = <0x0 0x00f>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts index 8c013b54db14..cdc4aee75227 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts @@ -93,6 +93,39 @@ }; }; +&dspi { + bus-num = <0>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a11", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst25wf040b", "jedec,spi-nor"; + spi-cpol; + spi-cpha; + reg = <1>; + spi-max-frequency = <10000000>; + }; + + flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "en25s64", "jedec,spi-nor"; + spi-cpol; + spi-cpha; + reg = <2>; + spi-max-frequency = <10000000>; + }; +}; + &duart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index fe1ea5d707a8..82b272fb41b9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -355,6 +355,19 @@ status = "disabled"; }; + dspi: dspi@2100000 { + compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + spi-num-chipselects = <5>; + big-endian; + status = "disabled"; + }; + duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; @@ -503,4 +516,11 @@ <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; }; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index d16b9cc1e825..380e7c713395 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -376,14 +376,14 @@ qman: qman@1880000 { compatible = "fsl,qman"; reg = <0x0 0x1880000 0x0 0x10000>; - interrupts = <0 45 0x4>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; memory-region = <&qman_fqd &qman_pfdr>; }; bman: bman@1890000 { compatible = "fsl,bman"; reg = <0x0 0x1890000 0x0 0x10000>; - interrupts = <0 45 0x4>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; memory-region = <&bman_fbpr>; }; @@ -749,6 +749,13 @@ }; }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + }; #include "qoriq-qman-portals.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index e8a478ca1485..06b5e12d04d8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -281,7 +281,7 @@ qman: qman@1880000 { compatible = "fsl,qman"; reg = <0x0 0x1880000 0x0 0x10000>; - interrupts = <0 45 0x4>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; memory-region = <&qman_fqd &qman_pfdr>; }; @@ -289,7 +289,7 @@ bman: bman@1890000 { compatible = "fsl,bman"; reg = <0x0 0x1890000 0x0 0x10000>; - interrupts = <0 45 0x4>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; memory-region = <&bman_fbpr>; }; @@ -764,6 +764,13 @@ no-map; }; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; #include "qoriq-qman-portals.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 33797b373674..bd80e9a2e67c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -147,6 +147,15 @@ <0x0 0x0c0d0000 0 0x1000>, /* GICH */ <0x0 0x0c0e0000 0 0x20000>; /* GICV */ interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + its: gic-its@6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; }; timer { @@ -434,6 +443,85 @@ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; }; }; + + pcie@3400000 { + compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; + }; + + pcie@3500000 { + compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; + }; + + pcie@3600000 { + compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-lanes = <8>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index 6aa319dae396..aeaef01d375f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -151,6 +151,7 @@ }; &pcie1 { + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -159,6 +160,7 @@ }; &pcie2 { + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -167,6 +169,7 @@ }; &pcie3 { + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -175,6 +178,7 @@ }; &pcie4 { + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 4fb9a0966a84..f3a40af33af8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -786,4 +786,11 @@ interrupts = <0 18 0x4>; little-endian; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index e9f87cb61ade..97d768730952 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -197,6 +197,325 @@ }; }; +/* + * Legend: proper name = the GPIO line is used as GPIO + * NC = not connected (pin out but not routed from the chip to + * anything the board) + * "[PER]" = pin is muxed for [peripheral] (not GPIO) + * "" = no idea, schematic doesn't say, could be + * unrouted (not connected to any external pin) + * LSEC = Low Speed External Connector + * HSEC = High Speed External Connector + * + * Line names are taken from "HiKey 960 Board ver A" schematics + * from Huawei. The 40 pin low speed expansion connector is named + * J2002 63453-140LF. + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Board naming of a line and the schematic name of + * the same line are in conflict, the 96Board specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART3. This is only for the informational lines i.e. "[FOO]", + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only + * ones actually used for GPIO. + */ +&gpio0 { + /* GPIO_000-GPIO_007 */ + gpio-line-names = + "", + "TP901", /* TEST_MODE connected to TP901 */ + "[PMU0_SSI]", + "[PMU1_SSI]", + "[PMU2_SSI]", + "[PMU0_CLKOUT]", + "[JTAG_TCK]", + "[JTAG_TMS]"; +}; + +&gpio1 { + /* GPIO_008-GPIO_015 */ + gpio-line-names = + "[JTAG_TRST_N]", + "[JTAG_TDI]", + "[JTAG_TDO]", + "NC", "NC", + "[I2C3_SCL]", + "[I2C3_SDA]", + "NC"; +}; + +&gpio2 { + /* GPIO_016-GPIO_023 */ + gpio-line-names = + "NC", "NC", "NC", + "GPIO-J", /* LSEC pin 32: GPIO_019 */ + "GPIO_020_HDMI_SEL", + "GPIO-L", /* LSEC pin 34: GPIO_021 */ + "GPIO_022_UFSBUCK_INT_N", + "GPIO-G"; /* LSEC pin 29: LCD_TE0 */ +}; + +&gpio3 { + /* GPIO_024-GPIO_031 */ + /* The rail from pin BK36 is named LCD_TE0, we assume to be muxed as GPIO for GPIO-G */ + gpio-line-names = + "[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */ + "[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */ + "NC", + "[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */ + "[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */ + "[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */ + "[I2C3_SDA]", /* HSEC pin 38: ISP_SDA1 */ + "NC"; +}; + +&gpio4 { + /* GPIO_032-GPIO_039 */ + gpio-line-names = + "NC", "NC", + "PWR_BTN_N", /* LSEC pin 4: GPIO_034_PWRON_DET */ + "GPIO_035_PMU2_EN", + "GPIO_036_USB_HUB_RESET", + "NC", "NC", "NC"; +}; + +&gpio5 { + /* GPIO_040-GPIO_047 */ + gpio-line-names = + "GPIO-H", /* LSEC pin 30: GPIO_040_LCD_RST_N */ + "GPIO_041_HDMI_PD", + "TP904", /* Test point */ + "TP905", /* Test point */ + "NC", "NC", + "GPIO_046_HUB_VDD33_EN", + "GPIO_047_PMU1_EN"; +}; + +&gpio6 { + /* GPIO_048-GPIO_055 */ + gpio-line-names = + "NC", "NC", "NC", + "GPIO_051_WIFI_EN", + "GPIO-I", /* LSEC pin 31: GPIO_052_CAM0_RST_N */ + /* + * These two pins should be used for SD(IO) data according to the + * 96boards specification but seems to be repurposed for a IRDA UART. + * They are however named according to the spec. + */ + "[SD_DAT1]", /* HSEC pin 3: UART0_IRDA_RXD */ + "[SD_DAT2]", /* HSEC pin 5: UART0_IRDA_TXD */ + "[UART1_RXD]"; /* LSEC pin 13: DEBUG_UART6_RXD */ +}; + +&gpio7 { + /* GPIO_056-GPIO_063 */ + gpio-line-names = + "[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */ + "[UART0_CTS]", /* LSEC pin 3: UART3_CTS_N */ + "[UART0_RTS]", /* LSEC pin 9: UART3_RTS_N */ + "[UART0_RXD]", /* LSEC pin 7: UART3_RXD */ + "[UART0_TXD]", /* LSEC pin 5: UART3_TXD */ + "[SOC_BT_UART4_CTS_N]", + "[SOC_BT_UART4_RTS_N]", + "[SOC_BT_UART4_RXD]"; +}; + +&gpio8 { + /* GPIO_064-GPIO_071 */ + gpio-line-names = + "[SOC_BT_UART4_TXD]", + "NC", + "[PMU_HKADC_SSI]", + "NC", + "GPIO_068_SEL", + "NC", "NC", "NC"; + +}; + +&gpio9 { + /* GPIO_072-GPIO_079 */ + gpio-line-names = + "NC", "NC", "NC", + "GPIO-K", /* LSEC pin 33: GPIO_075_CAM1_RST_N */ + "NC", "NC", "NC", "NC"; +}; + +&gpio10 { + /* GPIO_080-GPIO_087 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio11 { + /* GPIO_088-GPIO_095 */ + gpio-line-names = + "NC", + "[PCIE_PERST_N]", + "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio12 { + /* GPIO_096-GPIO_103 */ + gpio-line-names = "NC", "NC", "NC", "", "", "", "", "NC"; +}; + +&gpio13 { + /* GPIO_104-GPIO_111 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio14 { + /* GPIO_112-GPIO_119 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio15 { + /* GPIO_120-GPIO_127 */ + gpio-line-names = + "NC", "NC", "NC", "NC", "NC", "NC", + "GPIO_126_BT_EN", + "TP902"; /* GPIO_127_JTAG_SEL0 */ +}; + +&gpio16 { + /* GPIO_128-GPIO_135 */ + gpio-line-names = "", "", "", "", "", "", "", ""; +}; + +&gpio17 { + /* GPIO_136-GPIO_143 */ + gpio-line-names = "", "", "", "", "", "", "", ""; +}; + +&gpio18 { + /* GPIO_144-GPIO_151 */ + gpio-line-names = + "[UFS_REF_CLK]", + "[UFS_RST_N]", + "[SPI1_SCLK]", /* HSEC pin 9: GPIO_146_SPI3_CLK */ + "[SPI1_DIN]", /* HSEC pin 11: GPIO_147_SPI3_DI */ + "[SPI1_DOUT]", /* HSEC pin 1: GPIO_148_SPI3_DO */ + "[SPI1_CS]", /* HSEC pin 7: GPIO_149_SPI3_CS0_N */ + "GPIO_150_USER_LED1", + "GPIO_151_USER_LED2"; +}; + +&gpio19 { + /* GPIO_152-GPIO_159 */ + gpio-line-names = "NC", "NC", "NC", "NC", "", "", "", ""; +}; + +&gpio20 { + /* GPIO_160-GPIO_167 */ + gpio-line-names = + "[SD_CLK]", + "[SD_CMD]", + "[SD_DATA0]", + "[SD_DATA1]", + "[SD_DATA2]", + "[SD_DATA3]", + "", ""; +}; + +&gpio21 { + /* GPIO_168-GPIO_175 */ + gpio-line-names = + "[WL_SDIO_CLK]", + "[WL_SDIO_CMD]", + "[WL_SDIO_DATA0]", + "[WL_SDIO_DATA1]", + "[WL_SDIO_DATA2]", + "[WL_SDIO_DATA3]", + "", ""; +}; + +&gpio22 { + /* GPIO_176-GPIO_183 */ + gpio-line-names = + "[GPIO_176_PMU_PWR_HOLD]", + "NA", + "[SYSCLK_EN]", + "GPIO_179_WL_WAKEUP_AP", + "GPIO_180_HDMI_INT", + "NA", + "GPIO-F", /* LSEC pin 28: LCD_BL_PWM */ + "[I2C0_SCL]"; /* LSEC pin 15 */ +}; + +&gpio23 { + /* GPIO_184-GPIO_191 */ + gpio-line-names = + "[I2C0_SDA]", /* LSEC pin 17 */ + "[I2C1_SCL]", /* Actual SoC I2C1 */ + "[I2C1_SDA]", /* Actual SoC I2C1 */ + "[I2C1_SCL]", /* LSEC pin 19: I2C7_SCL */ + "[I2C1_SDA]", /* LSEC pin 21: I2C7_SDA */ + "GPIO_189_USER_LED3", + "GPIO_190_USER_LED4", + ""; +}; + +&gpio24 { + /* GPIO_192-GPIO_199 */ + gpio-line-names = + "[PCM_DI]", /* LSEC pin 22: GPIO_192_I2S0_DI */ + "[PCM_DO]", /* LSEC pin 20: GPIO_193_I2S0_DO */ + "[PCM_CLK]", /* LSEC pin 18: GPIO_194_I2S0_XCLK */ + "[PCM_FS]", /* LSEC pin 16: GPIO_195_I2S0_XFS */ + "[GPIO_196_I2S2_DI]", + "[GPIO_197_I2S2_DO]", + "[GPIO_198_I2S2_XCLK]", + "[GPIO_199_I2S2_XFS]"; +}; + +&gpio25 { + /* GPIO_200-GPIO_207 */ + gpio-line-names = + "NC", + "NC", + "GPIO_202_VBUS_TYPEC", + "GPIO_203_SD_DET", + "GPIO_204_PMU12_IRQ_N", + "GPIO_205_WIFI_ACTIVE", + "GPIO_206_USBSW_SEL", + "GPIO_207_BT_ACTIVE"; +}; + +&gpio26 { + /* GPIO_208-GPIO_215 */ + gpio-line-names = + "GPIO-A", /* LSEC pin 23: GPIO_208 */ + "GPIO-B", /* LSEC pin 24: GPIO_209 */ + "GPIO-C", /* LSEC pin 25: GPIO_210 */ + "GPIO-D", /* LSEC pin 26: GPIO_211 */ + "GPIO-E", /* LSEC pin 27: GPIO_212 */ + "[PCIE_CLKREQ_N]", + "[PCIE_WAKE_N]", + "[SPI0_CLK]"; /* LSEC pin 8: SPI2_CLK */ +}; + +&gpio27 { + /* GPIO_216-GPIO_223 */ + gpio-line-names = + "[SPI0_DIN]", /* LSEC pin 10: SPI2_DI */ + "[SPI0_DOUT]", /* LSEC pin 14: SPI2_DO */ + "[SPI0_CS]", /* LSEC pin 12: SPI2_CS0_N */ + "GPIO_219_CC_INT", + "NC", + "NC", + "[PMU_INT]", + ""; +}; + +&gpio28 { + /* GPIO_224-GPIO_231 */ + gpio-line-names = + "", "", "", "", "", "", "", ""; +}; + &i2c0 { /* On Low speed expansion */ label = "LS-I2C0"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 13ae69f5a327..ab0b95ba5ae5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -979,5 +979,12 @@ clocks = <&crg_ctrl HI3660_OSC32K>; clock-names = "apb_pclk"; }; + + tsensor: tsensor@fff30000 { + compatible = "hisilicon,hi3660-tsensor"; + reg = <0x0 0xfff30000 0x0 0x1000>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + #thermal-sensor-cells = <1>; + }; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts index b9142871d6fe..a6fd13389f8d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts @@ -78,17 +78,17 @@ &gpio1 { status = "okay"; - gpio-line-names = "LS-GPIO-E", "", + gpio-line-names = "GPIO-E", "", "", "", - "", "LS-GPIO-F", - "", "LS-GPIO-J"; + "", "GPIO-F", + "", "GPIO-J"; }; &gpio2 { status = "okay"; - gpio-line-names = "LS-GPIO-H", "LS-GPIO-I", - "LS-GPIO-L", "LS-GPIO-G", - "LS-GPIO-K", "", + gpio-line-names = "GPIO-H", "GPIO-I", + "GPIO-L", "GPIO-G", + "GPIO-K", "", "", ""; }; @@ -96,15 +96,15 @@ status = "okay"; gpio-line-names = "", "", "", "", - "LS-GPIO-C", "", - "", "LS-GPIO-B"; + "GPIO-C", "", + "", "GPIO-B"; }; &gpio4 { status = "okay"; gpio-line-names = "", "", "", "", - "", "LS-GPIO-D", + "", "GPIO-D", "", ""; }; @@ -112,7 +112,7 @@ status = "okay"; gpio-line-names = "", "USER-LED-1", "USER-LED-2", "", - "", "LS-GPIO-A", + "", "GPIO-A", "", ""; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi new file mode 100644 index 000000000000..7afee5d5087b --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi @@ -0,0 +1,381 @@ +/* + * dtsi file for Hisilicon Hi6220 coresight + * + * Copyright (C) 2017 Hisilicon Ltd. + * + * Author: Pengcheng Li <lipengcheng8@huawei.com> + * Leo Yan <leo.yan@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +/ { + soc { + funnel@f6401000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xf6401000 0 0x1000>; + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + soc_funnel_out: endpoint { + remote-endpoint = + <&etf_in>; + }; + }; + + port@1 { + reg = <0>; + soc_funnel_in: endpoint { + slave-mode; + remote-endpoint = + <&acpu_funnel_out>; + }; + }; + }; + }; + + etf@f6402000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xf6402000 0 0x1000>; + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etf_in: endpoint { + slave-mode; + remote-endpoint = + <&soc_funnel_out>; + }; + }; + + port@1 { + reg = <0>; + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + }; + + replicator { + compatible = "arm,coresight-replicator"; + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_in: endpoint { + slave-mode; + remote-endpoint = + <&etf_out>; + }; + }; + + port@1 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = + <&etr_in>; + }; + }; + + port@2 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = + <&tpiu_in>; + }; + }; + }; + }; + + etr@f6404000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xf6404000 0 0x1000>; + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etr_in: endpoint { + slave-mode; + remote-endpoint = + <&replicator_out0>; + }; + }; + }; + }; + + tpiu@f6405000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0xf6405000 0 0x1000>; + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpiu_in: endpoint { + slave-mode; + remote-endpoint = + <&replicator_out1>; + }; + }; + }; + }; + + funnel@f6501000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xf6501000 0 0x1000>; + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + acpu_funnel_out: endpoint { + remote-endpoint = + <&soc_funnel_in>; + }; + }; + + port@1 { + reg = <0>; + acpu_funnel_in0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out>; + }; + }; + + port@2 { + reg = <1>; + acpu_funnel_in1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out>; + }; + }; + + port@3 { + reg = <2>; + acpu_funnel_in2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out>; + }; + }; + + port@4 { + reg = <3>; + acpu_funnel_in3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out>; + }; + }; + + port@5 { + reg = <4>; + acpu_funnel_in4: endpoint { + slave-mode; + remote-endpoint = + <&etm4_out>; + }; + }; + + port@6 { + reg = <5>; + acpu_funnel_in5: endpoint { + slave-mode; + remote-endpoint = + <&etm5_out>; + }; + }; + + port@7 { + reg = <6>; + acpu_funnel_in6: endpoint { + slave-mode; + remote-endpoint = + <&etm6_out>; + }; + }; + + port@8 { + reg = <7>; + acpu_funnel_in7: endpoint { + slave-mode; + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + etm@f659c000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf659c000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu0>; + + port { + etm0_out: endpoint { + remote-endpoint = + <&acpu_funnel_in0>; + }; + }; + }; + + etm@f659d000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf659d000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu1>; + + port { + etm1_out: endpoint { + remote-endpoint = + <&acpu_funnel_in1>; + }; + }; + }; + + etm@f659e000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf659e000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu2>; + + port { + etm2_out: endpoint { + remote-endpoint = + <&acpu_funnel_in2>; + }; + }; + }; + + etm@f659f000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf659f000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu3>; + + port { + etm3_out: endpoint { + remote-endpoint = + <&acpu_funnel_in3>; + }; + }; + }; + + etm@f65dc000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf65dc000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu4>; + + port { + etm4_out: endpoint { + remote-endpoint = + <&acpu_funnel_in4>; + }; + }; + }; + + etm@f65dd000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf65dd000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu5>; + + port { + etm5_out: endpoint { + remote-endpoint = + <&acpu_funnel_in5>; + }; + }; + }; + + etm@f65de000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf65de000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu6>; + + port { + etm6_out: endpoint { + remote-endpoint = + <&acpu_funnel_in6>; + }; + }; + }; + + etm@f65df000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf65df000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu7>; + + port { + etm7_out: endpoint { + remote-endpoint = + <&acpu_funnel_in7>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index ff1dc89f599e..6a180d1926e8 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -987,3 +987,5 @@ }; }; }; + +#include "hi6220-coresight.dtsi" diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts index abba750b87f8..3bbd017f088f 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts @@ -18,7 +18,7 @@ model = "Hisilicon Hip05 D02 Development Board"; compatible = "hisilicon,hip05-d02"; - memory@00000000 { + memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x0 0x80000000>; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts index 7c4114a67753..9af633021a42 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts +++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts @@ -17,7 +17,7 @@ model = "Hisilicon Hip06 D03 Development Board"; compatible = "hisilicon,hip06-d03"; - memory@00000000 { + memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x0 0x40000000>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index 9df0f06ce607..0f3468e777f7 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -94,6 +94,16 @@ 3300000 0x0>; enable-active-high; }; + + vcc_sd_reg2: regulator-vmcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_sd2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; + }; }; /* Gigabit module on CON19(V2.0)/CON21(V1.4) */ @@ -179,6 +189,7 @@ bus-width = <4>; marvell,pad-type = "sd"; vqmmc-supply = <&vcc_sd_reg1>; + vmmc-supply = <&vcc_sd_reg2>; status = "okay"; }; @@ -216,7 +227,7 @@ /* * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through - * an FTDI + * an FTDI (also on CON24(V2.0)/CON26(V1.4)). */ &uart0 { pinctrl-names = "default"; @@ -224,6 +235,13 @@ status = "okay"; }; +/* CON26(V2.0)/CON28(V1.4) */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + /* CON27(V2.0)/CON29(V1.4) */ &usb2 { status = "okay"; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index 2ce52ba74f73..bdfb5553ddb5 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -98,9 +98,21 @@ /* Exported on the micro USB connector J5 through an FTDI */ &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; status = "okay"; }; +/* + * Connector J17 and J18 expose a number of different features. Some pins are + * multiplexed. This is the case for instance for the following features: + * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of + * how to enable it. Beware that the signals are 1.8V TTL. + * - I2C + * - SPI + * - MMC + */ + /* J7 */ &usb3 { status = "okay"; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 8c0cf7efac65..90c26d616a54 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -55,6 +55,7 @@ aliases { serial0 = &uart0; + serial1 = &uart1; }; cpus { @@ -134,8 +135,24 @@ uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x400>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x12000 0x200>; + clocks = <&xtalclk>; + interrupts = + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uart-sum", "uart-tx", "uart-rx"; + status = "disabled"; + }; + + uart1: serial@12200 { + compatible = "marvell,armada-3700-uart-ext"; + reg = <0x12200 0x30>; + clocks = <&xtalclk>; + interrupts = + <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "uart-tx", "uart-rx"; status = "disabled"; }; @@ -183,7 +200,6 @@ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - }; xtalclk: xtal-clk { diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts index 9c3bdf87e543..52b5341cb270 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts @@ -56,7 +56,7 @@ stdout-path = "serial0:115200n8"; }; - memory@00000000 { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; @@ -124,6 +124,8 @@ &uart0 { status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; }; @@ -141,9 +143,49 @@ gpio-controller; #gpio-cells = <2>; reg = <0x21>; + /* + * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect + * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit + * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN + * IO0_3: USB2_DEVICE_DETECT + * IO0_4: GPIO_0 IO1_4: SD_Status + * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable + * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC + * IO0_7: IO1_7: SDIO_Vcntrl + */ }; }; +&cpm_nand { + /* + * SPI on CPM and NAND have common pins on this board. We can + * use only one at a time. To enable the NAND (whihch will + * disable the SPI), the "status = "okay";" line have to be + * added here. + */ + num-cs = <1>; + pinctrl-0 = <&nand_pins>, <&nand_rb>; + pinctrl-names = "default"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "Linux"; + reg = <0x200000 0xe00000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; +}; + + &cpm_spi1 { status = "okay"; @@ -197,7 +239,7 @@ status = "okay"; bus-width = <4>; no-1-8-v; - non-removable; + cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>; }; &cpm_mdio { @@ -215,10 +257,21 @@ status = "okay"; }; +&cpm_eth0 { + status = "okay"; + /* Network PHY */ + phy-mode = "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys = <&cpm_comphy2 0>; +}; + &cpm_eth1 { status = "okay"; + /* Network PHY */ phy = <&phy0>; phy-mode = "sgmii"; + /* Generic PHY, providing serdes lanes */ + phys = <&cpm_comphy0 1>; }; &cpm_eth2 { diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi index 860b6ae9dcc5..0e1a1e5be399 100644 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi @@ -64,5 +64,19 @@ &cpm_syscon0 { cpm_pinctrl: pinctrl { compatible = "marvell,armada-7k-pinctrl"; + + nand_pins: nand-pins { + marvell,pins = + "mpp15", "mpp16", "mpp17", "mpp18", + "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function = "dev"; + }; + + nand_rb: nand-rb { + marvell,pins = "mpp13"; + marvell,function = "nf"; + }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index 0d7b2ae46610..d97b72bed662 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -56,7 +56,7 @@ stdout-path = "serial0:115200n8"; }; - memory@00000000 { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; @@ -139,8 +139,14 @@ /* Accessible over the mini-USB CON9 connector on the main board */ &uart0 { status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; }; +/* CON6 on CP0 expansion */ +&cpm_pcie0 { + status = "okay"; +}; /* CON5 on CP0 expansion */ &cpm_pcie2 { @@ -200,12 +206,27 @@ status = "okay"; }; +&cpm_eth0 { + status = "okay"; + phy-mode = "10gbase-kr"; +}; + &cpm_eth2 { status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; }; +/* CON6 on CP1 expansion */ +&cps_pcie0 { + status = "okay"; +}; + +/* CON7 on CP1 expansion */ +&cps_pcie1 { + status = "okay"; +}; + /* CON5 on CP1 expansion */ &cps_pcie2 { status = "okay"; @@ -216,6 +237,37 @@ clock-frequency = <100000>; }; +&cps_spi1 { + status = "okay"; + + spi-flash@0 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <20000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Boot"; + reg = <0x0 0x200000>; + }; + partition@200000 { + label = "Filesystem"; + reg = <0x200000 0xd00000>; + }; + partition@f00000 { + label = "Boot_2nd"; + reg = <0xf00000 0x100000>; + }; + }; + }; +}; + /* CON4 on CP1 expansion */ &cps_sata0 { status = "okay"; @@ -244,6 +296,11 @@ status = "okay"; }; +&cps_eth0 { + status = "okay"; + phy-mode = "10gbase-kr"; +}; + &cps_eth1 { status = "okay"; phy = <&phy0>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts index acf5c7d16d79..b3350827ee55 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts @@ -57,7 +57,7 @@ stdout-path = "serial0:115200n8"; }; - memory@00000000 { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; @@ -101,6 +101,8 @@ &uart0 { status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; }; &ap_sdhci0 { @@ -222,8 +224,11 @@ &cpm_eth0 { status = "okay"; + /* Network PHY */ phy = <&phy0>; phy-mode = "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys = <&cpm_comphy4 0>; }; &cpm_sata0 { @@ -257,15 +262,21 @@ &cps_eth0 { status = "okay"; + /* Network PHY */ phy = <&phy8>; phy-mode = "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys = <&cps_comphy4 0>; }; &cps_eth1 { /* CPS Lane 0 - J5 (Gigabit RJ45) */ status = "okay"; + /* Network PHY */ phy = <&ge_phy>; phy-mode = "sgmii"; + /* Generic PHY, providing serdes lanes */ + phys = <&cps_comphy0 1>; }; &cps_pinctrl { diff --git a/arch/arm64/boot/dts/marvell/armada-8080-db.dts b/arch/arm64/boot/dts/marvell/armada-8080-db.dts index 707af833832b..85b58a19a9fb 100644 --- a/arch/arm64/boot/dts/marvell/armada-8080-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8080-db.dts @@ -55,7 +55,7 @@ stdout-path = "serial0:115200n8"; }; - memory@00000000 { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index 95a1ff60f6c1..b98ea137371d 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -54,13 +54,13 @@ #address-cells = <1>; #size-cells = <0>; - cpu@000 { + cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x000>; enable-method = "psci"; }; - cpu@001 { + cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x001>; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi index ba43a4357b89..116164ff260f 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi @@ -54,13 +54,13 @@ #address-cells = <1>; #size-cells = <0>; - cpu@000 { + cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x000>; enable-method = "psci"; }; - cpu@001 { + cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x001>; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index 30d48ecf46e0..1c4dd8ab9ad5 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -241,6 +241,12 @@ }; + watchdog: watchdog@600000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x610000 0x1000>, <0x600000 0x1000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + }; + ap_sdhci0: sdhci@6e0000 { compatible = "marvell,armada-ap806-sdhci"; reg = <0x6e0000 0x300>; @@ -263,6 +269,11 @@ ap_pinctrl: pinctrl { compatible = "marvell,ap806-pinctrl"; + + uart0_pins: uart0-pins { + marvell,pins = "mpp11", "mpp19"; + marvell,function = "uart0"; + }; }; ap_gpio: gpio@1040 { diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi index bf1b22b70384..7f0661e12f5e 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi @@ -52,13 +52,13 @@ #size-cells = <0>; compatible = "marvell,armada-ap810-octa"; - cpu@000 { + cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x000>; enable-method = "psci"; }; - cpu@001 { + cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x001>; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index f2aa2a81de4d..e3b64d03fbd8 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -74,9 +74,10 @@ <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>, <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>, <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>, - <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>; + <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <0>; gop-port-id = <0>; status = "disabled"; @@ -87,9 +88,10 @@ <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>, <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>, <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>, - <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>; + <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <1>; gop-port-id = <2>; status = "disabled"; @@ -100,15 +102,54 @@ <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>, <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>, <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>, - <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>; + <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <2>; gop-port-id = <3>; status = "disabled"; }; }; + cpm_comphy: phy@120000 { + compatible = "marvell,comphy-cp110"; + reg = <0x120000 0x6000>; + marvell,system-controller = <&cpm_syscon0>; + #address-cells = <1>; + #size-cells = <0>; + + cpm_comphy0: phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + + cpm_comphy1: phy@1 { + reg = <1>; + #phy-cells = <1>; + }; + + cpm_comphy2: phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + + cpm_comphy3: phy@3 { + reg = <3>; + #phy-cells = <1>; + }; + + cpm_comphy4: phy@4 { + reg = <4>; + #phy-cells = <1>; + }; + + cpm_comphy5: phy@5 { + reg = <5>; + #phy-cells = <1>; + }; + }; + cpm_mdio: mdio@12a200 { #address-cells = <1>; #size-cells = <0>; @@ -143,7 +184,7 @@ cpm_syscon0: system-controller@440000 { compatible = "syscon", "simple-mfd"; - reg = <0x440000 0x1000>; + reg = <0x440000 0x2000>; cpm_clk: clock { compatible = "marvell,cp110-clock"; @@ -274,12 +315,14 @@ * this controller is only usable on the CPM * for A7K and on the CPS for A8K. */ - compatible = "marvell,armada370-nand"; + compatible = "marvell,armada-8k-nand", + "marvell,armada370-nand"; reg = <0x720000 0x54>; #address-cells = <1>; #size-cells = <1>; interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpm_clk 1 2>; + marvell,system-controller = <&cpm_syscon0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 4fe70323abb3..0d51096c69f8 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -74,9 +74,10 @@ <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>, <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>, <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>, - <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>; + <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <0>; gop-port-id = <0>; status = "disabled"; @@ -87,9 +88,10 @@ <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>, <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>, <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>, - <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>; + <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <1>; gop-port-id = <2>; status = "disabled"; @@ -100,15 +102,54 @@ <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>, <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>, <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>, - <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>; + <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <2>; gop-port-id = <3>; status = "disabled"; }; }; + cps_comphy: phy@120000 { + compatible = "marvell,comphy-cp110"; + reg = <0x120000 0x6000>; + marvell,system-controller = <&cps_syscon0>; + #address-cells = <1>; + #size-cells = <0>; + + cps_comphy0: phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + + cps_comphy1: phy@1 { + reg = <1>; + #phy-cells = <1>; + }; + + cps_comphy2: phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + + cps_comphy3: phy@3 { + reg = <3>; + #phy-cells = <1>; + }; + + cps_comphy4: phy@4 { + reg = <4>; + #phy-cells = <1>; + }; + + cps_comphy5: phy@5 { + reg = <5>; + #phy-cells = <1>; + }; + }; + cps_mdio: mdio@12a200 { #address-cells = <1>; #size-cells = <0>; @@ -143,7 +184,7 @@ cps_syscon0: system-controller@440000 { compatible = "syscon", "simple-mfd"; - reg = <0x440000 0x1000>; + reg = <0x440000 0x2000>; cps_clk: clock { compatible = "marvell,cp110-clock"; @@ -275,7 +316,8 @@ * this controller is only usable on the CPM * for A7K and on the CPS for A8K. */ - compatible = "marvell,armada370-nand"; + compatible = "marvell,armada370-nand", + "marvell,armada370-nand"; reg = <0x720000 0x54>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi index d6b800fd26d0..d2f88b92d8e2 100644 --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi @@ -167,7 +167,7 @@ ranges = <0 0xe80000 0x10000>; interrupt-parent = <&aic>; - gpio0: gpio@0400 { + gpio0: gpio@400 { compatible = "snps,dw-apb-gpio"; reg = <0x0400 0x400>; #address-cells = <1>; @@ -185,7 +185,7 @@ }; }; - gpio1: gpio@0800 { + gpio1: gpio@800 { compatible = "snps,dw-apb-gpio"; reg = <0x0800 0x400>; #address-cells = <1>; @@ -203,7 +203,7 @@ }; }; - gpio2: gpio@0c00 { + gpio2: gpio@c00 { compatible = "snps,dw-apb-gpio"; reg = <0x0c00 0x400>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 57d0396b7faa..5d4e406bb35d 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -39,6 +39,7 @@ device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x000>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu1: cpu@1 { @@ -46,6 +47,7 @@ compatible = "arm,cortex-a35"; reg = <0x001>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu2: cpu@200 { @@ -53,6 +55,29 @@ compatible = "arm,cortex-a72"; reg = <0x200>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <100>; + exit-latency-us = <80>; + min-residency-us = <2000>; + arm,psci-suspend-param = <0x0010000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <350>; + exit-latency-us = <80>; + min-residency-us = <3000>; + arm,psci-suspend-param = <0x1010000>; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index c71d762bf697..42a23997dcdb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -50,6 +50,30 @@ vmmc-supply = <&vdd_sd>; }; + pcie@10003000 { + status = "okay"; + + dvdd-pex-supply = <&vdd_pex>; + hvdd-pex-pll-supply = <&vdd_1v8>; + hvdd-pex-supply = <&vdd_1v8>; + vddio-pexctl-aud-supply = <&vdd_1v8>; + + pci@1,0 { + nvidia,num-lanes = <4>; + status = "okay"; + }; + + pci@2,0 { + nvidia,num-lanes = <0>; + status = "disabled"; + }; + + pci@3,0 { + nvidia,num-lanes = <1>; + status = "disabled"; + }; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index a9c3eef6c4e0..46d1f287fb0f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/mailbox/tegra186-hsp.h> #include <dt-bindings/power/tegra186-powergate.h> #include <dt-bindings/reset/tegra186-reset.h> +#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> / { compatible = "nvidia,tegra186"; @@ -356,6 +357,116 @@ nvidia,bpmp = <&bpmp>; }; + pcie@10003000 { + compatible = "nvidia,tegra186-pcie"; + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; + device_type = "pci"; + reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ + 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ + 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ + 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ + 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ + 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ + + clocks = <&bpmp TEGRA186_CLK_AFI>, + <&bpmp TEGRA186_CLK_PCIE>, + <&bpmp TEGRA186_CLK_PLLE>; + clock-names = "afi", "pex", "pll_e"; + + resets = <&bpmp TEGRA186_RESET_AFI>, + <&bpmp TEGRA186_RESET_PCIE>, + <&bpmp TEGRA186_RESET_PCIEXCLK>; + reset-names = "afi", "pex", "pcie_x"; + + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; + reg = <0x001800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + + host1x@13e00000 { + compatible = "nvidia,tegra186-host1x", "simple-bus"; + reg = <0x0 0x13e00000 0x0 0x10000>, + <0x0 0x13e10000 0x0 0x10000>; + reg-names = "hypervisor", "vm"; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA186_CLK_HOST1X>; + clock-names = "host1x"; + resets = <&bpmp TEGRA186_RESET_HOST1X>; + reset-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x15000000 0x0 0x15000000 0x01000000>; + + vic@15340000 { + compatible = "nvidia,tegra186-vic"; + reg = <0x15340000 0x40000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA186_CLK_VIC>; + clock-names = "vic"; + resets = <&bpmp TEGRA186_RESET_VIC>; + reset-names = "vic"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; + }; + }; + gpu@17000000 { compatible = "nvidia,gp10b"; reg = <0x0 0x17000000 0x0 0x1000000>, @@ -444,6 +555,7 @@ shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; bpmp_i2c: i2c { compatible = "nvidia,tegra186-bpmp-i2c"; @@ -452,6 +564,108 @@ #size-cells = <0>; status = "disabled"; }; + + bpmp_thermal: thermal { + compatible = "nvidia,tegra186-bpmp-thermal"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + a57 { + polling-delay = <0>; + polling-delay-passive = <1000>; + + thermal-sensors = + <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; + + trips { + critical { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + + denver { + polling-delay = <0>; + polling-delay-passive = <1000>; + + thermal-sensors = + <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; + + trips { + critical { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + + gpu { + polling-delay = <0>; + polling-delay-passive = <1000>; + + thermal-sensors = + <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; + + trips { + critical { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + + pll { + polling-delay = <0>; + polling-delay-passive = <1000>; + + thermal-sensors = + <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; + + trips { + critical { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + + always_on { + polling-delay = <0>; + polling-delay-passive = <1000>; + + thermal-sensors = + <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; + + trips { + critical { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; }; timer { diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 1d63e6b879de..33a3297eb284 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -19,6 +19,30 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/sound/apq8016-lpass.h> +/* + * GPIO name legend: proper name = the GPIO line is used as GPIO + * NC = not connected (pin out but not routed from the chip to + * anything the board) + * "[PER]" = pin is muxed for [peripheral] (not GPIO) + * LSEC = Low Speed External Connector + * HSEC = High Speed External Connector + * + * Line names are taken from the schematic "DragonBoard410c" + * dated monday, august 31, 2015. Page 5 in particular. + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Board naming of a line and the schematic name of + * the same line are in conflict, the 96Board specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART3. This is only for the informational lines i.e. "[FOO]", + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only + * ones actually used for GPIO. + */ + / { aliases { serial0 = &blsp1_uart2; @@ -47,6 +71,132 @@ }; soc { + pinctrl@1000000 { + gpio-line-names = + "[UART0_TX]", /* GPIO_0, LSEC pin 5 */ + "[UART0_RX]", /* GPIO_1, LSEC pin 7 */ + "[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */ + "[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */ + "[UART1_TX]", /* GPIO_4, LSEC pin 11 */ + "[UART1_RX]", /* GPIO_5, LSEC pin 13 */ + "[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */ + "[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */ + "[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */ + "[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */ + "[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */ + "[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */ + "GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */ + "GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */ + "[I2C3_SDA]", /* HSEC pin 38 */ + "[I2C3_SCL]", /* HSEC pin 36 */ + "[SPI0_MOSI]", /* LSEC pin 14 */ + "[SPI0_MISO]", /* LSEC pin 10 */ + "[SPI0_CS_N]", /* LSEC pin 12 */ + "[SPI0_CLK]", /* LSEC pin 8 */ + "HDMI_HPD_N", /* GPIO 20 */ + "USR_LED_1_CTRL", + "[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */ + "[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */ + "GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */ + "GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */ + "[CSI0_MCLK]", /* HSEC pin 15 */ + "[CSI1_MCLK]", /* HSEC pin 17 */ + "GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */ + "[I2C2_SDA]", /* HSEC pin 34 */ + "[I2C2_SCL]", /* HSEC pin 32 */ + "DSI2HDMI_INT_N", + "DSI_SW_SEL_APQ", + "GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */ + "GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */ + "GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */ + "GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */ + "FORCED_USB_BOOT", + "SD_CARD_DET_N", + "[WCSS_BT_SSBI]", + "[WCSS_WLAN_DATA_2]", /* GPIO 40 */ + "[WCSS_WLAN_DATA_1]", + "[WCSS_WLAN_DATA_0]", + "[WCSS_WLAN_SET]", + "[WCSS_WLAN_CLK]", + "[WCSS_FM_SSBI]", + "[WCSS_FM_SDI]", + "[WCSS_BT_DAT_CTL]", + "[WCSS_BT_DAT_STB]", + "NC", + "NC", /* GPIO 50 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", /* GPIO 60 */ + "NC", + "NC", + "[CDC_PDM0_CLK]", + "[CDC_PDM0_SYNC]", + "[CDC_PDM0_TX0]", + "[CDC_PDM0_RX0]", + "[CDC_PDM0_RX1]", + "[CDC_PDM0_RX2]", + "GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */ + "NC", /* GPIO 70 */ + "NC", + "NC", + "NC", + "NC", /* GPIO 74 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "BOOT_CONFIG_0", /* GPIO 80 */ + "BOOT_CONFIG_1", + "BOOT_CONFIG_2", + "BOOT_CONFIG_3", + "NC", + "NC", + "BOOT_CONFIG_5", + "NC", + "NC", + "NC", + "NC", /* GPIO 90 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", /* GPIO 100 */ + "NC", + "NC", + "NC", + "SSBI_GPS", + "NC", + "NC", + "KEY_VOLP_N", + "NC", + "NC", + "[LS_EXP_MI2S_WS]", /* GPIO 110 */ + "NC", + "NC", + "[LS_EXP_MI2S_SCK]", + "[LS_EXP_MI2S_DATA0]", + "GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */ + "NC", + "[DSI2HDMI_MI2S_WS]", + "[DSI2HDMI_MI2S_SCK]", + "[DSI2HDMI_MI2S_DATA0]", + "USR_LED_2_CTRL", /* GPIO 120 */ + "SB_HS_ID"; + }; + dma@7884000 { status = "okay"; }; @@ -192,7 +342,7 @@ }; }; - sdhci@07824000 { + sdhci@7824000 { vmmc-supply = <&pm8916_l8>; vqmmc-supply = <&pm8916_l5>; @@ -202,7 +352,7 @@ status = "okay"; }; - sdhci@07864000 { + sdhci@7864000 { vmmc-supply = <&pm8916_l11>; vqmmc-supply = <&pm8916_l12>; @@ -232,7 +382,7 @@ }; }; - lpass@07708000 { + lpass@7708000 { status = "okay"; }; @@ -329,6 +479,25 @@ }; }; + spmi@200f000 { + pm8916@0 { + gpios@c000 { + gpio-line-names = + "USR_LED_3_CTRL", + "USR_LED_4_CTRL", + "USB_HUB_RESET_N_PM", + "USB_SW_SEL_PM"; + }; + mpps@a000 { + gpio-line-names = + "VDD_PX_BIAS", + "WLAN_LED_CTRL", + "BT_LED_CTRL", + "GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */ + }; + }; + }; + wcnss@a21b000 { status = "okay"; }; @@ -379,6 +548,8 @@ status = "okay"; clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; clock-names = "mclk"; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; }; &smd_rpm_regulators { diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 789f3e87321e..492a011f14f6 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -51,31 +51,31 @@ pinctrl-1 = <&blsp2_uart2_4pins_sleep>; }; - i2c@07577000 { + i2c@7577000 { /* On Low speed expansion */ label = "LS-I2C0"; status = "okay"; }; - i2c@075b6000 { + i2c@75b6000 { /* On Low speed expansion */ label = "LS-I2C1"; status = "okay"; }; - spi@07575000 { + spi@7575000 { /* On Low speed expansion */ label = "LS-SPI0"; status = "okay"; }; - i2c@075b5000 { + i2c@75b5000 { /* On High speed expansion */ label = "HS-I2C2"; status = "okay"; }; - spi@075ba000{ + spi@75ba000{ /* On High speed expansion */ label = "HS-SPI1"; status = "okay"; @@ -138,6 +138,22 @@ pinctrl-names = "default"; pinctrl-0 = <&usb2_vbus_det_gpio>; }; + + agnoc@0 { + qcom,pcie@00600000 { + perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>; + }; + + qcom,pcie@00608000 { + status = "okay"; + perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>; + }; + + qcom,pcie@00610000 { + status = "okay"; + perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>; + }; + }; }; @@ -173,9 +189,15 @@ regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1300000>; }; + + /** + * 1.8v required on LS expansion + * for mezzanine boards + */ s4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; }; s5 { regulator-min-microvolt = <2150000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index dc3817593e14..6b2127a6ced1 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -69,8 +69,11 @@ }; rmtfs@86700000 { + compatible = "qcom,rmtfs-mem"; reg = <0x0 0x86700000 0x0 0xe0000>; no-map; + + qcom,client-id = <1>; }; rfsa@867e00000 { @@ -257,6 +260,8 @@ clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; clock-names = "core", "bus", "iface"; #reset-cells = <1>; + + qcom,dload-mode = <&tcsr 0x6100>; }; }; @@ -495,7 +500,7 @@ status = "disabled"; }; - lpass: lpass@07708000 { + lpass: lpass@7708000 { status = "disabled"; compatible = "qcom,lpass-cpu-apq8016"; clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, @@ -530,7 +535,7 @@ #sound-dai-cells = <1>; }; - sdhc_1: sdhci@07824000 { + sdhc_1: sdhci@7824000 { compatible = "qcom,sdhci-msm-v4"; reg = <0x07824900 0x11c>, <0x07824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -547,7 +552,7 @@ status = "disabled"; }; - sdhc_2: sdhci@07864000 { + sdhc_2: sdhci@7864000 { compatible = "qcom,sdhci-msm-v4"; reg = <0x07864900 0x11c>, <0x07864000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -814,7 +819,7 @@ mdp: mdp@1a01000 { compatible = "qcom,mdp5"; - reg = <0x1a01000 0x90000>; + reg = <0x1a01000 0x89000>; reg-names = "mdp_phys"; interrupt-parent = <&mdss>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 659940434842..c5c42e94f387 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -300,4 +300,199 @@ drive-strength = <2>; /* 2 MA */ }; }; + + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio36"; + function = "pci_e0"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_clkreq_sleep: pcie0_clkreq_sleep { + mux { + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie0_wake_sleep: pcie0_wake_sleep { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie1_clkreq_default: pcie1_clkreq_default { + mux { + pins = "gpio131"; + function = "pci_e1"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_perst_default: pcie1_perst_default { + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio132"; + function = "gpio"; + }; + + config { + pins = "gpio132"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_clkreq_sleep: pcie1_clkreq_sleep { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie1_wake_sleep: pcie1_wake_sleep { + mux { + pins = "gpio132"; + function = "gpio"; + }; + + config { + pins = "gpio132"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie2_clkreq_default: pcie2_clkreq_default { + mux { + pins = "gpio115"; + function = "pci_e2"; + }; + + config { + pins = "gpio115"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2_perst_default: pcie2_perst_default { + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie2_wake_default: pcie2_wake_default { + mux { + pins = "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio116"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie2_clkreq_sleep: pcie2_clkreq_sleep { + mux { + pins = "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio115"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie2_wake_sleep: pcie2_wake_sleep { + mux { + pins = "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio116"; + drive-strength = <2>; + bias-disable; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 887b61c872dd..4b2afcc4fdf4 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8996.h> #include <dt-bindings/clock/qcom,mmcc-msm8996.h> +#include <dt-bindings/clock/qcom,rpmcc.h> / { model = "Qualcomm Technologies, Inc. MSM8996"; @@ -261,6 +262,8 @@ firmware { scm { compatible = "qcom,scm-msm8996"; + + qcom,dload-mode = <&tcsr 0x13000>; }; }; @@ -289,6 +292,11 @@ compatible = "qcom,rpm-msm8996"; qcom,glink-channels = "rpm_requests"; + rpmcc: qcom,rpmcc { + compatible = "qcom,rpmcc-msm8996"; + #clock-cells = <1>; + }; + pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; @@ -358,6 +366,11 @@ reg = <0x740000 0x20000>; }; + tcsr: syscon@7a0000 { + compatible = "qcom,tcsr-msm8996", "syscon"; + reg = <0x7a0000 0x18000>; + }; + intc: interrupt-controller@9bc0000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -395,7 +408,7 @@ #clock-cells = <1>; }; - blsp1_spi0: spi@07575000 { + blsp1_spi0: spi@7575000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x07575000 0x600>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; @@ -410,7 +423,7 @@ status = "disabled"; }; - blsp2_i2c0: i2c@075b5000 { + blsp2_i2c0: i2c@75b5000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x075b5000 0x1000>; interrupts = <GIC_SPI 101 0>; @@ -441,7 +454,7 @@ status = "disabled"; }; - blsp2_i2c1: i2c@075b6000 { + blsp2_i2c1: i2c@75b6000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x075b6000 0x1000>; interrupts = <GIC_SPI 102 0>; @@ -466,7 +479,7 @@ status = "disabled"; }; - blsp1_i2c2: i2c@07577000 { + blsp1_i2c2: i2c@7577000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07577000 0x1000>; interrupts = <GIC_SPI 97 0>; @@ -481,7 +494,7 @@ status = "disabled"; }; - blsp2_spi5: spi@075ba000{ + blsp2_spi5: spi@75ba000{ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x075ba000 0x600>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; @@ -522,7 +535,7 @@ #interrupt-cells = <2>; }; - timer@09840000 { + timer@9840000 { #address-cells = <1>; #size-cells = <1>; ranges; @@ -819,6 +832,172 @@ phy-names = "usb2-phy", "usb3-phy"; }; }; + + agnoc@0 { + power-domains = <&gcc AGGRE0_NOC_GDSC>; + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pcie0: qcom,pcie@00600000 { + compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; + status = "disabled"; + power-domains = <&gcc PCIE0_GDSC>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + reg = <0x00600000 0x2000>, + <0x0c000000 0xf1d>, + <0x0c000f20 0xa8>, + <0x0c100000 0x100000>; + reg-names = "parf", "dbi", "elbi","config"; + + phys = <&pciephy_0>; + phy-names = "pciephy"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, + <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; + + interrupts = <GIC_SPI 405 IRQ_TYPE_NONE>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; + pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; + + + vdda-supply = <&pm8994_l28>; + + linux,pci-domain = <0>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; + + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave"; + + }; + + pcie1: qcom,pcie@00608000 { + compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; + power-domains = <&gcc PCIE1_GDSC>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + status = "disabled"; + + reg = <0x00608000 0x2000>, + <0x0d000000 0xf1d>, + <0x0d000f20 0xa8>, + <0x0d100000 0x100000>; + + reg-names = "parf", "dbi", "elbi","config"; + + phys = <&pciephy_1>; + phy-names = "pciephy"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, + <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; + + interrupts = <GIC_SPI 413 IRQ_TYPE_NONE>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; + pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; + + + vdda-supply = <&pm8994_l28>; + linux,pci-domain = <1>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>; + + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave"; + }; + + pcie2: qcom,pcie@00610000 { + compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; + power-domains = <&gcc PCIE2_GDSC>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + status = "disabled"; + reg = <0x00610000 0x2000>, + <0x0e000000 0xf1d>, + <0x0e000f20 0xa8>, + <0x0e100000 0x100000>; + + reg-names = "parf", "dbi", "elbi","config"; + + phys = <&pciephy_2>; + phy-names = "pciephy"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, + <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; + + device_type = "pci"; + + interrupts = <GIC_SPI 421 IRQ_TYPE_NONE>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; + pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; + + vdda-supply = <&pm8994_l28>; + + linux,pci-domain = <2>; + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, + <&gcc GCC_PCIE_2_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_AXI_CLK>; + + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave"; + }; + }; }; adsp-pil { diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index 6e2ae59a3745..c108d73f8766 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -1 +1,3 @@ +dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb +dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb diff --git a/arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts b/arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts new file mode 100644 index 000000000000..bd584e99fff9 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "rtd1295.dtsi" + +/ { + compatible = "mele,v9", "realtek,rtd1295"; + model = "MeLE V9"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts b/arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts new file mode 100644 index 000000000000..8e2b0e75298a --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "rtd1295.dtsi" + +/ { + compatible = "probox2,ava", "realtek,rtd1295"; + model = "PROBOX2 AVA"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts b/arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts index 6efa8091bb30..da19faab29d5 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts +++ b/arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts @@ -6,12 +6,6 @@ /dts-v1/; -/memreserve/ 0x0000000000000000 0x0000000000030000; -/memreserve/ 0x000000000001f000 0x0000000000001000; -/memreserve/ 0x0000000000030000 0x00000000000d0000; -/memreserve/ 0x0000000001b00000 0x00000000004be000; -/memreserve/ 0x0000000001ffe000 0x0000000000004000; - #include "rtd1295.dtsi" / { diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi index d8f84666c8ce..8d9ac05d17dc 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi @@ -6,13 +6,10 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "rtd129x.dtsi" / { compatible = "realtek,rtd1295"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; cpus { #address-cells = <2>; @@ -62,12 +59,6 @@ }; }; - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 @@ -79,53 +70,8 @@ <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>; }; +}; - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - /* Exclude up to 2 GiB of RAM */ - ranges = <0x80000000 0x80000000 0x80000000>; - - uart0: serial@98007800 { - compatible = "snps,dw-apb-uart"; - reg = <0x98007800 0x400>, - <0x98007000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - status = "disabled"; - }; - - uart1: serial@9801b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x9801b200 0x100>, - <0x9801b00c 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - status = "disabled"; - }; - - uart2: serial@9801b400 { - compatible = "snps,dw-apb-uart"; - reg = <0x9801b400 0x100>, - <0x9801b00c 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - status = "disabled"; - }; - - gic: interrupt-controller@ff011000 { - compatible = "arm,gic-400"; - reg = <0xff011000 0x1000>, - <0xff012000 0x2000>, - <0xff014000 0x2000>, - <0xff016000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - interrupt-controller; - #interrupt-cells = <3>; - }; - }; +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi new file mode 100644 index 000000000000..b9cb92466fc7 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi @@ -0,0 +1,72 @@ +/* + * Realtek RTD1293/RTD1295/RTD1296 SoC + * + * Copyright (c) 2016-2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/memreserve/ 0x0000000000000000 0x0000000000030000; +/memreserve/ 0x000000000001f000 0x0000000000001000; +/memreserve/ 0x0000000000030000 0x00000000000d0000; +/memreserve/ 0x0000000001b00000 0x00000000004be000; +/memreserve/ 0x0000000001ffe000 0x0000000000004000; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + arm_pmu: arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + /* Exclude up to 2 GiB of RAM */ + ranges = <0x80000000 0x80000000 0x80000000>; + + uart0: serial@98007800 { + compatible = "snps,dw-apb-uart"; + reg = <0x98007800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + status = "disabled"; + }; + + uart1: serial@9801b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x9801b200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + status = "disabled"; + }; + + uart2: serial@9801b400 { + compatible = "snps,dw-apb-uart"; + reg = <0x9801b400 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + status = "disabled"; + }; + + gic: interrupt-controller@ff011000 { + compatible = "arm,gic-400"; + reg = <0xff011000 0x1000>, + <0xff012000 0x2000>, + <0xff014000 0x2000>, + <0xff016000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 6b282283f1bf..646198d82903 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -1,6 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb +dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb +dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb +dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb +dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts new file mode 100644 index 000000000000..009cb1cb0dde --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts @@ -0,0 +1,19 @@ +/* + * Device Tree Source for the H3ULCB Kingfisher board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include "r8a7795-es1-h3ulcb.dts" +#include "ulcb-kf.dtsi" + +/ { + model = "Renesas H3ULCB Kingfisher board based on r8a7795 ES1.x"; + compatible = "shimafuji,kingfisher", "renesas,h3ulcb", + "renesas,r8a7795"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index aaa5e67a963e..655dd30639c5 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi @@ -11,7 +11,7 @@ #include "r8a7795.dtsi" &soc { - xhci1: usb@ee0400000 { + xhci1: usb@ee040000 { compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; reg = <0 0xee040000 0 0xc00>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts new file mode 100644 index 000000000000..4403227c0f97 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts @@ -0,0 +1,19 @@ +/* + * Device Tree Source for the H3ULCB Kingfisher board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include "r8a7795-h3ulcb.dts" +#include "ulcb-kf.dtsi" + +/ { + model = "Renesas H3ULCB Kingfisher board based on r8a7795 ES2.0+"; + compatible = "shimafuji,kingfisher", "renesas,h3ulcb", + "renesas,r8a7795"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 2938195b9571..15ef292a8d9f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -220,7 +220,7 @@ gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -235,7 +235,7 @@ gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -250,7 +250,7 @@ gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -265,7 +265,7 @@ gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -280,7 +280,7 @@ gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -295,7 +295,7 @@ gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -310,7 +310,7 @@ gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -325,7 +325,7 @@ gpio7: gpio@e6055800 { compatible = "renesas,gpio-r8a7795", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -1471,6 +1471,17 @@ status = "disabled"; }; + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a7795-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + usb_dmac0: dma-controller@e65a0000 { compatible = "renesas,r8a7795-usb-dmac", "renesas,usb-dmac"; @@ -2014,7 +2025,7 @@ renesas,fcp = <&fcpf1>; }; - hdmi0: hdmi0@fead0000 { + hdmi0: hdmi@fead0000 { compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; reg = <0 0xfead0000 0 0x10000>; interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; @@ -2039,7 +2050,7 @@ }; }; - hdmi1: hdmi1@feae0000 { + hdmi1: hdmi@feae0000 { compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; reg = <0 0xfeae0000 0 0x10000>; interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts new file mode 100644 index 000000000000..de2390f009e7 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts @@ -0,0 +1,19 @@ +/* + * Device Tree Source for the M3ULCB Kingfisher board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include "r8a7796-m3ulcb.dts" +#include "ulcb-kf.dtsi" + +/ { + model = "Renesas M3ULCB Kingfisher board based on r8a7796"; + compatible = "shimafuji,kingfisher", "renesas,m3ulcb", + "renesas,r8a7796"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 369092e17e34..f2b2e40c655e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -214,7 +214,7 @@ gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -229,7 +229,7 @@ gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -244,7 +244,7 @@ gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -259,7 +259,7 @@ gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -274,7 +274,7 @@ gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -289,7 +289,7 @@ gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -304,7 +304,7 @@ gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -319,7 +319,7 @@ gpio7: gpio@e6055800 { compatible = "renesas,gpio-r8a7796", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -383,6 +383,22 @@ #power-domain-cells = <1>; }; + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a7796", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + i2c_dvfs: i2c@e60b0000 { #address-cells = <1>; #size-cells = <0>; @@ -1279,6 +1295,17 @@ status = "disabled"; }; + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a7796-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + ohci0: usb@ee080000 { compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; @@ -1659,6 +1686,16 @@ /* placeholder */ }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + fcpf0: fcp@fe950000 { compatible = "renesas,fcpf"; reg = <0 0xfe950000 0 0x200>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts new file mode 100644 index 000000000000..a711e77cc6a5 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -0,0 +1,57 @@ +/* + * Device Tree Source for the Eagle board + * + * Copyright (C) 2016-2017 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a77970.dtsi" + +/ { + model = "Renesas Eagle board based on r8a77970"; + compatible = "renesas,eagle", "renesas,r8a77970"; + + aliases { + serial0 = &scif0; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&scif0 { + status = "okay"; +}; + +&avb { + renesas,no-ether-link; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi new file mode 100644 index 000000000000..97e6981938e7 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -0,0 +1,382 @@ +/* + * Device Tree Source for the r8a77970 SoC + * + * Copyright (C) 2016-2017 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/ { + compatible = "renesas,r8a77970"; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0>; + clocks = <&cpg CPG_CORE 0>; + power-domains = <&sysc 5>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA53: cache-controller { + compatible = "cache"; + power-domains = <&sysc 21>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1010000 0 0x1000>, + <0 0xf1020000 0 0x20000>, + <0 0xf1040000 0 0x20000>, + <0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc 32>; + resets = <&cpg 408>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77970-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77970-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77970-sysc"; + reg = <0 0xe6180000 0 0x440>; + #power-domain-cells = <1>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc 32>; + resets = <&cpg 407>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a77970", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <8>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a77970", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <8>; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a77970", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 96>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a77970", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 96>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a77970", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 96>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a77970", + "renesas,rcar-gen3-hscif", "renesas,hscif"; + reg = <0 0xe66a0000 0 96>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x37>, <&dmac1 0x36>, + <&dmac2 0x37>, <&dmac2 0x36>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 517>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77970", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77970", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a77970", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x57>, <&dmac1 0x56>, + <&dmac2 0x57>, <&dmac2 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a77970", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE 9>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x59>, <&dmac1 0x58>, + <&dmac2 0x59>, <&dmac2 0x58>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 203>; + status = "disabled"; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77970", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc 32>; + resets = <&cpg 812>; + phy-mode = "rgmii-id"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index d144370051d5..09de73b11db8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "r8a77995.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Renesas Draak board based on r8a77995"; @@ -18,6 +19,7 @@ aliases { serial0 = &scif2; + ethernet0 = &avb; }; chosen { @@ -36,7 +38,83 @@ clock-frequency = <48000000>; }; +&pfc { + avb0_pins: avb { + mux { + groups = "avb0_link", "avb0_mdc", "avb0_mii"; + function = "avb0"; + }; + }; + + pwm0_pins: pwm0 { + groups = "pwm0_c"; + function = "pwm0"; + }; + + pwm1_pins: pwm1 { + groups = "pwm1_c"; + function = "pwm1"; + }; + + scif2_pins: scif2 { + groups = "scif2_data"; + function = "scif2"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&avb { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + }; +}; + &scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index d0f95b78c022..788e3afae6e3 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -9,8 +9,9 @@ * kind, whether express or implied. */ -#include <dt-bindings/clock/renesas-cpg-mssr.h> +#include <dt-bindings/clock/r8a77995-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/r8a77995-sysc.h> / { compatible = "renesas,r8a77995"; @@ -30,14 +31,14 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0>; device_type = "cpu"; - power-domains = <&sysc 5>; + power-domains = <&sysc R8A77995_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; }; L2_CA53: cache-controller-1 { compatible = "cache"; - power-domains = <&sysc 21>; + power-domains = <&sysc R8A77995_PD_CA53_SCU>; cache-unified; cache-level = <2>; }; @@ -76,7 +77,7 @@ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 408>; }; @@ -97,7 +98,7 @@ "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 402>; status = "disabled"; }; @@ -122,7 +123,7 @@ reg = <0 0xe6160000 0 0x0200>; }; - pfc: pfc@e6060000 { + pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a77995"; reg = <0 0xe6060000 0 0x508>; }; @@ -138,18 +139,268 @@ #power-domain-cells = <1>; }; + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 9>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 10>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 21>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 14>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 906>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77995", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii-txid"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif2: serial@e6e88000 { compatible = "renesas,scif-r8a77995", "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6e88000 0 64>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE 16>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 310>; status = "disabled"; }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a77995", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index d9d885006a8e..a298df74ca6c 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -52,7 +52,7 @@ */ compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <11289600>; + clock-frequency = <12288000>; }; backlight: backlight { @@ -282,6 +282,7 @@ }; &ehci0 { + dr_mode = "otg"; status = "okay"; }; @@ -294,6 +295,7 @@ }; &hsusb { + dr_mode = "otg"; status = "okay"; }; @@ -356,6 +358,7 @@ }; &ohci0 { + dr_mode = "otg"; status = "okay"; }; @@ -381,8 +384,7 @@ avb_pins: avb { mux { - groups = "avb_link", "avb_phy_int", "avb_mdc", - "avb_mii"; + groups = "avb_link", "avb_mdc", "avb_mii"; function = "avb"; }; @@ -496,6 +498,11 @@ bias-pull-down; }; }; + + usb30_pins: usb30 { + groups = "usb30"; + function = "usb30"; + }; }; &pwm1 { @@ -631,5 +638,8 @@ }; &xhci0 { + pinctrl-0 = <&usb30_pins>; + pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi new file mode 100644 index 000000000000..657ad1041965 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -0,0 +1,169 @@ +/* + * Device Tree Source for the Kingfisher (ULCB extension) board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/ { + aliases { + serial1 = &hscif0; + serial2 = &scif1; + }; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + status = "okay"; +}; + +&hsusb { + status = "okay"; +}; + +&i2c2 { + gpio_exp_74: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio6>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + hub_pwen { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "HUB pwen"; + }; + + hub_rst { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "HUB rst"; + }; + }; + + gpio_exp_75: gpio@75 { + compatible = "ti,tca9539"; + reg = <0x75>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio6>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + }; + + i2cswitch2: i2c-switch@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c4 { + gpio_exp_76: gpio@76 { + compatible = "ti,tca9539"; + reg = <0x76>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio7>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + }; + + gpio_exp_77: gpio@77 { + compatible = "ti,tca9539"; + reg = <0x77>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + }; + + i2cswitch4: i2c-switch@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec0 { + status = "okay"; +}; + +&pciec1 { + status = "okay"; +}; + +&pfc { + can0_pins: can0 { + groups = "can0_data_a"; + function = "can0"; + }; + + can1_pins: can1 { + groups = "can1_data"; + function = "can1"; + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + scif1_pins: scif1 { + groups = "scif1_data_b", "scif1_ctrl"; + function = "scif1"; + }; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + status = "okay"; +}; + +&xhci0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 1b868df2393f..0d85b315ce71 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -31,7 +31,7 @@ */ compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <11289600>; + clock-frequency = <12288000>; }; hdmi0-out { @@ -157,6 +157,10 @@ }; }; +&du { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -250,8 +254,7 @@ avb_pins: avb { mux { - groups = "avb_link", "avb_phy_int", "avb_mdc", - "avb_mii"; + groups = "avb_link", "avb_mdc", "avb_mii"; function = "avb"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts index 8e6a65431756..3d551e3e6c23 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts @@ -60,6 +60,31 @@ regulator-max-microvolt = <12000000>; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + vcc_sys: vcc-sys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -78,6 +103,19 @@ }; }; +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + &gmac2phy { phy-supply = <&vcc_phy>; clock_in_out = "output"; @@ -85,7 +123,7 @@ assigned-clock-rate = <50000000>; assigned-clocks = <&cru SCLK_MAC2PHY>; assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; - status = "okay"; + }; &i2c1 { @@ -203,6 +241,38 @@ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <1 18 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; }; &tsadc { diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 1070c8264c13..aa4d07046a7b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -786,6 +786,22 @@ status = "disabled"; }; + efuse256: efuse@ffb00000 { + compatible = "rockchip,rk3368-efuse"; + reg = <0x0 0xffb00000 0x0 0x20>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE256>; + clock-names = "pclk_efuse"; + + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + temp_adjust: temp-adjust@1f { + reg = <0x1f 0x1>; + }; + }; + gic: interrupt-controller@ffb71000 { compatible = "arm,gic-400"; interrupt-controller; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index fef82274a39d..4f28628aa091 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -49,6 +49,10 @@ model = "Firefly-RK3399 Board"; compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; + chosen { + stdout-path = "serial2:1500000n8"; + }; + backlight: backlight { compatible = "pwm-backlight"; enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; @@ -255,6 +259,13 @@ status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; @@ -728,3 +739,19 @@ status = "okay"; dr_mode = "host"; }; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts index a3d3cea7dc4f..0384e3121f18 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts @@ -249,6 +249,10 @@ ap_i2c_dig: &i2c2 { pinctrl-0 = <&trackpad_int_l>; interrupt-parent = <&gpio1>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + linux,gpio-keymap = <KEY_RESERVED + KEY_RESERVED + KEY_RESERVED + BTN_LEFT>; wakeup-source; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 199a5118b20d..5772c52fbfd3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -514,7 +514,8 @@ sound { compatible = "rockchip,rk3399-gru-sound"; rockchip,cpu = <&i2s0 &i2s2>; - rockchip,codec = <&max98357a &headsetcodec &codec>; + rockchip,codec = <&max98357a &headsetcodec + &codec &wacky_spi_audio>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index ab7629c5b856..d340b58ab184 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1204,6 +1204,17 @@ status = "disabled"; }; + rga: rga@ff680000 { + compatible = "rockchip,rk3399-rga"; + reg = <0x0 0xff680000 0x0 0x10000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3399_PD_RGA>; + }; + efuse0: efuse@ff690000 { compatible = "rockchip,rk3399-efuse"; reg = <0x0 0xff690000 0x0 0x80>; @@ -1601,8 +1612,12 @@ compatible = "rockchip,rk3399-dw-hdmi"; reg = <0x0 0xff940000 0x0 0x20000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; - clock-names = "iahb", "isfr", "vpll", "grf"; + clocks = <&cru PCLK_HDMI_CTRL>, + <&cru SCLK_HDMI_SFR>, + <&cru PLL_VPLL>, + <&cru PCLK_VIO_GRF>, + <&cru SCLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "vpll", "grf", "cec"; power-domains = <&power RK3399_PD_HDCP>; reg-io-width = <4>; rockchip,grf = <&grf>; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts index ffb473ad2e0f..dd7193acc7df 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts @@ -40,13 +40,22 @@ }; ðsc { - interrupts = <0 48 4>; + interrupt-parent = <&gpio>; + interrupts = <0 8>; }; &serial0 { status = "okay"; }; +&gpio { + xirq0 { + gpio-hog; + gpios = <120 0>; + input; + }; +}; + &i2c0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 09c429cb6d61..1c63d0ab8a58 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -7,6 +7,8 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#include <dt-bindings/gpio/gpio.h> + /memreserve/ 0x80000000 0x02000000; / { @@ -49,7 +51,7 @@ }; }; - cluster0_opp: opp_table { + cluster0_opp: opp-table { compatible = "operating-points-v2"; opp-shared; @@ -96,6 +98,11 @@ }; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, @@ -118,6 +125,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; }; serial1: serial@54006900 { @@ -128,6 +136,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; }; serial2: serial@54006a00 { @@ -138,6 +147,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; }; serial3: serial@54006b00 { @@ -148,6 +158,32 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 43 0 0>, + <&pinctrl 51 0 0>, + <&pinctrl 96 0 0>, + <&pinctrl 160 0 0>, + <&pinctrl 184 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1", + "gpio_range2", + "gpio_range3", + "gpio_range4", + "gpio_range5"; + ngpios = <200>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>, + <21 217 3>; }; adamv@57920000 { @@ -171,6 +207,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; clock-frequency = <100000>; }; @@ -184,6 +221,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; clock-frequency = <100000>; }; @@ -194,6 +232,7 @@ #size-cells = <0>; interrupts = <0 43 4>; clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; clock-frequency = <400000>; }; @@ -207,6 +246,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; clock-frequency = <100000>; }; @@ -220,6 +260,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; clocks = <&peri_clk 8>; + resets = <&peri_rst 8>; clock-frequency = <100000>; }; @@ -230,6 +271,7 @@ #size-cells = <0>; interrupts = <0 25 4>; clocks = <&peri_clk 9>; + resets = <&peri_rst 9>; clock-frequency = <400000>; }; @@ -282,9 +324,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&sys_clk 4>; + resets = <&sys_rst 4>; bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + mmc-pwrseq = <&emmc_pwrseq>; cdns,phy-input-delay-legacy = <4>; cdns,phy-input-delay-mmc-highspeed = <2>; cdns,phy-input-delay-mmc-ddr = <3>; @@ -358,6 +402,24 @@ }; }; + soc-glue@5f900000 { + compatible = "socionext,uniphier-ld11-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x68>; + }; + }; + aidet: aidet@5fc20000 { compatible = "socionext,uniphier-ld11-aidet"; reg = <0x5fc20000 0x200>; @@ -403,6 +465,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clocks = <&sys_clk 2>; + resets = <&sys_rst 2>; }; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts index 1ca0c8620dc5..d99e3731358c 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts @@ -40,13 +40,22 @@ }; ðsc { - interrupts = <0 48 4>; + interrupt-parent = <&gpio>; + interrupts = <0 8>; }; &serial0 { status = "okay"; }; +&gpio { + xirq0 { + gpio-hog; + gpios = <120 0>; + input; + }; +}; + &i2c0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index a29c279b6e8e..5c81070944cc 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -7,6 +7,9 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> + /memreserve/ 0x80000000 0x02000000; / { @@ -46,6 +49,7 @@ clocks = <&sys_clk 32>; enable-method = "psci"; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -64,6 +68,7 @@ clocks = <&sys_clk 33>; enable-method = "psci"; operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; }; cpu3: cpu@101 { @@ -76,7 +81,7 @@ }; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table0 { compatible = "operating-points-v2"; opp-shared; @@ -114,7 +119,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table1 { compatible = "operating-points-v2"; opp-shared; @@ -165,6 +170,11 @@ }; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, @@ -173,6 +183,40 @@ <1 10 4>; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + thermal-sensors = <&pvtctl>; + + trips { + cpu_crit: cpu-crit { + temperature = <110000>; /* 110C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu-alert { + temperature = <100000>; /* 100C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&cpu0 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert>; + cooling-device = <&cpu2 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -187,6 +231,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; }; serial1: serial@54006900 { @@ -197,6 +242,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; }; serial2: serial@54006a00 { @@ -207,6 +253,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; }; serial3: serial@54006b00 { @@ -217,6 +264,26 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 96 0 0>, + <&pinctrl 160 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1", + "gpio_range2"; + ngpios = <205>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>, + <21 217 3>; }; adamv@57920000 { @@ -240,6 +307,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; clock-frequency = <100000>; }; @@ -253,6 +321,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; clock-frequency = <100000>; }; @@ -263,6 +332,7 @@ #size-cells = <0>; interrupts = <0 43 4>; clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; clock-frequency = <400000>; }; @@ -276,6 +346,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; clock-frequency = <100000>; }; @@ -289,6 +360,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; clocks = <&peri_clk 8>; + resets = <&peri_rst 8>; clock-frequency = <100000>; }; @@ -299,6 +371,7 @@ #size-cells = <0>; interrupts = <0 25 4>; clocks = <&peri_clk 9>; + resets = <&peri_rst 9>; clock-frequency = <400000>; }; @@ -356,9 +429,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&sys_clk 4>; + resets = <&sys_rst 4>; bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + mmc-pwrseq = <&emmc_pwrseq>; cdns,phy-input-delay-legacy = <4>; cdns,phy-input-delay-mmc-highspeed = <2>; cdns,phy-input-delay-mmc-ddr = <3>; @@ -376,6 +451,24 @@ }; }; + soc-glue@5f900000 { + compatible = "socionext,uniphier-ld20-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x68>; + }; + }; + aidet: aidet@5fc20000 { compatible = "socionext,uniphier-ld20-aidet"; reg = <0x5fc20000 0x200>; @@ -410,6 +503,13 @@ watchdog { compatible = "socionext,uniphier-wdt"; }; + + pvtctl: pvtctl { + compatible = "socionext,uniphier-ld20-thermal"; + interrupts = <0 3 4>; + #thermal-sensor-cells = <0>; + socionext,tmod-calibration = <0x0f22 0x68ee>; + }; }; nand: nand@68000000 { @@ -421,6 +521,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clocks = <&sys_clk 2>; + resets = <&sys_rst 2>; }; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts index d65f746a3f9d..864feeb35180 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts @@ -38,7 +38,8 @@ }; ðsc { - interrupts = <0 52 4>; + interrupt-parent = <&gpio>; + interrupts = <0 8>; }; &serial0 { @@ -60,3 +61,7 @@ &i2c3 { status = "okay"; }; + +&nand { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 384729fa740f..48e733136db4 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -7,6 +7,8 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#include <dt-bindings/gpio/gpio.h> + /memreserve/ 0x80000000 0x02000000; / { @@ -73,7 +75,7 @@ }; }; - cluster0_opp: opp_table { + cluster0_opp: opp-table { compatible = "operating-points-v2"; opp-shared; @@ -124,6 +126,11 @@ }; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio 47 GPIO_ACTIVE_LOW>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, @@ -146,6 +153,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; + resets = <&peri_rst 0>; }; serial1: serial@54006900 { @@ -156,6 +164,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; + resets = <&peri_rst 1>; }; serial2: serial@54006a00 { @@ -166,6 +175,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; + resets = <&peri_rst 2>; }; serial3: serial@54006b00 { @@ -176,6 +186,26 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; + resets = <&peri_rst 3>; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 96 0 0>, + <&pinctrl 160 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1", + "gpio_range2"; + ngpios = <286>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>, + <21 217 3>; }; i2c0: i2c@58780000 { @@ -188,6 +218,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; + resets = <&peri_rst 4>; clock-frequency = <100000>; }; @@ -201,6 +232,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; + resets = <&peri_rst 5>; clock-frequency = <100000>; }; @@ -214,6 +246,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; + resets = <&peri_rst 6>; clock-frequency = <100000>; }; @@ -227,6 +260,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; + resets = <&peri_rst 7>; clock-frequency = <100000>; }; @@ -238,6 +272,7 @@ #size-cells = <0>; interrupts = <0 26 4>; clocks = <&peri_clk 10>; + resets = <&peri_rst 10>; clock-frequency = <400000>; }; @@ -295,9 +330,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&sys_clk 4>; + resets = <&sys_rst 4>; bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + mmc-pwrseq = <&emmc_pwrseq>; cdns,phy-input-delay-legacy = <4>; cdns,phy-input-delay-mmc-highspeed = <2>; cdns,phy-input-delay-mmc-ddr = <3>; @@ -315,6 +352,24 @@ }; }; + soc-glue@5f900000 { + compatible = "socionext,uniphier-pxs3-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x68>; + }; + }; + aidet: aidet@5fc20000 { compatible = "socionext,uniphier-pxs3-aidet"; reg = <0x5fc20000 0x200>; @@ -360,6 +415,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clocks = <&sys_clk 2>; + resets = <&sys_rst 2>; }; }; }; diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h index 7dd8bc0c3cd0..0dcb3e87d44c 100644 --- a/include/dt-bindings/clock/r7s72100-clock.h +++ b/include/dt-bindings/clock/r7s72100-clock.h @@ -11,6 +11,8 @@ #define __DT_BINDINGS_CLOCK_R7S72100_H__ #define R7S72100_CLK_PLL 0 +#define R7S72100_CLK_I 1 +#define R7S72100_CLK_G 2 /* MSTP2 */ #define R7S72100_CLK_CORESIGHT 0 diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index eff4319d008b..b9462b7d3dfe 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -68,12 +68,14 @@ #define ACLK_LCDC1 196 #define ACLK_GPU 197 #define ACLK_SMC 198 -#define ACLK_CIF 199 +#define ACLK_CIF1 199 #define ACLK_IPP 200 #define ACLK_RGA 201 #define ACLK_CIF0 202 #define ACLK_CPU 203 #define ACLK_PERI 204 +#define ACLK_VEPU 205 +#define ACLK_VDPU 206 /* pclk gates */ #define PCLK_GRF 320 @@ -134,8 +136,11 @@ #define HCLK_NANDC0 467 #define HCLK_CPU 468 #define HCLK_PERI 469 +#define HCLK_CIF1 470 +#define HCLK_VEPU 471 +#define HCLK_VDPU 472 -#define CLK_NR_CLKS (HCLK_PERI + 1) +#define CLK_NR_CLKS (HCLK_VDPU + 1) /* soft-reset indices */ #define SRST_MCORE 2 diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h index aeb83e581a11..a0063ed7284a 100644 --- a/include/dt-bindings/clock/rk3368-cru.h +++ b/include/dt-bindings/clock/rk3368-cru.h @@ -156,6 +156,7 @@ #define PCLK_ISP 366 #define PCLK_VIP 367 #define PCLK_WDT 368 +#define PCLK_EFUSE256 369 /* hclk gates */ #define HCLK_SFC 448 diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index a9dc1457cb00..6422314e46eb 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -310,6 +310,7 @@ #define TEGRA210_CLK_BLINK 280 /* 281 */ #define TEGRA210_CLK_SOR1_SRC 282 +#define TEGRA210_CLK_SOR1_OUT 282 /* 283 */ #define TEGRA210_CLK_XUSB_HOST_SRC 284 #define TEGRA210_CLK_XUSB_FALCON_SRC 285 diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h index 46789157660b..a69e310789c5 100644 --- a/include/dt-bindings/pinctrl/am43xx.h +++ b/include/dt-bindings/pinctrl/am43xx.h @@ -22,9 +22,21 @@ #define INPUT_EN (1 << 18) #define SLEWCTRL_SLOW (1 << 19) #define SLEWCTRL_FAST 0 +#define DS0_FORCE_OFF_MODE (1 << 24) +#define DS0_INPUT (1 << 25) +#define DS0_FORCE_OUT_HIGH (1 << 26) #define DS0_PULL_UP_DOWN_EN (1 << 27) +#define DS0_PULL_UP_SEL (1 << 28) #define WAKEUP_ENABLE (1 << 29) +#define DS0_PIN_OUTPUT (DS0_FORCE_OFF_MODE) +#define DS0_PIN_OUTPUT_HIGH (DS0_FORCE_OFF_MODE | DS0_FORCE_OUT_HIGH) +#define DS0_PIN_OUTPUT_PULLUP (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | DS0_PULL_UP_SEL) +#define DS0_PIN_OUTPUT_PULLDOWN (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN) +#define DS0_PIN_INPUT (DS0_FORCE_OFF_MODE | DS0_INPUT) +#define DS0_PIN_INPUT_PULLUP (DS0_FORCE_OFF_MODE | DS0_INPUT | DS0_PULL_UP_DOWN_EN | DS0_PULL_UP_SEL) +#define DS0_PIN_INPUT_PULLDOWN (DS0_FORCE_OFF_MODE | DS0_INPUT | DS0_PULL_UP_DOWN_EN) + #define PIN_OUTPUT (PULL_DISABLE) #define PIN_OUTPUT_PULLUP (PULL_UP) #define PIN_OUTPUT_PULLDOWN 0 diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h new file mode 100644 index 000000000000..b8dfe31821e6 --- /dev/null +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -0,0 +1,30 @@ +#ifndef _DT_BINDINGS_STM32_PINFUNC_H +#define _DT_BINDINGS_STM32_PINFUNC_H + +/* define PIN modes */ +#define GPIO 0x0 +#define AF0 0x1 +#define AF1 0x2 +#define AF2 0x3 +#define AF3 0x4 +#define AF4 0x5 +#define AF5 0x6 +#define AF6 0x7 +#define AF7 0x8 +#define AF8 0x9 +#define AF9 0xa +#define AF10 0xb +#define AF11 0xc +#define AF12 0xd +#define AF13 0xe +#define AF14 0xf +#define AF15 0x10 +#define ANALOG 0x11 + +/* define Pins number*/ +#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) + +#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) + +#endif /* _DT_BINDINGS_STM32_PINFUNC_H */ + diff --git a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h deleted file mode 100644 index 9a5a028f0d00..000000000000 --- a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h +++ /dev/null @@ -1,1240 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H -#define _DT_BINDINGS_STM32F429_PINFUNC_H - -#define STM32F429_PA0_FUNC_GPIO 0x0 -#define STM32F429_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 -#define STM32F429_PA0_FUNC_TIM5_CH1 0x3 -#define STM32F429_PA0_FUNC_TIM8_ETR 0x4 -#define STM32F429_PA0_FUNC_USART2_CTS 0x8 -#define STM32F429_PA0_FUNC_UART4_TX 0x9 -#define STM32F429_PA0_FUNC_ETH_MII_CRS 0xc -#define STM32F429_PA0_FUNC_EVENTOUT 0x10 -#define STM32F429_PA0_FUNC_ANALOG 0x11 - -#define STM32F429_PA1_FUNC_GPIO 0x100 -#define STM32F429_PA1_FUNC_TIM2_CH2 0x102 -#define STM32F429_PA1_FUNC_TIM5_CH2 0x103 -#define STM32F429_PA1_FUNC_USART2_RTS 0x108 -#define STM32F429_PA1_FUNC_UART4_RX 0x109 -#define STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c -#define STM32F429_PA1_FUNC_EVENTOUT 0x110 -#define STM32F429_PA1_FUNC_ANALOG 0x111 - -#define STM32F429_PA2_FUNC_GPIO 0x200 -#define STM32F429_PA2_FUNC_TIM2_CH3 0x202 -#define STM32F429_PA2_FUNC_TIM5_CH3 0x203 -#define STM32F429_PA2_FUNC_TIM9_CH1 0x204 -#define STM32F429_PA2_FUNC_USART2_TX 0x208 -#define STM32F429_PA2_FUNC_ETH_MDIO 0x20c -#define STM32F429_PA2_FUNC_EVENTOUT 0x210 -#define STM32F429_PA2_FUNC_ANALOG 0x211 - -#define STM32F429_PA3_FUNC_GPIO 0x300 -#define STM32F429_PA3_FUNC_TIM2_CH4 0x302 -#define STM32F429_PA3_FUNC_TIM5_CH4 0x303 -#define STM32F429_PA3_FUNC_TIM9_CH2 0x304 -#define STM32F429_PA3_FUNC_USART2_RX 0x308 -#define STM32F429_PA3_FUNC_OTG_HS_ULPI_D0 0x30b -#define STM32F429_PA3_FUNC_ETH_MII_COL 0x30c -#define STM32F429_PA3_FUNC_LCD_B5 0x30f -#define STM32F429_PA3_FUNC_EVENTOUT 0x310 -#define STM32F429_PA3_FUNC_ANALOG 0x311 - -#define STM32F429_PA4_FUNC_GPIO 0x400 -#define STM32F429_PA4_FUNC_SPI1_NSS 0x406 -#define STM32F429_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 -#define STM32F429_PA4_FUNC_USART2_CK 0x408 -#define STM32F429_PA4_FUNC_OTG_HS_SOF 0x40d -#define STM32F429_PA4_FUNC_DCMI_HSYNC 0x40e -#define STM32F429_PA4_FUNC_LCD_VSYNC 0x40f -#define STM32F429_PA4_FUNC_EVENTOUT 0x410 -#define STM32F429_PA4_FUNC_ANALOG 0x411 - -#define STM32F429_PA5_FUNC_GPIO 0x500 -#define STM32F429_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 -#define STM32F429_PA5_FUNC_TIM8_CH1N 0x504 -#define STM32F429_PA5_FUNC_SPI1_SCK 0x506 -#define STM32F429_PA5_FUNC_OTG_HS_ULPI_CK 0x50b -#define STM32F429_PA5_FUNC_EVENTOUT 0x510 -#define STM32F429_PA5_FUNC_ANALOG 0x511 - -#define STM32F429_PA6_FUNC_GPIO 0x600 -#define STM32F429_PA6_FUNC_TIM1_BKIN 0x602 -#define STM32F429_PA6_FUNC_TIM3_CH1 0x603 -#define STM32F429_PA6_FUNC_TIM8_BKIN 0x604 -#define STM32F429_PA6_FUNC_SPI1_MISO 0x606 -#define STM32F429_PA6_FUNC_TIM13_CH1 0x60a -#define STM32F429_PA6_FUNC_DCMI_PIXCLK 0x60e -#define STM32F429_PA6_FUNC_LCD_G2 0x60f -#define STM32F429_PA6_FUNC_EVENTOUT 0x610 -#define STM32F429_PA6_FUNC_ANALOG 0x611 - -#define STM32F429_PA7_FUNC_GPIO 0x700 -#define STM32F429_PA7_FUNC_TIM1_CH1N 0x702 -#define STM32F429_PA7_FUNC_TIM3_CH2 0x703 -#define STM32F429_PA7_FUNC_TIM8_CH1N 0x704 -#define STM32F429_PA7_FUNC_SPI1_MOSI 0x706 -#define STM32F429_PA7_FUNC_TIM14_CH1 0x70a -#define STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c -#define STM32F429_PA7_FUNC_EVENTOUT 0x710 -#define STM32F429_PA7_FUNC_ANALOG 0x711 - -#define STM32F429_PA8_FUNC_GPIO 0x800 -#define STM32F429_PA8_FUNC_MCO1 0x801 -#define STM32F429_PA8_FUNC_TIM1_CH1 0x802 -#define STM32F429_PA8_FUNC_I2C3_SCL 0x805 -#define STM32F429_PA8_FUNC_USART1_CK 0x808 -#define STM32F429_PA8_FUNC_OTG_FS_SOF 0x80b -#define STM32F429_PA8_FUNC_LCD_R6 0x80f -#define STM32F429_PA8_FUNC_EVENTOUT 0x810 -#define STM32F429_PA8_FUNC_ANALOG 0x811 - -#define STM32F429_PA9_FUNC_GPIO 0x900 -#define STM32F429_PA9_FUNC_TIM1_CH2 0x902 -#define STM32F429_PA9_FUNC_I2C3_SMBA 0x905 -#define STM32F429_PA9_FUNC_USART1_TX 0x908 -#define STM32F429_PA9_FUNC_DCMI_D0 0x90e -#define STM32F429_PA9_FUNC_EVENTOUT 0x910 -#define STM32F429_PA9_FUNC_ANALOG 0x911 - -#define STM32F429_PA10_FUNC_GPIO 0xa00 -#define STM32F429_PA10_FUNC_TIM1_CH3 0xa02 -#define STM32F429_PA10_FUNC_USART1_RX 0xa08 -#define STM32F429_PA10_FUNC_OTG_FS_ID 0xa0b -#define STM32F429_PA10_FUNC_DCMI_D1 0xa0e -#define STM32F429_PA10_FUNC_EVENTOUT 0xa10 -#define STM32F429_PA10_FUNC_ANALOG 0xa11 - -#define STM32F429_PA11_FUNC_GPIO 0xb00 -#define STM32F429_PA11_FUNC_TIM1_CH4 0xb02 -#define STM32F429_PA11_FUNC_USART1_CTS 0xb08 -#define STM32F429_PA11_FUNC_CAN1_RX 0xb0a -#define STM32F429_PA11_FUNC_OTG_FS_DM 0xb0b -#define STM32F429_PA11_FUNC_LCD_R4 0xb0f -#define STM32F429_PA11_FUNC_EVENTOUT 0xb10 -#define STM32F429_PA11_FUNC_ANALOG 0xb11 - -#define STM32F429_PA12_FUNC_GPIO 0xc00 -#define STM32F429_PA12_FUNC_TIM1_ETR 0xc02 -#define STM32F429_PA12_FUNC_USART1_RTS 0xc08 -#define STM32F429_PA12_FUNC_CAN1_TX 0xc0a -#define STM32F429_PA12_FUNC_OTG_FS_DP 0xc0b -#define STM32F429_PA12_FUNC_LCD_R5 0xc0f -#define STM32F429_PA12_FUNC_EVENTOUT 0xc10 -#define STM32F429_PA12_FUNC_ANALOG 0xc11 - -#define STM32F429_PA13_FUNC_GPIO 0xd00 -#define STM32F429_PA13_FUNC_JTMS_SWDIO 0xd01 -#define STM32F429_PA13_FUNC_EVENTOUT 0xd10 -#define STM32F429_PA13_FUNC_ANALOG 0xd11 - -#define STM32F429_PA14_FUNC_GPIO 0xe00 -#define STM32F429_PA14_FUNC_JTCK_SWCLK 0xe01 -#define STM32F429_PA14_FUNC_EVENTOUT 0xe10 -#define STM32F429_PA14_FUNC_ANALOG 0xe11 - -#define STM32F429_PA15_FUNC_GPIO 0xf00 -#define STM32F429_PA15_FUNC_JTDI 0xf01 -#define STM32F429_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 -#define STM32F429_PA15_FUNC_SPI1_NSS 0xf06 -#define STM32F429_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 -#define STM32F429_PA15_FUNC_EVENTOUT 0xf10 -#define STM32F429_PA15_FUNC_ANALOG 0xf11 - - - -#define STM32F429_PB0_FUNC_GPIO 0x1000 -#define STM32F429_PB0_FUNC_TIM1_CH2N 0x1002 -#define STM32F429_PB0_FUNC_TIM3_CH3 0x1003 -#define STM32F429_PB0_FUNC_TIM8_CH2N 0x1004 -#define STM32F429_PB0_FUNC_LCD_R3 0x100a -#define STM32F429_PB0_FUNC_OTG_HS_ULPI_D1 0x100b -#define STM32F429_PB0_FUNC_ETH_MII_RXD2 0x100c -#define STM32F429_PB0_FUNC_EVENTOUT 0x1010 -#define STM32F429_PB0_FUNC_ANALOG 0x1011 - -#define STM32F429_PB1_FUNC_GPIO 0x1100 -#define STM32F429_PB1_FUNC_TIM1_CH3N 0x1102 -#define STM32F429_PB1_FUNC_TIM3_CH4 0x1103 -#define STM32F429_PB1_FUNC_TIM8_CH3N 0x1104 -#define STM32F429_PB1_FUNC_LCD_R6 0x110a -#define STM32F429_PB1_FUNC_OTG_HS_ULPI_D2 0x110b -#define STM32F429_PB1_FUNC_ETH_MII_RXD3 0x110c -#define STM32F429_PB1_FUNC_EVENTOUT 0x1110 -#define STM32F429_PB1_FUNC_ANALOG 0x1111 - -#define STM32F429_PB2_FUNC_GPIO 0x1200 -#define STM32F429_PB2_FUNC_EVENTOUT 0x1210 -#define STM32F429_PB2_FUNC_ANALOG 0x1211 - -#define STM32F429_PB3_FUNC_GPIO 0x1300 -#define STM32F429_PB3_FUNC_JTDO_TRACESWO 0x1301 -#define STM32F429_PB3_FUNC_TIM2_CH2 0x1302 -#define STM32F429_PB3_FUNC_SPI1_SCK 0x1306 -#define STM32F429_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 -#define STM32F429_PB3_FUNC_EVENTOUT 0x1310 -#define STM32F429_PB3_FUNC_ANALOG 0x1311 - -#define STM32F429_PB4_FUNC_GPIO 0x1400 -#define STM32F429_PB4_FUNC_NJTRST 0x1401 -#define STM32F429_PB4_FUNC_TIM3_CH1 0x1403 -#define STM32F429_PB4_FUNC_SPI1_MISO 0x1406 -#define STM32F429_PB4_FUNC_SPI3_MISO 0x1407 -#define STM32F429_PB4_FUNC_I2S3EXT_SD 0x1408 -#define STM32F429_PB4_FUNC_EVENTOUT 0x1410 -#define STM32F429_PB4_FUNC_ANALOG 0x1411 - -#define STM32F429_PB5_FUNC_GPIO 0x1500 -#define STM32F429_PB5_FUNC_TIM3_CH2 0x1503 -#define STM32F429_PB5_FUNC_I2C1_SMBA 0x1505 -#define STM32F429_PB5_FUNC_SPI1_MOSI 0x1506 -#define STM32F429_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507 -#define STM32F429_PB5_FUNC_CAN2_RX 0x150a -#define STM32F429_PB5_FUNC_OTG_HS_ULPI_D7 0x150b -#define STM32F429_PB5_FUNC_ETH_PPS_OUT 0x150c -#define STM32F429_PB5_FUNC_FMC_SDCKE1 0x150d -#define STM32F429_PB5_FUNC_DCMI_D10 0x150e -#define STM32F429_PB5_FUNC_EVENTOUT 0x1510 -#define STM32F429_PB5_FUNC_ANALOG 0x1511 - -#define STM32F429_PB6_FUNC_GPIO 0x1600 -#define STM32F429_PB6_FUNC_TIM4_CH1 0x1603 -#define STM32F429_PB6_FUNC_I2C1_SCL 0x1605 -#define STM32F429_PB6_FUNC_USART1_TX 0x1608 -#define STM32F429_PB6_FUNC_CAN2_TX 0x160a -#define STM32F429_PB6_FUNC_FMC_SDNE1 0x160d -#define STM32F429_PB6_FUNC_DCMI_D5 0x160e -#define STM32F429_PB6_FUNC_EVENTOUT 0x1610 -#define STM32F429_PB6_FUNC_ANALOG 0x1611 - -#define STM32F429_PB7_FUNC_GPIO 0x1700 -#define STM32F429_PB7_FUNC_TIM4_CH2 0x1703 -#define STM32F429_PB7_FUNC_I2C1_SDA 0x1705 -#define STM32F429_PB7_FUNC_USART1_RX 0x1708 -#define STM32F429_PB7_FUNC_FMC_NL 0x170d -#define STM32F429_PB7_FUNC_DCMI_VSYNC 0x170e -#define STM32F429_PB7_FUNC_EVENTOUT 0x1710 -#define STM32F429_PB7_FUNC_ANALOG 0x1711 - -#define STM32F429_PB8_FUNC_GPIO 0x1800 -#define STM32F429_PB8_FUNC_TIM4_CH3 0x1803 -#define STM32F429_PB8_FUNC_TIM10_CH1 0x1804 -#define STM32F429_PB8_FUNC_I2C1_SCL 0x1805 -#define STM32F429_PB8_FUNC_CAN1_RX 0x180a -#define STM32F429_PB8_FUNC_ETH_MII_TXD3 0x180c -#define STM32F429_PB8_FUNC_SDIO_D4 0x180d -#define STM32F429_PB8_FUNC_DCMI_D6 0x180e -#define STM32F429_PB8_FUNC_LCD_B6 0x180f -#define STM32F429_PB8_FUNC_EVENTOUT 0x1810 -#define STM32F429_PB8_FUNC_ANALOG 0x1811 - -#define STM32F429_PB9_FUNC_GPIO 0x1900 -#define STM32F429_PB9_FUNC_TIM4_CH4 0x1903 -#define STM32F429_PB9_FUNC_TIM11_CH1 0x1904 -#define STM32F429_PB9_FUNC_I2C1_SDA 0x1905 -#define STM32F429_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 -#define STM32F429_PB9_FUNC_CAN1_TX 0x190a -#define STM32F429_PB9_FUNC_SDIO_D5 0x190d -#define STM32F429_PB9_FUNC_DCMI_D7 0x190e -#define STM32F429_PB9_FUNC_LCD_B7 0x190f -#define STM32F429_PB9_FUNC_EVENTOUT 0x1910 -#define STM32F429_PB9_FUNC_ANALOG 0x1911 - -#define STM32F429_PB10_FUNC_GPIO 0x1a00 -#define STM32F429_PB10_FUNC_TIM2_CH3 0x1a02 -#define STM32F429_PB10_FUNC_I2C2_SCL 0x1a05 -#define STM32F429_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 -#define STM32F429_PB10_FUNC_USART3_TX 0x1a08 -#define STM32F429_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b -#define STM32F429_PB10_FUNC_ETH_MII_RX_ER 0x1a0c -#define STM32F429_PB10_FUNC_LCD_G4 0x1a0f -#define STM32F429_PB10_FUNC_EVENTOUT 0x1a10 -#define STM32F429_PB10_FUNC_ANALOG 0x1a11 - -#define STM32F429_PB11_FUNC_GPIO 0x1b00 -#define STM32F429_PB11_FUNC_TIM2_CH4 0x1b02 -#define STM32F429_PB11_FUNC_I2C2_SDA 0x1b05 -#define STM32F429_PB11_FUNC_USART3_RX 0x1b08 -#define STM32F429_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b -#define STM32F429_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c -#define STM32F429_PB11_FUNC_LCD_G5 0x1b0f -#define STM32F429_PB11_FUNC_EVENTOUT 0x1b10 -#define STM32F429_PB11_FUNC_ANALOG 0x1b11 - -#define STM32F429_PB12_FUNC_GPIO 0x1c00 -#define STM32F429_PB12_FUNC_TIM1_BKIN 0x1c02 -#define STM32F429_PB12_FUNC_I2C2_SMBA 0x1c05 -#define STM32F429_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 -#define STM32F429_PB12_FUNC_USART3_CK 0x1c08 -#define STM32F429_PB12_FUNC_CAN2_RX 0x1c0a -#define STM32F429_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b -#define STM32F429_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c -#define STM32F429_PB12_FUNC_OTG_HS_ID 0x1c0d -#define STM32F429_PB12_FUNC_EVENTOUT 0x1c10 -#define STM32F429_PB12_FUNC_ANALOG 0x1c11 - -#define STM32F429_PB13_FUNC_GPIO 0x1d00 -#define STM32F429_PB13_FUNC_TIM1_CH1N 0x1d02 -#define STM32F429_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 -#define STM32F429_PB13_FUNC_USART3_CTS 0x1d08 -#define STM32F429_PB13_FUNC_CAN2_TX 0x1d0a -#define STM32F429_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b -#define STM32F429_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c -#define STM32F429_PB13_FUNC_EVENTOUT 0x1d10 -#define STM32F429_PB13_FUNC_ANALOG 0x1d11 - -#define STM32F429_PB14_FUNC_GPIO 0x1e00 -#define STM32F429_PB14_FUNC_TIM1_CH2N 0x1e02 -#define STM32F429_PB14_FUNC_TIM8_CH2N 0x1e04 -#define STM32F429_PB14_FUNC_SPI2_MISO 0x1e06 -#define STM32F429_PB14_FUNC_I2S2EXT_SD 0x1e07 -#define STM32F429_PB14_FUNC_USART3_RTS 0x1e08 -#define STM32F429_PB14_FUNC_TIM12_CH1 0x1e0a -#define STM32F429_PB14_FUNC_OTG_HS_DM 0x1e0d -#define STM32F429_PB14_FUNC_EVENTOUT 0x1e10 -#define STM32F429_PB14_FUNC_ANALOG 0x1e11 - -#define STM32F429_PB15_FUNC_GPIO 0x1f00 -#define STM32F429_PB15_FUNC_RTC_REFIN 0x1f01 -#define STM32F429_PB15_FUNC_TIM1_CH3N 0x1f02 -#define STM32F429_PB15_FUNC_TIM8_CH3N 0x1f04 -#define STM32F429_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06 -#define STM32F429_PB15_FUNC_TIM12_CH2 0x1f0a -#define STM32F429_PB15_FUNC_OTG_HS_DP 0x1f0d -#define STM32F429_PB15_FUNC_EVENTOUT 0x1f10 -#define STM32F429_PB15_FUNC_ANALOG 0x1f11 - - - -#define STM32F429_PC0_FUNC_GPIO 0x2000 -#define STM32F429_PC0_FUNC_OTG_HS_ULPI_STP 0x200b -#define STM32F429_PC0_FUNC_FMC_SDNWE 0x200d -#define STM32F429_PC0_FUNC_EVENTOUT 0x2010 -#define STM32F429_PC0_FUNC_ANALOG 0x2011 - -#define STM32F429_PC1_FUNC_GPIO 0x2100 -#define STM32F429_PC1_FUNC_ETH_MDC 0x210c -#define STM32F429_PC1_FUNC_EVENTOUT 0x2110 -#define STM32F429_PC1_FUNC_ANALOG 0x2111 - -#define STM32F429_PC2_FUNC_GPIO 0x2200 -#define STM32F429_PC2_FUNC_SPI2_MISO 0x2206 -#define STM32F429_PC2_FUNC_I2S2EXT_SD 0x2207 -#define STM32F429_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b -#define STM32F429_PC2_FUNC_ETH_MII_TXD2 0x220c -#define STM32F429_PC2_FUNC_FMC_SDNE0 0x220d -#define STM32F429_PC2_FUNC_EVENTOUT 0x2210 -#define STM32F429_PC2_FUNC_ANALOG 0x2211 - -#define STM32F429_PC3_FUNC_GPIO 0x2300 -#define STM32F429_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306 -#define STM32F429_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b -#define STM32F429_PC3_FUNC_ETH_MII_TX_CLK 0x230c -#define STM32F429_PC3_FUNC_FMC_SDCKE0 0x230d -#define STM32F429_PC3_FUNC_EVENTOUT 0x2310 -#define STM32F429_PC3_FUNC_ANALOG 0x2311 - -#define STM32F429_PC4_FUNC_GPIO 0x2400 -#define STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c -#define STM32F429_PC4_FUNC_EVENTOUT 0x2410 -#define STM32F429_PC4_FUNC_ANALOG 0x2411 - -#define STM32F429_PC5_FUNC_GPIO 0x2500 -#define STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c -#define STM32F429_PC5_FUNC_EVENTOUT 0x2510 -#define STM32F429_PC5_FUNC_ANALOG 0x2511 - -#define STM32F429_PC6_FUNC_GPIO 0x2600 -#define STM32F429_PC6_FUNC_TIM3_CH1 0x2603 -#define STM32F429_PC6_FUNC_TIM8_CH1 0x2604 -#define STM32F429_PC6_FUNC_I2S2_MCK 0x2606 -#define STM32F429_PC6_FUNC_USART6_TX 0x2609 -#define STM32F429_PC6_FUNC_SDIO_D6 0x260d -#define STM32F429_PC6_FUNC_DCMI_D0 0x260e -#define STM32F429_PC6_FUNC_LCD_HSYNC 0x260f -#define STM32F429_PC6_FUNC_EVENTOUT 0x2610 -#define STM32F429_PC6_FUNC_ANALOG 0x2611 - -#define STM32F429_PC7_FUNC_GPIO 0x2700 -#define STM32F429_PC7_FUNC_TIM3_CH2 0x2703 -#define STM32F429_PC7_FUNC_TIM8_CH2 0x2704 -#define STM32F429_PC7_FUNC_I2S3_MCK 0x2707 -#define STM32F429_PC7_FUNC_USART6_RX 0x2709 -#define STM32F429_PC7_FUNC_SDIO_D7 0x270d -#define STM32F429_PC7_FUNC_DCMI_D1 0x270e -#define STM32F429_PC7_FUNC_LCD_G6 0x270f -#define STM32F429_PC7_FUNC_EVENTOUT 0x2710 -#define STM32F429_PC7_FUNC_ANALOG 0x2711 - -#define STM32F429_PC8_FUNC_GPIO 0x2800 -#define STM32F429_PC8_FUNC_TIM3_CH3 0x2803 -#define STM32F429_PC8_FUNC_TIM8_CH3 0x2804 -#define STM32F429_PC8_FUNC_USART6_CK 0x2809 -#define STM32F429_PC8_FUNC_SDIO_D0 0x280d -#define STM32F429_PC8_FUNC_DCMI_D2 0x280e -#define STM32F429_PC8_FUNC_EVENTOUT 0x2810 -#define STM32F429_PC8_FUNC_ANALOG 0x2811 - -#define STM32F429_PC9_FUNC_GPIO 0x2900 -#define STM32F429_PC9_FUNC_MCO2 0x2901 -#define STM32F429_PC9_FUNC_TIM3_CH4 0x2903 -#define STM32F429_PC9_FUNC_TIM8_CH4 0x2904 -#define STM32F429_PC9_FUNC_I2C3_SDA 0x2905 -#define STM32F429_PC9_FUNC_I2S_CKIN 0x2906 -#define STM32F429_PC9_FUNC_SDIO_D1 0x290d -#define STM32F429_PC9_FUNC_DCMI_D3 0x290e -#define STM32F429_PC9_FUNC_EVENTOUT 0x2910 -#define STM32F429_PC9_FUNC_ANALOG 0x2911 - -#define STM32F429_PC10_FUNC_GPIO 0x2a00 -#define STM32F429_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 -#define STM32F429_PC10_FUNC_USART3_TX 0x2a08 -#define STM32F429_PC10_FUNC_UART4_TX 0x2a09 -#define STM32F429_PC10_FUNC_SDIO_D2 0x2a0d -#define STM32F429_PC10_FUNC_DCMI_D8 0x2a0e -#define STM32F429_PC10_FUNC_LCD_R2 0x2a0f -#define STM32F429_PC10_FUNC_EVENTOUT 0x2a10 -#define STM32F429_PC10_FUNC_ANALOG 0x2a11 - -#define STM32F429_PC11_FUNC_GPIO 0x2b00 -#define STM32F429_PC11_FUNC_I2S3EXT_SD 0x2b06 -#define STM32F429_PC11_FUNC_SPI3_MISO 0x2b07 -#define STM32F429_PC11_FUNC_USART3_RX 0x2b08 -#define STM32F429_PC11_FUNC_UART4_RX 0x2b09 -#define STM32F429_PC11_FUNC_SDIO_D3 0x2b0d -#define STM32F429_PC11_FUNC_DCMI_D4 0x2b0e -#define STM32F429_PC11_FUNC_EVENTOUT 0x2b10 -#define STM32F429_PC11_FUNC_ANALOG 0x2b11 - -#define STM32F429_PC12_FUNC_GPIO 0x2c00 -#define STM32F429_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07 -#define STM32F429_PC12_FUNC_USART3_CK 0x2c08 -#define STM32F429_PC12_FUNC_UART5_TX 0x2c09 -#define STM32F429_PC12_FUNC_SDIO_CK 0x2c0d -#define STM32F429_PC12_FUNC_DCMI_D9 0x2c0e -#define STM32F429_PC12_FUNC_EVENTOUT 0x2c10 -#define STM32F429_PC12_FUNC_ANALOG 0x2c11 - -#define STM32F429_PC13_FUNC_GPIO 0x2d00 -#define STM32F429_PC13_FUNC_EVENTOUT 0x2d10 -#define STM32F429_PC13_FUNC_ANALOG 0x2d11 - -#define STM32F429_PC14_FUNC_GPIO 0x2e00 -#define STM32F429_PC14_FUNC_EVENTOUT 0x2e10 -#define STM32F429_PC14_FUNC_ANALOG 0x2e11 - -#define STM32F429_PC15_FUNC_GPIO 0x2f00 -#define STM32F429_PC15_FUNC_EVENTOUT 0x2f10 -#define STM32F429_PC15_FUNC_ANALOG 0x2f11 - - - -#define STM32F429_PD0_FUNC_GPIO 0x3000 -#define STM32F429_PD0_FUNC_CAN1_RX 0x300a -#define STM32F429_PD0_FUNC_FMC_D2 0x300d -#define STM32F429_PD0_FUNC_EVENTOUT 0x3010 -#define STM32F429_PD0_FUNC_ANALOG 0x3011 - -#define STM32F429_PD1_FUNC_GPIO 0x3100 -#define STM32F429_PD1_FUNC_CAN1_TX 0x310a -#define STM32F429_PD1_FUNC_FMC_D3 0x310d -#define STM32F429_PD1_FUNC_EVENTOUT 0x3110 -#define STM32F429_PD1_FUNC_ANALOG 0x3111 - -#define STM32F429_PD2_FUNC_GPIO 0x3200 -#define STM32F429_PD2_FUNC_TIM3_ETR 0x3203 -#define STM32F429_PD2_FUNC_UART5_RX 0x3209 -#define STM32F429_PD2_FUNC_SDIO_CMD 0x320d -#define STM32F429_PD2_FUNC_DCMI_D11 0x320e -#define STM32F429_PD2_FUNC_EVENTOUT 0x3210 -#define STM32F429_PD2_FUNC_ANALOG 0x3211 - -#define STM32F429_PD3_FUNC_GPIO 0x3300 -#define STM32F429_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 -#define STM32F429_PD3_FUNC_USART2_CTS 0x3308 -#define STM32F429_PD3_FUNC_FMC_CLK 0x330d -#define STM32F429_PD3_FUNC_DCMI_D5 0x330e -#define STM32F429_PD3_FUNC_LCD_G7 0x330f -#define STM32F429_PD3_FUNC_EVENTOUT 0x3310 -#define STM32F429_PD3_FUNC_ANALOG 0x3311 - -#define STM32F429_PD4_FUNC_GPIO 0x3400 -#define STM32F429_PD4_FUNC_USART2_RTS 0x3408 -#define STM32F429_PD4_FUNC_FMC_NOE 0x340d -#define STM32F429_PD4_FUNC_EVENTOUT 0x3410 -#define STM32F429_PD4_FUNC_ANALOG 0x3411 - -#define STM32F429_PD5_FUNC_GPIO 0x3500 -#define STM32F429_PD5_FUNC_USART2_TX 0x3508 -#define STM32F429_PD5_FUNC_FMC_NWE 0x350d -#define STM32F429_PD5_FUNC_EVENTOUT 0x3510 -#define STM32F429_PD5_FUNC_ANALOG 0x3511 - -#define STM32F429_PD6_FUNC_GPIO 0x3600 -#define STM32F429_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606 -#define STM32F429_PD6_FUNC_SAI1_SD_A 0x3607 -#define STM32F429_PD6_FUNC_USART2_RX 0x3608 -#define STM32F429_PD6_FUNC_FMC_NWAIT 0x360d -#define STM32F429_PD6_FUNC_DCMI_D10 0x360e -#define STM32F429_PD6_FUNC_LCD_B2 0x360f -#define STM32F429_PD6_FUNC_EVENTOUT 0x3610 -#define STM32F429_PD6_FUNC_ANALOG 0x3611 - -#define STM32F429_PD7_FUNC_GPIO 0x3700 -#define STM32F429_PD7_FUNC_USART2_CK 0x3708 -#define STM32F429_PD7_FUNC_FMC_NE1_FMC_NCE2 0x370d -#define STM32F429_PD7_FUNC_EVENTOUT 0x3710 -#define STM32F429_PD7_FUNC_ANALOG 0x3711 - -#define STM32F429_PD8_FUNC_GPIO 0x3800 -#define STM32F429_PD8_FUNC_USART3_TX 0x3808 -#define STM32F429_PD8_FUNC_FMC_D13 0x380d -#define STM32F429_PD8_FUNC_EVENTOUT 0x3810 -#define STM32F429_PD8_FUNC_ANALOG 0x3811 - -#define STM32F429_PD9_FUNC_GPIO 0x3900 -#define STM32F429_PD9_FUNC_USART3_RX 0x3908 -#define STM32F429_PD9_FUNC_FMC_D14 0x390d -#define STM32F429_PD9_FUNC_EVENTOUT 0x3910 -#define STM32F429_PD9_FUNC_ANALOG 0x3911 - -#define STM32F429_PD10_FUNC_GPIO 0x3a00 -#define STM32F429_PD10_FUNC_USART3_CK 0x3a08 -#define STM32F429_PD10_FUNC_FMC_D15 0x3a0d -#define STM32F429_PD10_FUNC_LCD_B3 0x3a0f -#define STM32F429_PD10_FUNC_EVENTOUT 0x3a10 -#define STM32F429_PD10_FUNC_ANALOG 0x3a11 - -#define STM32F429_PD11_FUNC_GPIO 0x3b00 -#define STM32F429_PD11_FUNC_USART3_CTS 0x3b08 -#define STM32F429_PD11_FUNC_FMC_A16 0x3b0d -#define STM32F429_PD11_FUNC_EVENTOUT 0x3b10 -#define STM32F429_PD11_FUNC_ANALOG 0x3b11 - -#define STM32F429_PD12_FUNC_GPIO 0x3c00 -#define STM32F429_PD12_FUNC_TIM4_CH1 0x3c03 -#define STM32F429_PD12_FUNC_USART3_RTS 0x3c08 -#define STM32F429_PD12_FUNC_FMC_A17 0x3c0d -#define STM32F429_PD12_FUNC_EVENTOUT 0x3c10 -#define STM32F429_PD12_FUNC_ANALOG 0x3c11 - -#define STM32F429_PD13_FUNC_GPIO 0x3d00 -#define STM32F429_PD13_FUNC_TIM4_CH2 0x3d03 -#define STM32F429_PD13_FUNC_FMC_A18 0x3d0d -#define STM32F429_PD13_FUNC_EVENTOUT 0x3d10 -#define STM32F429_PD13_FUNC_ANALOG 0x3d11 - -#define STM32F429_PD14_FUNC_GPIO 0x3e00 -#define STM32F429_PD14_FUNC_TIM4_CH3 0x3e03 -#define STM32F429_PD14_FUNC_FMC_D0 0x3e0d -#define STM32F429_PD14_FUNC_EVENTOUT 0x3e10 -#define STM32F429_PD14_FUNC_ANALOG 0x3e11 - -#define STM32F429_PD15_FUNC_GPIO 0x3f00 -#define STM32F429_PD15_FUNC_TIM4_CH4 0x3f03 -#define STM32F429_PD15_FUNC_FMC_D1 0x3f0d -#define STM32F429_PD15_FUNC_EVENTOUT 0x3f10 -#define STM32F429_PD15_FUNC_ANALOG 0x3f11 - - - -#define STM32F429_PE0_FUNC_GPIO 0x4000 -#define STM32F429_PE0_FUNC_TIM4_ETR 0x4003 -#define STM32F429_PE0_FUNC_UART8_RX 0x4009 -#define STM32F429_PE0_FUNC_FMC_NBL0 0x400d -#define STM32F429_PE0_FUNC_DCMI_D2 0x400e -#define STM32F429_PE0_FUNC_EVENTOUT 0x4010 -#define STM32F429_PE0_FUNC_ANALOG 0x4011 - -#define STM32F429_PE1_FUNC_GPIO 0x4100 -#define STM32F429_PE1_FUNC_UART8_TX 0x4109 -#define STM32F429_PE1_FUNC_FMC_NBL1 0x410d -#define STM32F429_PE1_FUNC_DCMI_D3 0x410e -#define STM32F429_PE1_FUNC_EVENTOUT 0x4110 -#define STM32F429_PE1_FUNC_ANALOG 0x4111 - -#define STM32F429_PE2_FUNC_GPIO 0x4200 -#define STM32F429_PE2_FUNC_TRACECLK 0x4201 -#define STM32F429_PE2_FUNC_SPI4_SCK 0x4206 -#define STM32F429_PE2_FUNC_SAI1_MCLK_A 0x4207 -#define STM32F429_PE2_FUNC_ETH_MII_TXD3 0x420c -#define STM32F429_PE2_FUNC_FMC_A23 0x420d -#define STM32F429_PE2_FUNC_EVENTOUT 0x4210 -#define STM32F429_PE2_FUNC_ANALOG 0x4211 - -#define STM32F429_PE3_FUNC_GPIO 0x4300 -#define STM32F429_PE3_FUNC_TRACED0 0x4301 -#define STM32F429_PE3_FUNC_SAI1_SD_B 0x4307 -#define STM32F429_PE3_FUNC_FMC_A19 0x430d -#define STM32F429_PE3_FUNC_EVENTOUT 0x4310 -#define STM32F429_PE3_FUNC_ANALOG 0x4311 - -#define STM32F429_PE4_FUNC_GPIO 0x4400 -#define STM32F429_PE4_FUNC_TRACED1 0x4401 -#define STM32F429_PE4_FUNC_SPI4_NSS 0x4406 -#define STM32F429_PE4_FUNC_SAI1_FS_A 0x4407 -#define STM32F429_PE4_FUNC_FMC_A20 0x440d -#define STM32F429_PE4_FUNC_DCMI_D4 0x440e -#define STM32F429_PE4_FUNC_LCD_B0 0x440f -#define STM32F429_PE4_FUNC_EVENTOUT 0x4410 -#define STM32F429_PE4_FUNC_ANALOG 0x4411 - -#define STM32F429_PE5_FUNC_GPIO 0x4500 -#define STM32F429_PE5_FUNC_TRACED2 0x4501 -#define STM32F429_PE5_FUNC_TIM9_CH1 0x4504 -#define STM32F429_PE5_FUNC_SPI4_MISO 0x4506 -#define STM32F429_PE5_FUNC_SAI1_SCK_A 0x4507 -#define STM32F429_PE5_FUNC_FMC_A21 0x450d -#define STM32F429_PE5_FUNC_DCMI_D6 0x450e -#define STM32F429_PE5_FUNC_LCD_G0 0x450f -#define STM32F429_PE5_FUNC_EVENTOUT 0x4510 -#define STM32F429_PE5_FUNC_ANALOG 0x4511 - -#define STM32F429_PE6_FUNC_GPIO 0x4600 -#define STM32F429_PE6_FUNC_TRACED3 0x4601 -#define STM32F429_PE6_FUNC_TIM9_CH2 0x4604 -#define STM32F429_PE6_FUNC_SPI4_MOSI 0x4606 -#define STM32F429_PE6_FUNC_SAI1_SD_A 0x4607 -#define STM32F429_PE6_FUNC_FMC_A22 0x460d -#define STM32F429_PE6_FUNC_DCMI_D7 0x460e -#define STM32F429_PE6_FUNC_LCD_G1 0x460f -#define STM32F429_PE6_FUNC_EVENTOUT 0x4610 -#define STM32F429_PE6_FUNC_ANALOG 0x4611 - -#define STM32F429_PE7_FUNC_GPIO 0x4700 -#define STM32F429_PE7_FUNC_TIM1_ETR 0x4702 -#define STM32F429_PE7_FUNC_UART7_RX 0x4709 -#define STM32F429_PE7_FUNC_FMC_D4 0x470d -#define STM32F429_PE7_FUNC_EVENTOUT 0x4710 -#define STM32F429_PE7_FUNC_ANALOG 0x4711 - -#define STM32F429_PE8_FUNC_GPIO 0x4800 -#define STM32F429_PE8_FUNC_TIM1_CH1N 0x4802 -#define STM32F429_PE8_FUNC_UART7_TX 0x4809 -#define STM32F429_PE8_FUNC_FMC_D5 0x480d -#define STM32F429_PE8_FUNC_EVENTOUT 0x4810 -#define STM32F429_PE8_FUNC_ANALOG 0x4811 - -#define STM32F429_PE9_FUNC_GPIO 0x4900 -#define STM32F429_PE9_FUNC_TIM1_CH1 0x4902 -#define STM32F429_PE9_FUNC_FMC_D6 0x490d -#define STM32F429_PE9_FUNC_EVENTOUT 0x4910 -#define STM32F429_PE9_FUNC_ANALOG 0x4911 - -#define STM32F429_PE10_FUNC_GPIO 0x4a00 -#define STM32F429_PE10_FUNC_TIM1_CH2N 0x4a02 -#define STM32F429_PE10_FUNC_FMC_D7 0x4a0d -#define STM32F429_PE10_FUNC_EVENTOUT 0x4a10 -#define STM32F429_PE10_FUNC_ANALOG 0x4a11 - -#define STM32F429_PE11_FUNC_GPIO 0x4b00 -#define STM32F429_PE11_FUNC_TIM1_CH2 0x4b02 -#define STM32F429_PE11_FUNC_SPI4_NSS 0x4b06 -#define STM32F429_PE11_FUNC_FMC_D8 0x4b0d -#define STM32F429_PE11_FUNC_LCD_G3 0x4b0f -#define STM32F429_PE11_FUNC_EVENTOUT 0x4b10 -#define STM32F429_PE11_FUNC_ANALOG 0x4b11 - -#define STM32F429_PE12_FUNC_GPIO 0x4c00 -#define STM32F429_PE12_FUNC_TIM1_CH3N 0x4c02 -#define STM32F429_PE12_FUNC_SPI4_SCK 0x4c06 -#define STM32F429_PE12_FUNC_FMC_D9 0x4c0d -#define STM32F429_PE12_FUNC_LCD_B4 0x4c0f -#define STM32F429_PE12_FUNC_EVENTOUT 0x4c10 -#define STM32F429_PE12_FUNC_ANALOG 0x4c11 - -#define STM32F429_PE13_FUNC_GPIO 0x4d00 -#define STM32F429_PE13_FUNC_TIM1_CH3 0x4d02 -#define STM32F429_PE13_FUNC_SPI4_MISO 0x4d06 -#define STM32F429_PE13_FUNC_FMC_D10 0x4d0d -#define STM32F429_PE13_FUNC_LCD_DE 0x4d0f -#define STM32F429_PE13_FUNC_EVENTOUT 0x4d10 -#define STM32F429_PE13_FUNC_ANALOG 0x4d11 - -#define STM32F429_PE14_FUNC_GPIO 0x4e00 -#define STM32F429_PE14_FUNC_TIM1_CH4 0x4e02 -#define STM32F429_PE14_FUNC_SPI4_MOSI 0x4e06 -#define STM32F429_PE14_FUNC_FMC_D11 0x4e0d -#define STM32F429_PE14_FUNC_LCD_CLK 0x4e0f -#define STM32F429_PE14_FUNC_EVENTOUT 0x4e10 -#define STM32F429_PE14_FUNC_ANALOG 0x4e11 - -#define STM32F429_PE15_FUNC_GPIO 0x4f00 -#define STM32F429_PE15_FUNC_TIM1_BKIN 0x4f02 -#define STM32F429_PE15_FUNC_FMC_D12 0x4f0d -#define STM32F429_PE15_FUNC_LCD_R7 0x4f0f -#define STM32F429_PE15_FUNC_EVENTOUT 0x4f10 -#define STM32F429_PE15_FUNC_ANALOG 0x4f11 - - - -#define STM32F429_PF0_FUNC_GPIO 0x5000 -#define STM32F429_PF0_FUNC_I2C2_SDA 0x5005 -#define STM32F429_PF0_FUNC_FMC_A0 0x500d -#define STM32F429_PF0_FUNC_EVENTOUT 0x5010 -#define STM32F429_PF0_FUNC_ANALOG 0x5011 - -#define STM32F429_PF1_FUNC_GPIO 0x5100 -#define STM32F429_PF1_FUNC_I2C2_SCL 0x5105 -#define STM32F429_PF1_FUNC_FMC_A1 0x510d -#define STM32F429_PF1_FUNC_EVENTOUT 0x5110 -#define STM32F429_PF1_FUNC_ANALOG 0x5111 - -#define STM32F429_PF2_FUNC_GPIO 0x5200 -#define STM32F429_PF2_FUNC_I2C2_SMBA 0x5205 -#define STM32F429_PF2_FUNC_FMC_A2 0x520d -#define STM32F429_PF2_FUNC_EVENTOUT 0x5210 -#define STM32F429_PF2_FUNC_ANALOG 0x5211 - -#define STM32F429_PF3_FUNC_GPIO 0x5300 -#define STM32F429_PF3_FUNC_FMC_A3 0x530d -#define STM32F429_PF3_FUNC_EVENTOUT 0x5310 -#define STM32F429_PF3_FUNC_ANALOG 0x5311 - -#define STM32F429_PF4_FUNC_GPIO 0x5400 -#define STM32F429_PF4_FUNC_FMC_A4 0x540d -#define STM32F429_PF4_FUNC_EVENTOUT 0x5410 -#define STM32F429_PF4_FUNC_ANALOG 0x5411 - -#define STM32F429_PF5_FUNC_GPIO 0x5500 -#define STM32F429_PF5_FUNC_FMC_A5 0x550d -#define STM32F429_PF5_FUNC_EVENTOUT 0x5510 -#define STM32F429_PF5_FUNC_ANALOG 0x5511 - -#define STM32F429_PF6_FUNC_GPIO 0x5600 -#define STM32F429_PF6_FUNC_TIM10_CH1 0x5604 -#define STM32F429_PF6_FUNC_SPI5_NSS 0x5606 -#define STM32F429_PF6_FUNC_SAI1_SD_B 0x5607 -#define STM32F429_PF6_FUNC_UART7_RX 0x5609 -#define STM32F429_PF6_FUNC_FMC_NIORD 0x560d -#define STM32F429_PF6_FUNC_EVENTOUT 0x5610 -#define STM32F429_PF6_FUNC_ANALOG 0x5611 - -#define STM32F429_PF7_FUNC_GPIO 0x5700 -#define STM32F429_PF7_FUNC_TIM11_CH1 0x5704 -#define STM32F429_PF7_FUNC_SPI5_SCK 0x5706 -#define STM32F429_PF7_FUNC_SAI1_MCLK_B 0x5707 -#define STM32F429_PF7_FUNC_UART7_TX 0x5709 -#define STM32F429_PF7_FUNC_FMC_NREG 0x570d -#define STM32F429_PF7_FUNC_EVENTOUT 0x5710 -#define STM32F429_PF7_FUNC_ANALOG 0x5711 - -#define STM32F429_PF8_FUNC_GPIO 0x5800 -#define STM32F429_PF8_FUNC_SPI5_MISO 0x5806 -#define STM32F429_PF8_FUNC_SAI1_SCK_B 0x5807 -#define STM32F429_PF8_FUNC_TIM13_CH1 0x580a -#define STM32F429_PF8_FUNC_FMC_NIOWR 0x580d -#define STM32F429_PF8_FUNC_EVENTOUT 0x5810 -#define STM32F429_PF8_FUNC_ANALOG 0x5811 - -#define STM32F429_PF9_FUNC_GPIO 0x5900 -#define STM32F429_PF9_FUNC_SPI5_MOSI 0x5906 -#define STM32F429_PF9_FUNC_SAI1_FS_B 0x5907 -#define STM32F429_PF9_FUNC_TIM14_CH1 0x590a -#define STM32F429_PF9_FUNC_FMC_CD 0x590d -#define STM32F429_PF9_FUNC_EVENTOUT 0x5910 -#define STM32F429_PF9_FUNC_ANALOG 0x5911 - -#define STM32F429_PF10_FUNC_GPIO 0x5a00 -#define STM32F429_PF10_FUNC_FMC_INTR 0x5a0d -#define STM32F429_PF10_FUNC_DCMI_D11 0x5a0e -#define STM32F429_PF10_FUNC_LCD_DE 0x5a0f -#define STM32F429_PF10_FUNC_EVENTOUT 0x5a10 -#define STM32F429_PF10_FUNC_ANALOG 0x5a11 - -#define STM32F429_PF11_FUNC_GPIO 0x5b00 -#define STM32F429_PF11_FUNC_SPI5_MOSI 0x5b06 -#define STM32F429_PF11_FUNC_FMC_SDNRAS 0x5b0d -#define STM32F429_PF11_FUNC_DCMI_D12 0x5b0e -#define STM32F429_PF11_FUNC_EVENTOUT 0x5b10 -#define STM32F429_PF11_FUNC_ANALOG 0x5b11 - -#define STM32F429_PF12_FUNC_GPIO 0x5c00 -#define STM32F429_PF12_FUNC_FMC_A6 0x5c0d -#define STM32F429_PF12_FUNC_EVENTOUT 0x5c10 -#define STM32F429_PF12_FUNC_ANALOG 0x5c11 - -#define STM32F429_PF13_FUNC_GPIO 0x5d00 -#define STM32F429_PF13_FUNC_FMC_A7 0x5d0d -#define STM32F429_PF13_FUNC_EVENTOUT 0x5d10 -#define STM32F429_PF13_FUNC_ANALOG 0x5d11 - -#define STM32F429_PF14_FUNC_GPIO 0x5e00 -#define STM32F429_PF14_FUNC_FMC_A8 0x5e0d -#define STM32F429_PF14_FUNC_EVENTOUT 0x5e10 -#define STM32F429_PF14_FUNC_ANALOG 0x5e11 - -#define STM32F429_PF15_FUNC_GPIO 0x5f00 -#define STM32F429_PF15_FUNC_FMC_A9 0x5f0d -#define STM32F429_PF15_FUNC_EVENTOUT 0x5f10 -#define STM32F429_PF15_FUNC_ANALOG 0x5f11 - - - -#define STM32F429_PG0_FUNC_GPIO 0x6000 -#define STM32F429_PG0_FUNC_FMC_A10 0x600d -#define STM32F429_PG0_FUNC_EVENTOUT 0x6010 -#define STM32F429_PG0_FUNC_ANALOG 0x6011 - -#define STM32F429_PG1_FUNC_GPIO 0x6100 -#define STM32F429_PG1_FUNC_FMC_A11 0x610d -#define STM32F429_PG1_FUNC_EVENTOUT 0x6110 -#define STM32F429_PG1_FUNC_ANALOG 0x6111 - -#define STM32F429_PG2_FUNC_GPIO 0x6200 -#define STM32F429_PG2_FUNC_FMC_A12 0x620d -#define STM32F429_PG2_FUNC_EVENTOUT 0x6210 -#define STM32F429_PG2_FUNC_ANALOG 0x6211 - -#define STM32F429_PG3_FUNC_GPIO 0x6300 -#define STM32F429_PG3_FUNC_FMC_A13 0x630d -#define STM32F429_PG3_FUNC_EVENTOUT 0x6310 -#define STM32F429_PG3_FUNC_ANALOG 0x6311 - -#define STM32F429_PG4_FUNC_GPIO 0x6400 -#define STM32F429_PG4_FUNC_FMC_A14_FMC_BA0 0x640d -#define STM32F429_PG4_FUNC_EVENTOUT 0x6410 -#define STM32F429_PG4_FUNC_ANALOG 0x6411 - -#define STM32F429_PG5_FUNC_GPIO 0x6500 -#define STM32F429_PG5_FUNC_FMC_A15_FMC_BA1 0x650d -#define STM32F429_PG5_FUNC_EVENTOUT 0x6510 -#define STM32F429_PG5_FUNC_ANALOG 0x6511 - -#define STM32F429_PG6_FUNC_GPIO 0x6600 -#define STM32F429_PG6_FUNC_FMC_INT2 0x660d -#define STM32F429_PG6_FUNC_DCMI_D12 0x660e -#define STM32F429_PG6_FUNC_LCD_R7 0x660f -#define STM32F429_PG6_FUNC_EVENTOUT 0x6610 -#define STM32F429_PG6_FUNC_ANALOG 0x6611 - -#define STM32F429_PG7_FUNC_GPIO 0x6700 -#define STM32F429_PG7_FUNC_USART6_CK 0x6709 -#define STM32F429_PG7_FUNC_FMC_INT3 0x670d -#define STM32F429_PG7_FUNC_DCMI_D13 0x670e -#define STM32F429_PG7_FUNC_LCD_CLK 0x670f -#define STM32F429_PG7_FUNC_EVENTOUT 0x6710 -#define STM32F429_PG7_FUNC_ANALOG 0x6711 - -#define STM32F429_PG8_FUNC_GPIO 0x6800 -#define STM32F429_PG8_FUNC_SPI6_NSS 0x6806 -#define STM32F429_PG8_FUNC_USART6_RTS 0x6809 -#define STM32F429_PG8_FUNC_ETH_PPS_OUT 0x680c -#define STM32F429_PG8_FUNC_FMC_SDCLK 0x680d -#define STM32F429_PG8_FUNC_EVENTOUT 0x6810 -#define STM32F429_PG8_FUNC_ANALOG 0x6811 - -#define STM32F429_PG9_FUNC_GPIO 0x6900 -#define STM32F429_PG9_FUNC_USART6_RX 0x6909 -#define STM32F429_PG9_FUNC_FMC_NE2_FMC_NCE3 0x690d -#define STM32F429_PG9_FUNC_DCMI_VSYNC 0x690e -#define STM32F429_PG9_FUNC_EVENTOUT 0x6910 -#define STM32F429_PG9_FUNC_ANALOG 0x6911 - -#define STM32F429_PG10_FUNC_GPIO 0x6a00 -#define STM32F429_PG10_FUNC_LCD_G3 0x6a0a -#define STM32F429_PG10_FUNC_FMC_NCE4_1_FMC_NE3 0x6a0d -#define STM32F429_PG10_FUNC_DCMI_D2 0x6a0e -#define STM32F429_PG10_FUNC_LCD_B2 0x6a0f -#define STM32F429_PG10_FUNC_EVENTOUT 0x6a10 -#define STM32F429_PG10_FUNC_ANALOG 0x6a11 - -#define STM32F429_PG11_FUNC_GPIO 0x6b00 -#define STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c -#define STM32F429_PG11_FUNC_FMC_NCE4_2 0x6b0d -#define STM32F429_PG11_FUNC_DCMI_D3 0x6b0e -#define STM32F429_PG11_FUNC_LCD_B3 0x6b0f -#define STM32F429_PG11_FUNC_EVENTOUT 0x6b10 -#define STM32F429_PG11_FUNC_ANALOG 0x6b11 - -#define STM32F429_PG12_FUNC_GPIO 0x6c00 -#define STM32F429_PG12_FUNC_SPI6_MISO 0x6c06 -#define STM32F429_PG12_FUNC_USART6_RTS 0x6c09 -#define STM32F429_PG12_FUNC_LCD_B4 0x6c0a -#define STM32F429_PG12_FUNC_FMC_NE4 0x6c0d -#define STM32F429_PG12_FUNC_LCD_B1 0x6c0f -#define STM32F429_PG12_FUNC_EVENTOUT 0x6c10 -#define STM32F429_PG12_FUNC_ANALOG 0x6c11 - -#define STM32F429_PG13_FUNC_GPIO 0x6d00 -#define STM32F429_PG13_FUNC_SPI6_SCK 0x6d06 -#define STM32F429_PG13_FUNC_USART6_CTS 0x6d09 -#define STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c -#define STM32F429_PG13_FUNC_FMC_A24 0x6d0d -#define STM32F429_PG13_FUNC_EVENTOUT 0x6d10 -#define STM32F429_PG13_FUNC_ANALOG 0x6d11 - -#define STM32F429_PG14_FUNC_GPIO 0x6e00 -#define STM32F429_PG14_FUNC_SPI6_MOSI 0x6e06 -#define STM32F429_PG14_FUNC_USART6_TX 0x6e09 -#define STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c -#define STM32F429_PG14_FUNC_FMC_A25 0x6e0d -#define STM32F429_PG14_FUNC_EVENTOUT 0x6e10 -#define STM32F429_PG14_FUNC_ANALOG 0x6e11 - -#define STM32F429_PG15_FUNC_GPIO 0x6f00 -#define STM32F429_PG15_FUNC_USART6_CTS 0x6f09 -#define STM32F429_PG15_FUNC_FMC_SDNCAS 0x6f0d -#define STM32F429_PG15_FUNC_DCMI_D13 0x6f0e -#define STM32F429_PG15_FUNC_EVENTOUT 0x6f10 -#define STM32F429_PG15_FUNC_ANALOG 0x6f11 - - - -#define STM32F429_PH0_FUNC_GPIO 0x7000 -#define STM32F429_PH0_FUNC_EVENTOUT 0x7010 -#define STM32F429_PH0_FUNC_ANALOG 0x7011 - -#define STM32F429_PH1_FUNC_GPIO 0x7100 -#define STM32F429_PH1_FUNC_EVENTOUT 0x7110 -#define STM32F429_PH1_FUNC_ANALOG 0x7111 - -#define STM32F429_PH2_FUNC_GPIO 0x7200 -#define STM32F429_PH2_FUNC_ETH_MII_CRS 0x720c -#define STM32F429_PH2_FUNC_FMC_SDCKE0 0x720d -#define STM32F429_PH2_FUNC_LCD_R0 0x720f -#define STM32F429_PH2_FUNC_EVENTOUT 0x7210 -#define STM32F429_PH2_FUNC_ANALOG 0x7211 - -#define STM32F429_PH3_FUNC_GPIO 0x7300 -#define STM32F429_PH3_FUNC_ETH_MII_COL 0x730c -#define STM32F429_PH3_FUNC_FMC_SDNE0 0x730d -#define STM32F429_PH3_FUNC_LCD_R1 0x730f -#define STM32F429_PH3_FUNC_EVENTOUT 0x7310 -#define STM32F429_PH3_FUNC_ANALOG 0x7311 - -#define STM32F429_PH4_FUNC_GPIO 0x7400 -#define STM32F429_PH4_FUNC_I2C2_SCL 0x7405 -#define STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b -#define STM32F429_PH4_FUNC_EVENTOUT 0x7410 -#define STM32F429_PH4_FUNC_ANALOG 0x7411 - -#define STM32F429_PH5_FUNC_GPIO 0x7500 -#define STM32F429_PH5_FUNC_I2C2_SDA 0x7505 -#define STM32F429_PH5_FUNC_SPI5_NSS 0x7506 -#define STM32F429_PH5_FUNC_FMC_SDNWE 0x750d -#define STM32F429_PH5_FUNC_EVENTOUT 0x7510 -#define STM32F429_PH5_FUNC_ANALOG 0x7511 - -#define STM32F429_PH6_FUNC_GPIO 0x7600 -#define STM32F429_PH6_FUNC_I2C2_SMBA 0x7605 -#define STM32F429_PH6_FUNC_SPI5_SCK 0x7606 -#define STM32F429_PH6_FUNC_TIM12_CH1 0x760a -#define STM32F429_PH6_FUNC_ETH_MII_RXD2 0x760c -#define STM32F429_PH6_FUNC_FMC_SDNE1 0x760d -#define STM32F429_PH6_FUNC_DCMI_D8 0x760e -#define STM32F429_PH6_FUNC_EVENTOUT 0x7610 -#define STM32F429_PH6_FUNC_ANALOG 0x7611 - -#define STM32F429_PH7_FUNC_GPIO 0x7700 -#define STM32F429_PH7_FUNC_I2C3_SCL 0x7705 -#define STM32F429_PH7_FUNC_SPI5_MISO 0x7706 -#define STM32F429_PH7_FUNC_ETH_MII_RXD3 0x770c -#define STM32F429_PH7_FUNC_FMC_SDCKE1 0x770d -#define STM32F429_PH7_FUNC_DCMI_D9 0x770e -#define STM32F429_PH7_FUNC_EVENTOUT 0x7710 -#define STM32F429_PH7_FUNC_ANALOG 0x7711 - -#define STM32F429_PH8_FUNC_GPIO 0x7800 -#define STM32F429_PH8_FUNC_I2C3_SDA 0x7805 -#define STM32F429_PH8_FUNC_FMC_D16 0x780d -#define STM32F429_PH8_FUNC_DCMI_HSYNC 0x780e -#define STM32F429_PH8_FUNC_LCD_R2 0x780f -#define STM32F429_PH8_FUNC_EVENTOUT 0x7810 -#define STM32F429_PH8_FUNC_ANALOG 0x7811 - -#define STM32F429_PH9_FUNC_GPIO 0x7900 -#define STM32F429_PH9_FUNC_I2C3_SMBA 0x7905 -#define STM32F429_PH9_FUNC_TIM12_CH2 0x790a -#define STM32F429_PH9_FUNC_FMC_D17 0x790d -#define STM32F429_PH9_FUNC_DCMI_D0 0x790e -#define STM32F429_PH9_FUNC_LCD_R3 0x790f -#define STM32F429_PH9_FUNC_EVENTOUT 0x7910 -#define STM32F429_PH9_FUNC_ANALOG 0x7911 - -#define STM32F429_PH10_FUNC_GPIO 0x7a00 -#define STM32F429_PH10_FUNC_TIM5_CH1 0x7a03 -#define STM32F429_PH10_FUNC_FMC_D18 0x7a0d -#define STM32F429_PH10_FUNC_DCMI_D1 0x7a0e -#define STM32F429_PH10_FUNC_LCD_R4 0x7a0f -#define STM32F429_PH10_FUNC_EVENTOUT 0x7a10 -#define STM32F429_PH10_FUNC_ANALOG 0x7a11 - -#define STM32F429_PH11_FUNC_GPIO 0x7b00 -#define STM32F429_PH11_FUNC_TIM5_CH2 0x7b03 -#define STM32F429_PH11_FUNC_FMC_D19 0x7b0d -#define STM32F429_PH11_FUNC_DCMI_D2 0x7b0e -#define STM32F429_PH11_FUNC_LCD_R5 0x7b0f -#define STM32F429_PH11_FUNC_EVENTOUT 0x7b10 -#define STM32F429_PH11_FUNC_ANALOG 0x7b11 - -#define STM32F429_PH12_FUNC_GPIO 0x7c00 -#define STM32F429_PH12_FUNC_TIM5_CH3 0x7c03 -#define STM32F429_PH12_FUNC_FMC_D20 0x7c0d -#define STM32F429_PH12_FUNC_DCMI_D3 0x7c0e -#define STM32F429_PH12_FUNC_LCD_R6 0x7c0f -#define STM32F429_PH12_FUNC_EVENTOUT 0x7c10 -#define STM32F429_PH12_FUNC_ANALOG 0x7c11 - -#define STM32F429_PH13_FUNC_GPIO 0x7d00 -#define STM32F429_PH13_FUNC_TIM8_CH1N 0x7d04 -#define STM32F429_PH13_FUNC_CAN1_TX 0x7d0a -#define STM32F429_PH13_FUNC_FMC_D21 0x7d0d -#define STM32F429_PH13_FUNC_LCD_G2 0x7d0f -#define STM32F429_PH13_FUNC_EVENTOUT 0x7d10 -#define STM32F429_PH13_FUNC_ANALOG 0x7d11 - -#define STM32F429_PH14_FUNC_GPIO 0x7e00 -#define STM32F429_PH14_FUNC_TIM8_CH2N 0x7e04 -#define STM32F429_PH14_FUNC_FMC_D22 0x7e0d -#define STM32F429_PH14_FUNC_DCMI_D4 0x7e0e -#define STM32F429_PH14_FUNC_LCD_G3 0x7e0f -#define STM32F429_PH14_FUNC_EVENTOUT 0x7e10 -#define STM32F429_PH14_FUNC_ANALOG 0x7e11 - -#define STM32F429_PH15_FUNC_GPIO 0x7f00 -#define STM32F429_PH15_FUNC_TIM8_CH3N 0x7f04 -#define STM32F429_PH15_FUNC_FMC_D23 0x7f0d -#define STM32F429_PH15_FUNC_DCMI_D11 0x7f0e -#define STM32F429_PH15_FUNC_LCD_G4 0x7f0f -#define STM32F429_PH15_FUNC_EVENTOUT 0x7f10 -#define STM32F429_PH15_FUNC_ANALOG 0x7f11 - - - -#define STM32F429_PI0_FUNC_GPIO 0x8000 -#define STM32F429_PI0_FUNC_TIM5_CH4 0x8003 -#define STM32F429_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 -#define STM32F429_PI0_FUNC_FMC_D24 0x800d -#define STM32F429_PI0_FUNC_DCMI_D13 0x800e -#define STM32F429_PI0_FUNC_LCD_G5 0x800f -#define STM32F429_PI0_FUNC_EVENTOUT 0x8010 -#define STM32F429_PI0_FUNC_ANALOG 0x8011 - -#define STM32F429_PI1_FUNC_GPIO 0x8100 -#define STM32F429_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 -#define STM32F429_PI1_FUNC_FMC_D25 0x810d -#define STM32F429_PI1_FUNC_DCMI_D8 0x810e -#define STM32F429_PI1_FUNC_LCD_G6 0x810f -#define STM32F429_PI1_FUNC_EVENTOUT 0x8110 -#define STM32F429_PI1_FUNC_ANALOG 0x8111 - -#define STM32F429_PI2_FUNC_GPIO 0x8200 -#define STM32F429_PI2_FUNC_TIM8_CH4 0x8204 -#define STM32F429_PI2_FUNC_SPI2_MISO 0x8206 -#define STM32F429_PI2_FUNC_I2S2EXT_SD 0x8207 -#define STM32F429_PI2_FUNC_FMC_D26 0x820d -#define STM32F429_PI2_FUNC_DCMI_D9 0x820e -#define STM32F429_PI2_FUNC_LCD_G7 0x820f -#define STM32F429_PI2_FUNC_EVENTOUT 0x8210 -#define STM32F429_PI2_FUNC_ANALOG 0x8211 - -#define STM32F429_PI3_FUNC_GPIO 0x8300 -#define STM32F429_PI3_FUNC_TIM8_ETR 0x8304 -#define STM32F429_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306 -#define STM32F429_PI3_FUNC_FMC_D27 0x830d -#define STM32F429_PI3_FUNC_DCMI_D10 0x830e -#define STM32F429_PI3_FUNC_EVENTOUT 0x8310 -#define STM32F429_PI3_FUNC_ANALOG 0x8311 - -#define STM32F429_PI4_FUNC_GPIO 0x8400 -#define STM32F429_PI4_FUNC_TIM8_BKIN 0x8404 -#define STM32F429_PI4_FUNC_FMC_NBL2 0x840d -#define STM32F429_PI4_FUNC_DCMI_D5 0x840e -#define STM32F429_PI4_FUNC_LCD_B4 0x840f -#define STM32F429_PI4_FUNC_EVENTOUT 0x8410 -#define STM32F429_PI4_FUNC_ANALOG 0x8411 - -#define STM32F429_PI5_FUNC_GPIO 0x8500 -#define STM32F429_PI5_FUNC_TIM8_CH1 0x8504 -#define STM32F429_PI5_FUNC_FMC_NBL3 0x850d -#define STM32F429_PI5_FUNC_DCMI_VSYNC 0x850e -#define STM32F429_PI5_FUNC_LCD_B5 0x850f -#define STM32F429_PI5_FUNC_EVENTOUT 0x8510 -#define STM32F429_PI5_FUNC_ANALOG 0x8511 - -#define STM32F429_PI6_FUNC_GPIO 0x8600 -#define STM32F429_PI6_FUNC_TIM8_CH2 0x8604 -#define STM32F429_PI6_FUNC_FMC_D28 0x860d -#define STM32F429_PI6_FUNC_DCMI_D6 0x860e -#define STM32F429_PI6_FUNC_LCD_B6 0x860f -#define STM32F429_PI6_FUNC_EVENTOUT 0x8610 -#define STM32F429_PI6_FUNC_ANALOG 0x8611 - -#define STM32F429_PI7_FUNC_GPIO 0x8700 -#define STM32F429_PI7_FUNC_TIM8_CH3 0x8704 -#define STM32F429_PI7_FUNC_FMC_D29 0x870d -#define STM32F429_PI7_FUNC_DCMI_D7 0x870e -#define STM32F429_PI7_FUNC_LCD_B7 0x870f -#define STM32F429_PI7_FUNC_EVENTOUT 0x8710 -#define STM32F429_PI7_FUNC_ANALOG 0x8711 - -#define STM32F429_PI8_FUNC_GPIO 0x8800 -#define STM32F429_PI8_FUNC_EVENTOUT 0x8810 -#define STM32F429_PI8_FUNC_ANALOG 0x8811 - -#define STM32F429_PI9_FUNC_GPIO 0x8900 -#define STM32F429_PI9_FUNC_CAN1_RX 0x890a -#define STM32F429_PI9_FUNC_FMC_D30 0x890d -#define STM32F429_PI9_FUNC_LCD_VSYNC 0x890f -#define STM32F429_PI9_FUNC_EVENTOUT 0x8910 -#define STM32F429_PI9_FUNC_ANALOG 0x8911 - -#define STM32F429_PI10_FUNC_GPIO 0x8a00 -#define STM32F429_PI10_FUNC_ETH_MII_RX_ER 0x8a0c -#define STM32F429_PI10_FUNC_FMC_D31 0x8a0d -#define STM32F429_PI10_FUNC_LCD_HSYNC 0x8a0f -#define STM32F429_PI10_FUNC_EVENTOUT 0x8a10 -#define STM32F429_PI10_FUNC_ANALOG 0x8a11 - -#define STM32F429_PI11_FUNC_GPIO 0x8b00 -#define STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b -#define STM32F429_PI11_FUNC_EVENTOUT 0x8b10 -#define STM32F429_PI11_FUNC_ANALOG 0x8b11 - -#define STM32F429_PI12_FUNC_GPIO 0x8c00 -#define STM32F429_PI12_FUNC_LCD_HSYNC 0x8c0f -#define STM32F429_PI12_FUNC_EVENTOUT 0x8c10 -#define STM32F429_PI12_FUNC_ANALOG 0x8c11 - -#define STM32F429_PI13_FUNC_GPIO 0x8d00 -#define STM32F429_PI13_FUNC_LCD_VSYNC 0x8d0f -#define STM32F429_PI13_FUNC_EVENTOUT 0x8d10 -#define STM32F429_PI13_FUNC_ANALOG 0x8d11 - -#define STM32F429_PI14_FUNC_GPIO 0x8e00 -#define STM32F429_PI14_FUNC_LCD_CLK 0x8e0f -#define STM32F429_PI14_FUNC_EVENTOUT 0x8e10 -#define STM32F429_PI14_FUNC_ANALOG 0x8e11 - -#define STM32F429_PI15_FUNC_GPIO 0x8f00 -#define STM32F429_PI15_FUNC_LCD_R0 0x8f0f -#define STM32F429_PI15_FUNC_EVENTOUT 0x8f10 -#define STM32F429_PI15_FUNC_ANALOG 0x8f11 - - - -#define STM32F429_PJ0_FUNC_GPIO 0x9000 -#define STM32F429_PJ0_FUNC_LCD_R1 0x900f -#define STM32F429_PJ0_FUNC_EVENTOUT 0x9010 -#define STM32F429_PJ0_FUNC_ANALOG 0x9011 - -#define STM32F429_PJ1_FUNC_GPIO 0x9100 -#define STM32F429_PJ1_FUNC_LCD_R2 0x910f -#define STM32F429_PJ1_FUNC_EVENTOUT 0x9110 -#define STM32F429_PJ1_FUNC_ANALOG 0x9111 - -#define STM32F429_PJ2_FUNC_GPIO 0x9200 -#define STM32F429_PJ2_FUNC_LCD_R3 0x920f -#define STM32F429_PJ2_FUNC_EVENTOUT 0x9210 -#define STM32F429_PJ2_FUNC_ANALOG 0x9211 - -#define STM32F429_PJ3_FUNC_GPIO 0x9300 -#define STM32F429_PJ3_FUNC_LCD_R4 0x930f -#define STM32F429_PJ3_FUNC_EVENTOUT 0x9310 -#define STM32F429_PJ3_FUNC_ANALOG 0x9311 - -#define STM32F429_PJ4_FUNC_GPIO 0x9400 -#define STM32F429_PJ4_FUNC_LCD_R5 0x940f -#define STM32F429_PJ4_FUNC_EVENTOUT 0x9410 -#define STM32F429_PJ4_FUNC_ANALOG 0x9411 - -#define STM32F429_PJ5_FUNC_GPIO 0x9500 -#define STM32F429_PJ5_FUNC_LCD_R6 0x950f -#define STM32F429_PJ5_FUNC_EVENTOUT 0x9510 -#define STM32F429_PJ5_FUNC_ANALOG 0x9511 - -#define STM32F429_PJ6_FUNC_GPIO 0x9600 -#define STM32F429_PJ6_FUNC_LCD_R7 0x960f -#define STM32F429_PJ6_FUNC_EVENTOUT 0x9610 -#define STM32F429_PJ6_FUNC_ANALOG 0x9611 - -#define STM32F429_PJ7_FUNC_GPIO 0x9700 -#define STM32F429_PJ7_FUNC_LCD_G0 0x970f -#define STM32F429_PJ7_FUNC_EVENTOUT 0x9710 -#define STM32F429_PJ7_FUNC_ANALOG 0x9711 - -#define STM32F429_PJ8_FUNC_GPIO 0x9800 -#define STM32F429_PJ8_FUNC_LCD_G1 0x980f -#define STM32F429_PJ8_FUNC_EVENTOUT 0x9810 -#define STM32F429_PJ8_FUNC_ANALOG 0x9811 - -#define STM32F429_PJ9_FUNC_GPIO 0x9900 -#define STM32F429_PJ9_FUNC_LCD_G2 0x990f -#define STM32F429_PJ9_FUNC_EVENTOUT 0x9910 -#define STM32F429_PJ9_FUNC_ANALOG 0x9911 - -#define STM32F429_PJ10_FUNC_GPIO 0x9a00 -#define STM32F429_PJ10_FUNC_LCD_G3 0x9a0f -#define STM32F429_PJ10_FUNC_EVENTOUT 0x9a10 -#define STM32F429_PJ10_FUNC_ANALOG 0x9a11 - -#define STM32F429_PJ11_FUNC_GPIO 0x9b00 -#define STM32F429_PJ11_FUNC_LCD_G4 0x9b0f -#define STM32F429_PJ11_FUNC_EVENTOUT 0x9b10 -#define STM32F429_PJ11_FUNC_ANALOG 0x9b11 - -#define STM32F429_PJ12_FUNC_GPIO 0x9c00 -#define STM32F429_PJ12_FUNC_LCD_B0 0x9c0f -#define STM32F429_PJ12_FUNC_EVENTOUT 0x9c10 -#define STM32F429_PJ12_FUNC_ANALOG 0x9c11 - -#define STM32F429_PJ13_FUNC_GPIO 0x9d00 -#define STM32F429_PJ13_FUNC_LCD_B1 0x9d0f -#define STM32F429_PJ13_FUNC_EVENTOUT 0x9d10 -#define STM32F429_PJ13_FUNC_ANALOG 0x9d11 - -#define STM32F429_PJ14_FUNC_GPIO 0x9e00 -#define STM32F429_PJ14_FUNC_LCD_B2 0x9e0f -#define STM32F429_PJ14_FUNC_EVENTOUT 0x9e10 -#define STM32F429_PJ14_FUNC_ANALOG 0x9e11 - -#define STM32F429_PJ15_FUNC_GPIO 0x9f00 -#define STM32F429_PJ15_FUNC_LCD_B3 0x9f0f -#define STM32F429_PJ15_FUNC_EVENTOUT 0x9f10 -#define STM32F429_PJ15_FUNC_ANALOG 0x9f11 - - - -#define STM32F429_PK0_FUNC_GPIO 0xa000 -#define STM32F429_PK0_FUNC_LCD_G5 0xa00f -#define STM32F429_PK0_FUNC_EVENTOUT 0xa010 -#define STM32F429_PK0_FUNC_ANALOG 0xa011 - -#define STM32F429_PK1_FUNC_GPIO 0xa100 -#define STM32F429_PK1_FUNC_LCD_G6 0xa10f -#define STM32F429_PK1_FUNC_EVENTOUT 0xa110 -#define STM32F429_PK1_FUNC_ANALOG 0xa111 - -#define STM32F429_PK2_FUNC_GPIO 0xa200 -#define STM32F429_PK2_FUNC_LCD_G7 0xa20f -#define STM32F429_PK2_FUNC_EVENTOUT 0xa210 -#define STM32F429_PK2_FUNC_ANALOG 0xa211 - -#define STM32F429_PK3_FUNC_GPIO 0xa300 -#define STM32F429_PK3_FUNC_LCD_B4 0xa30f -#define STM32F429_PK3_FUNC_EVENTOUT 0xa310 -#define STM32F429_PK3_FUNC_ANALOG 0xa311 - -#define STM32F429_PK4_FUNC_GPIO 0xa400 -#define STM32F429_PK4_FUNC_LCD_B5 0xa40f -#define STM32F429_PK4_FUNC_EVENTOUT 0xa410 -#define STM32F429_PK4_FUNC_ANALOG 0xa411 - -#define STM32F429_PK5_FUNC_GPIO 0xa500 -#define STM32F429_PK5_FUNC_LCD_B6 0xa50f -#define STM32F429_PK5_FUNC_EVENTOUT 0xa510 -#define STM32F429_PK5_FUNC_ANALOG 0xa511 - -#define STM32F429_PK6_FUNC_GPIO 0xa600 -#define STM32F429_PK6_FUNC_LCD_B7 0xa60f -#define STM32F429_PK6_FUNC_EVENTOUT 0xa610 -#define STM32F429_PK6_FUNC_ANALOG 0xa611 - -#define STM32F429_PK7_FUNC_GPIO 0xa700 -#define STM32F429_PK7_FUNC_LCD_DE 0xa70f -#define STM32F429_PK7_FUNC_EVENTOUT 0xa710 -#define STM32F429_PK7_FUNC_ANALOG 0xa711 - -#endif /* _DT_BINDINGS_STM32F429_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h b/include/dt-bindings/pinctrl/stm32f746-pinfunc.h deleted file mode 100644 index 4c28f8f41621..000000000000 --- a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h +++ /dev/null @@ -1,1325 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_STM32F746_PINFUNC_H -#define _DT_BINDINGS_STM32F746_PINFUNC_H - -#define STM32F746_PA0_FUNC_GPIO 0x0 -#define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 -#define STM32F746_PA0_FUNC_TIM5_CH1 0x3 -#define STM32F746_PA0_FUNC_TIM8_ETR 0x4 -#define STM32F746_PA0_FUNC_USART2_CTS 0x8 -#define STM32F746_PA0_FUNC_UART4_TX 0x9 -#define STM32F746_PA0_FUNC_SAI2_SD_B 0xb -#define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc -#define STM32F746_PA0_FUNC_EVENTOUT 0x10 -#define STM32F746_PA0_FUNC_ANALOG 0x11 - -#define STM32F746_PA1_FUNC_GPIO 0x100 -#define STM32F746_PA1_FUNC_TIM2_CH2 0x102 -#define STM32F746_PA1_FUNC_TIM5_CH2 0x103 -#define STM32F746_PA1_FUNC_USART2_RTS 0x108 -#define STM32F746_PA1_FUNC_UART4_RX 0x109 -#define STM32F746_PA1_FUNC_QUADSPI_BK1_IO3 0x10a -#define STM32F746_PA1_FUNC_SAI2_MCLK_B 0x10b -#define STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c -#define STM32F746_PA1_FUNC_LCD_R2 0x10f -#define STM32F746_PA1_FUNC_EVENTOUT 0x110 -#define STM32F746_PA1_FUNC_ANALOG 0x111 - -#define STM32F746_PA2_FUNC_GPIO 0x200 -#define STM32F746_PA2_FUNC_TIM2_CH3 0x202 -#define STM32F746_PA2_FUNC_TIM5_CH3 0x203 -#define STM32F746_PA2_FUNC_TIM9_CH1 0x204 -#define STM32F746_PA2_FUNC_USART2_TX 0x208 -#define STM32F746_PA2_FUNC_SAI2_SCK_B 0x209 -#define STM32F746_PA2_FUNC_ETH_MDIO 0x20c -#define STM32F746_PA2_FUNC_LCD_R1 0x20f -#define STM32F746_PA2_FUNC_EVENTOUT 0x210 -#define STM32F746_PA2_FUNC_ANALOG 0x211 - -#define STM32F746_PA3_FUNC_GPIO 0x300 -#define STM32F746_PA3_FUNC_TIM2_CH4 0x302 -#define STM32F746_PA3_FUNC_TIM5_CH4 0x303 -#define STM32F746_PA3_FUNC_TIM9_CH2 0x304 -#define STM32F746_PA3_FUNC_USART2_RX 0x308 -#define STM32F746_PA3_FUNC_OTG_HS_ULPI_D0 0x30b -#define STM32F746_PA3_FUNC_ETH_MII_COL 0x30c -#define STM32F746_PA3_FUNC_LCD_B5 0x30f -#define STM32F746_PA3_FUNC_EVENTOUT 0x310 -#define STM32F746_PA3_FUNC_ANALOG 0x311 - -#define STM32F746_PA4_FUNC_GPIO 0x400 -#define STM32F746_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406 -#define STM32F746_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 -#define STM32F746_PA4_FUNC_USART2_CK 0x408 -#define STM32F746_PA4_FUNC_OTG_HS_SOF 0x40d -#define STM32F746_PA4_FUNC_DCMI_HSYNC 0x40e -#define STM32F746_PA4_FUNC_LCD_VSYNC 0x40f -#define STM32F746_PA4_FUNC_EVENTOUT 0x410 -#define STM32F746_PA4_FUNC_ANALOG 0x411 - -#define STM32F746_PA5_FUNC_GPIO 0x500 -#define STM32F746_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 -#define STM32F746_PA5_FUNC_TIM8_CH1N 0x504 -#define STM32F746_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506 -#define STM32F746_PA5_FUNC_OTG_HS_ULPI_CK 0x50b -#define STM32F746_PA5_FUNC_LCD_R4 0x50f -#define STM32F746_PA5_FUNC_EVENTOUT 0x510 -#define STM32F746_PA5_FUNC_ANALOG 0x511 - -#define STM32F746_PA6_FUNC_GPIO 0x600 -#define STM32F746_PA6_FUNC_TIM1_BKIN 0x602 -#define STM32F746_PA6_FUNC_TIM3_CH1 0x603 -#define STM32F746_PA6_FUNC_TIM8_BKIN 0x604 -#define STM32F746_PA6_FUNC_SPI1_MISO 0x606 -#define STM32F746_PA6_FUNC_TIM13_CH1 0x60a -#define STM32F746_PA6_FUNC_DCMI_PIXCLK 0x60e -#define STM32F746_PA6_FUNC_LCD_G2 0x60f -#define STM32F746_PA6_FUNC_EVENTOUT 0x610 -#define STM32F746_PA6_FUNC_ANALOG 0x611 - -#define STM32F746_PA7_FUNC_GPIO 0x700 -#define STM32F746_PA7_FUNC_TIM1_CH1N 0x702 -#define STM32F746_PA7_FUNC_TIM3_CH2 0x703 -#define STM32F746_PA7_FUNC_TIM8_CH1N 0x704 -#define STM32F746_PA7_FUNC_SPI1_MOSI_I2S1_SD 0x706 -#define STM32F746_PA7_FUNC_TIM14_CH1 0x70a -#define STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c -#define STM32F746_PA7_FUNC_FMC_SDNWE 0x70d -#define STM32F746_PA7_FUNC_EVENTOUT 0x710 -#define STM32F746_PA7_FUNC_ANALOG 0x711 - -#define STM32F746_PA8_FUNC_GPIO 0x800 -#define STM32F746_PA8_FUNC_MCO1 0x801 -#define STM32F746_PA8_FUNC_TIM1_CH1 0x802 -#define STM32F746_PA8_FUNC_TIM8_BKIN2 0x804 -#define STM32F746_PA8_FUNC_I2C3_SCL 0x805 -#define STM32F746_PA8_FUNC_USART1_CK 0x808 -#define STM32F746_PA8_FUNC_OTG_FS_SOF 0x80b -#define STM32F746_PA8_FUNC_LCD_R6 0x80f -#define STM32F746_PA8_FUNC_EVENTOUT 0x810 -#define STM32F746_PA8_FUNC_ANALOG 0x811 - -#define STM32F746_PA9_FUNC_GPIO 0x900 -#define STM32F746_PA9_FUNC_TIM1_CH2 0x902 -#define STM32F746_PA9_FUNC_I2C3_SMBA 0x905 -#define STM32F746_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906 -#define STM32F746_PA9_FUNC_USART1_TX 0x908 -#define STM32F746_PA9_FUNC_DCMI_D0 0x90e -#define STM32F746_PA9_FUNC_EVENTOUT 0x910 -#define STM32F746_PA9_FUNC_ANALOG 0x911 - -#define STM32F746_PA10_FUNC_GPIO 0xa00 -#define STM32F746_PA10_FUNC_TIM1_CH3 0xa02 -#define STM32F746_PA10_FUNC_USART1_RX 0xa08 -#define STM32F746_PA10_FUNC_OTG_FS_ID 0xa0b -#define STM32F746_PA10_FUNC_DCMI_D1 0xa0e -#define STM32F746_PA10_FUNC_EVENTOUT 0xa10 -#define STM32F746_PA10_FUNC_ANALOG 0xa11 - -#define STM32F746_PA11_FUNC_GPIO 0xb00 -#define STM32F746_PA11_FUNC_TIM1_CH4 0xb02 -#define STM32F746_PA11_FUNC_USART1_CTS 0xb08 -#define STM32F746_PA11_FUNC_CAN1_RX 0xb0a -#define STM32F746_PA11_FUNC_OTG_FS_DM 0xb0b -#define STM32F746_PA11_FUNC_LCD_R4 0xb0f -#define STM32F746_PA11_FUNC_EVENTOUT 0xb10 -#define STM32F746_PA11_FUNC_ANALOG 0xb11 - -#define STM32F746_PA12_FUNC_GPIO 0xc00 -#define STM32F746_PA12_FUNC_TIM1_ETR 0xc02 -#define STM32F746_PA12_FUNC_USART1_RTS 0xc08 -#define STM32F746_PA12_FUNC_SAI2_FS_B 0xc09 -#define STM32F746_PA12_FUNC_CAN1_TX 0xc0a -#define STM32F746_PA12_FUNC_OTG_FS_DP 0xc0b -#define STM32F746_PA12_FUNC_LCD_R5 0xc0f -#define STM32F746_PA12_FUNC_EVENTOUT 0xc10 -#define STM32F746_PA12_FUNC_ANALOG 0xc11 - -#define STM32F746_PA13_FUNC_GPIO 0xd00 -#define STM32F746_PA13_FUNC_JTMS_SWDIO 0xd01 -#define STM32F746_PA13_FUNC_EVENTOUT 0xd10 -#define STM32F746_PA13_FUNC_ANALOG 0xd11 - -#define STM32F746_PA14_FUNC_GPIO 0xe00 -#define STM32F746_PA14_FUNC_JTCK_SWCLK 0xe01 -#define STM32F746_PA14_FUNC_EVENTOUT 0xe10 -#define STM32F746_PA14_FUNC_ANALOG 0xe11 - -#define STM32F746_PA15_FUNC_GPIO 0xf00 -#define STM32F746_PA15_FUNC_JTDI 0xf01 -#define STM32F746_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 -#define STM32F746_PA15_FUNC_HDMI_CEC 0xf05 -#define STM32F746_PA15_FUNC_SPI1_NSS_I2S1_WS 0xf06 -#define STM32F746_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 -#define STM32F746_PA15_FUNC_UART4_RTS 0xf09 -#define STM32F746_PA15_FUNC_EVENTOUT 0xf10 -#define STM32F746_PA15_FUNC_ANALOG 0xf11 - - -#define STM32F746_PB0_FUNC_GPIO 0x1000 -#define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002 -#define STM32F746_PB0_FUNC_TIM3_CH3 0x1003 -#define STM32F746_PB0_FUNC_TIM8_CH2N 0x1004 -#define STM32F746_PB0_FUNC_UART4_CTS 0x1009 -#define STM32F746_PB0_FUNC_LCD_R3 0x100a -#define STM32F746_PB0_FUNC_OTG_HS_ULPI_D1 0x100b -#define STM32F746_PB0_FUNC_ETH_MII_RXD2 0x100c -#define STM32F746_PB0_FUNC_EVENTOUT 0x1010 -#define STM32F746_PB0_FUNC_ANALOG 0x1011 - -#define STM32F746_PB1_FUNC_GPIO 0x1100 -#define STM32F746_PB1_FUNC_TIM1_CH3N 0x1102 -#define STM32F746_PB1_FUNC_TIM3_CH4 0x1103 -#define STM32F746_PB1_FUNC_TIM8_CH3N 0x1104 -#define STM32F746_PB1_FUNC_LCD_R6 0x110a -#define STM32F746_PB1_FUNC_OTG_HS_ULPI_D2 0x110b -#define STM32F746_PB1_FUNC_ETH_MII_RXD3 0x110c -#define STM32F746_PB1_FUNC_EVENTOUT 0x1110 -#define STM32F746_PB1_FUNC_ANALOG 0x1111 - -#define STM32F746_PB2_FUNC_GPIO 0x1200 -#define STM32F746_PB2_FUNC_SAI1_SD_A 0x1207 -#define STM32F746_PB2_FUNC_SPI3_MOSI_I2S3_SD 0x1208 -#define STM32F746_PB2_FUNC_QUADSPI_CLK 0x120a -#define STM32F746_PB2_FUNC_EVENTOUT 0x1210 -#define STM32F746_PB2_FUNC_ANALOG 0x1211 - -#define STM32F746_PB3_FUNC_GPIO 0x1300 -#define STM32F746_PB3_FUNC_JTDO_TRACESWO 0x1301 -#define STM32F746_PB3_FUNC_TIM2_CH2 0x1302 -#define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306 -#define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 -#define STM32F746_PB3_FUNC_EVENTOUT 0x1310 -#define STM32F746_PB3_FUNC_ANALOG 0x1311 - -#define STM32F746_PB4_FUNC_GPIO 0x1400 -#define STM32F746_PB4_FUNC_NJTRST 0x1401 -#define STM32F746_PB4_FUNC_TIM3_CH1 0x1403 -#define STM32F746_PB4_FUNC_SPI1_MISO 0x1406 -#define STM32F746_PB4_FUNC_SPI3_MISO 0x1407 -#define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408 -#define STM32F746_PB4_FUNC_EVENTOUT 0x1410 -#define STM32F746_PB4_FUNC_ANALOG 0x1411 - -#define STM32F746_PB5_FUNC_GPIO 0x1500 -#define STM32F746_PB5_FUNC_TIM3_CH2 0x1503 -#define STM32F746_PB5_FUNC_I2C1_SMBA 0x1505 -#define STM32F746_PB5_FUNC_SPI1_MOSI_I2S1_SD 0x1506 -#define STM32F746_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507 -#define STM32F746_PB5_FUNC_CAN2_RX 0x150a -#define STM32F746_PB5_FUNC_OTG_HS_ULPI_D7 0x150b -#define STM32F746_PB5_FUNC_ETH_PPS_OUT 0x150c -#define STM32F746_PB5_FUNC_FMC_SDCKE1 0x150d -#define STM32F746_PB5_FUNC_DCMI_D10 0x150e -#define STM32F746_PB5_FUNC_EVENTOUT 0x1510 -#define STM32F746_PB5_FUNC_ANALOG 0x1511 - -#define STM32F746_PB6_FUNC_GPIO 0x1600 -#define STM32F746_PB6_FUNC_TIM4_CH1 0x1603 -#define STM32F746_PB6_FUNC_HDMI_CEC 0x1604 -#define STM32F746_PB6_FUNC_I2C1_SCL 0x1605 -#define STM32F746_PB6_FUNC_USART1_TX 0x1608 -#define STM32F746_PB6_FUNC_CAN2_TX 0x160a -#define STM32F746_PB6_FUNC_QUADSPI_BK1_NCS 0x160b -#define STM32F746_PB6_FUNC_FMC_SDNE1 0x160d -#define STM32F746_PB6_FUNC_DCMI_D5 0x160e -#define STM32F746_PB6_FUNC_EVENTOUT 0x1610 -#define STM32F746_PB6_FUNC_ANALOG 0x1611 - -#define STM32F746_PB7_FUNC_GPIO 0x1700 -#define STM32F746_PB7_FUNC_TIM4_CH2 0x1703 -#define STM32F746_PB7_FUNC_I2C1_SDA 0x1705 -#define STM32F746_PB7_FUNC_USART1_RX 0x1708 -#define STM32F746_PB7_FUNC_FMC_NL 0x170d -#define STM32F746_PB7_FUNC_DCMI_VSYNC 0x170e -#define STM32F746_PB7_FUNC_EVENTOUT 0x1710 -#define STM32F746_PB7_FUNC_ANALOG 0x1711 - -#define STM32F746_PB8_FUNC_GPIO 0x1800 -#define STM32F746_PB8_FUNC_TIM4_CH3 0x1803 -#define STM32F746_PB8_FUNC_TIM10_CH1 0x1804 -#define STM32F746_PB8_FUNC_I2C1_SCL 0x1805 -#define STM32F746_PB8_FUNC_CAN1_RX 0x180a -#define STM32F746_PB8_FUNC_ETH_MII_TXD3 0x180c -#define STM32F746_PB8_FUNC_SDMMC1_D4 0x180d -#define STM32F746_PB8_FUNC_DCMI_D6 0x180e -#define STM32F746_PB8_FUNC_LCD_B6 0x180f -#define STM32F746_PB8_FUNC_EVENTOUT 0x1810 -#define STM32F746_PB8_FUNC_ANALOG 0x1811 - -#define STM32F746_PB9_FUNC_GPIO 0x1900 -#define STM32F746_PB9_FUNC_TIM4_CH4 0x1903 -#define STM32F746_PB9_FUNC_TIM11_CH1 0x1904 -#define STM32F746_PB9_FUNC_I2C1_SDA 0x1905 -#define STM32F746_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 -#define STM32F746_PB9_FUNC_CAN1_TX 0x190a -#define STM32F746_PB9_FUNC_SDMMC1_D5 0x190d -#define STM32F746_PB9_FUNC_DCMI_D7 0x190e -#define STM32F746_PB9_FUNC_LCD_B7 0x190f -#define STM32F746_PB9_FUNC_EVENTOUT 0x1910 -#define STM32F746_PB9_FUNC_ANALOG 0x1911 - -#define STM32F746_PB10_FUNC_GPIO 0x1a00 -#define STM32F746_PB10_FUNC_TIM2_CH3 0x1a02 -#define STM32F746_PB10_FUNC_I2C2_SCL 0x1a05 -#define STM32F746_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 -#define STM32F746_PB10_FUNC_USART3_TX 0x1a08 -#define STM32F746_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b -#define STM32F746_PB10_FUNC_ETH_MII_RX_ER 0x1a0c -#define STM32F746_PB10_FUNC_LCD_G4 0x1a0f -#define STM32F746_PB10_FUNC_EVENTOUT 0x1a10 -#define STM32F746_PB10_FUNC_ANALOG 0x1a11 - -#define STM32F746_PB11_FUNC_GPIO 0x1b00 -#define STM32F746_PB11_FUNC_TIM2_CH4 0x1b02 -#define STM32F746_PB11_FUNC_I2C2_SDA 0x1b05 -#define STM32F746_PB11_FUNC_USART3_RX 0x1b08 -#define STM32F746_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b -#define STM32F746_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c -#define STM32F746_PB11_FUNC_LCD_G5 0x1b0f -#define STM32F746_PB11_FUNC_EVENTOUT 0x1b10 -#define STM32F746_PB11_FUNC_ANALOG 0x1b11 - -#define STM32F746_PB12_FUNC_GPIO 0x1c00 -#define STM32F746_PB12_FUNC_TIM1_BKIN 0x1c02 -#define STM32F746_PB12_FUNC_I2C2_SMBA 0x1c05 -#define STM32F746_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 -#define STM32F746_PB12_FUNC_USART3_CK 0x1c08 -#define STM32F746_PB12_FUNC_CAN2_RX 0x1c0a -#define STM32F746_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b -#define STM32F746_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c -#define STM32F746_PB12_FUNC_OTG_HS_ID 0x1c0d -#define STM32F746_PB12_FUNC_EVENTOUT 0x1c10 -#define STM32F746_PB12_FUNC_ANALOG 0x1c11 - -#define STM32F746_PB13_FUNC_GPIO 0x1d00 -#define STM32F746_PB13_FUNC_TIM1_CH1N 0x1d02 -#define STM32F746_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 -#define STM32F746_PB13_FUNC_USART3_CTS 0x1d08 -#define STM32F746_PB13_FUNC_CAN2_TX 0x1d0a -#define STM32F746_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b -#define STM32F746_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c -#define STM32F746_PB13_FUNC_EVENTOUT 0x1d10 -#define STM32F746_PB13_FUNC_ANALOG 0x1d11 - -#define STM32F746_PB14_FUNC_GPIO 0x1e00 -#define STM32F746_PB14_FUNC_TIM1_CH2N 0x1e02 -#define STM32F746_PB14_FUNC_TIM8_CH2N 0x1e04 -#define STM32F746_PB14_FUNC_SPI2_MISO 0x1e06 -#define STM32F746_PB14_FUNC_USART3_RTS 0x1e08 -#define STM32F746_PB14_FUNC_TIM12_CH1 0x1e0a -#define STM32F746_PB14_FUNC_OTG_HS_DM 0x1e0d -#define STM32F746_PB14_FUNC_EVENTOUT 0x1e10 -#define STM32F746_PB14_FUNC_ANALOG 0x1e11 - -#define STM32F746_PB15_FUNC_GPIO 0x1f00 -#define STM32F746_PB15_FUNC_RTC_REFIN 0x1f01 -#define STM32F746_PB15_FUNC_TIM1_CH3N 0x1f02 -#define STM32F746_PB15_FUNC_TIM8_CH3N 0x1f04 -#define STM32F746_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06 -#define STM32F746_PB15_FUNC_TIM12_CH2 0x1f0a -#define STM32F746_PB15_FUNC_OTG_HS_DP 0x1f0d -#define STM32F746_PB15_FUNC_EVENTOUT 0x1f10 -#define STM32F746_PB15_FUNC_ANALOG 0x1f11 - - -#define STM32F746_PC0_FUNC_GPIO 0x2000 -#define STM32F746_PC0_FUNC_SAI2_FS_B 0x2009 -#define STM32F746_PC0_FUNC_OTG_HS_ULPI_STP 0x200b -#define STM32F746_PC0_FUNC_FMC_SDNWE 0x200d -#define STM32F746_PC0_FUNC_LCD_R5 0x200f -#define STM32F746_PC0_FUNC_EVENTOUT 0x2010 -#define STM32F746_PC0_FUNC_ANALOG 0x2011 - -#define STM32F746_PC1_FUNC_GPIO 0x2100 -#define STM32F746_PC1_FUNC_TRACED0 0x2101 -#define STM32F746_PC1_FUNC_SPI2_MOSI_I2S2_SD 0x2106 -#define STM32F746_PC1_FUNC_SAI1_SD_A 0x2107 -#define STM32F746_PC1_FUNC_ETH_MDC 0x210c -#define STM32F746_PC1_FUNC_EVENTOUT 0x2110 -#define STM32F746_PC1_FUNC_ANALOG 0x2111 - -#define STM32F746_PC2_FUNC_GPIO 0x2200 -#define STM32F746_PC2_FUNC_SPI2_MISO 0x2206 -#define STM32F746_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b -#define STM32F746_PC2_FUNC_ETH_MII_TXD2 0x220c -#define STM32F746_PC2_FUNC_FMC_SDNE0 0x220d -#define STM32F746_PC2_FUNC_EVENTOUT 0x2210 -#define STM32F746_PC2_FUNC_ANALOG 0x2211 - -#define STM32F746_PC3_FUNC_GPIO 0x2300 -#define STM32F746_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306 -#define STM32F746_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b -#define STM32F746_PC3_FUNC_ETH_MII_TX_CLK 0x230c -#define STM32F746_PC3_FUNC_FMC_SDCKE0 0x230d -#define STM32F746_PC3_FUNC_EVENTOUT 0x2310 -#define STM32F746_PC3_FUNC_ANALOG 0x2311 - -#define STM32F746_PC4_FUNC_GPIO 0x2400 -#define STM32F746_PC4_FUNC_I2S1_MCK 0x2406 -#define STM32F746_PC4_FUNC_SPDIFRX_IN2 0x2409 -#define STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c -#define STM32F746_PC4_FUNC_FMC_SDNE0 0x240d -#define STM32F746_PC4_FUNC_EVENTOUT 0x2410 -#define STM32F746_PC4_FUNC_ANALOG 0x2411 - -#define STM32F746_PC5_FUNC_GPIO 0x2500 -#define STM32F746_PC5_FUNC_SPDIFRX_IN3 0x2509 -#define STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c -#define STM32F746_PC5_FUNC_FMC_SDCKE0 0x250d -#define STM32F746_PC5_FUNC_EVENTOUT 0x2510 -#define STM32F746_PC5_FUNC_ANALOG 0x2511 - -#define STM32F746_PC6_FUNC_GPIO 0x2600 -#define STM32F746_PC6_FUNC_TIM3_CH1 0x2603 -#define STM32F746_PC6_FUNC_TIM8_CH1 0x2604 -#define STM32F746_PC6_FUNC_I2S2_MCK 0x2606 -#define STM32F746_PC6_FUNC_USART6_TX 0x2609 -#define STM32F746_PC6_FUNC_SDMMC1_D6 0x260d -#define STM32F746_PC6_FUNC_DCMI_D0 0x260e -#define STM32F746_PC6_FUNC_LCD_HSYNC 0x260f -#define STM32F746_PC6_FUNC_EVENTOUT 0x2610 -#define STM32F746_PC6_FUNC_ANALOG 0x2611 - -#define STM32F746_PC7_FUNC_GPIO 0x2700 -#define STM32F746_PC7_FUNC_TIM3_CH2 0x2703 -#define STM32F746_PC7_FUNC_TIM8_CH2 0x2704 -#define STM32F746_PC7_FUNC_I2S3_MCK 0x2707 -#define STM32F746_PC7_FUNC_USART6_RX 0x2709 -#define STM32F746_PC7_FUNC_SDMMC1_D7 0x270d -#define STM32F746_PC7_FUNC_DCMI_D1 0x270e -#define STM32F746_PC7_FUNC_LCD_G6 0x270f -#define STM32F746_PC7_FUNC_EVENTOUT 0x2710 -#define STM32F746_PC7_FUNC_ANALOG 0x2711 - -#define STM32F746_PC8_FUNC_GPIO 0x2800 -#define STM32F746_PC8_FUNC_TRACED1 0x2801 -#define STM32F746_PC8_FUNC_TIM3_CH3 0x2803 -#define STM32F746_PC8_FUNC_TIM8_CH3 0x2804 -#define STM32F746_PC8_FUNC_UART5_RTS 0x2808 -#define STM32F746_PC8_FUNC_USART6_CK 0x2809 -#define STM32F746_PC8_FUNC_SDMMC1_D0 0x280d -#define STM32F746_PC8_FUNC_DCMI_D2 0x280e -#define STM32F746_PC8_FUNC_EVENTOUT 0x2810 -#define STM32F746_PC8_FUNC_ANALOG 0x2811 - -#define STM32F746_PC9_FUNC_GPIO 0x2900 -#define STM32F746_PC9_FUNC_MCO2 0x2901 -#define STM32F746_PC9_FUNC_TIM3_CH4 0x2903 -#define STM32F746_PC9_FUNC_TIM8_CH4 0x2904 -#define STM32F746_PC9_FUNC_I2C3_SDA 0x2905 -#define STM32F746_PC9_FUNC_I2S_CKIN 0x2906 -#define STM32F746_PC9_FUNC_UART5_CTS 0x2908 -#define STM32F746_PC9_FUNC_QUADSPI_BK1_IO0 0x290a -#define STM32F746_PC9_FUNC_SDMMC1_D1 0x290d -#define STM32F746_PC9_FUNC_DCMI_D3 0x290e -#define STM32F746_PC9_FUNC_EVENTOUT 0x2910 -#define STM32F746_PC9_FUNC_ANALOG 0x2911 - -#define STM32F746_PC10_FUNC_GPIO 0x2a00 -#define STM32F746_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 -#define STM32F746_PC10_FUNC_USART3_TX 0x2a08 -#define STM32F746_PC10_FUNC_UART4_TX 0x2a09 -#define STM32F746_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a -#define STM32F746_PC10_FUNC_SDMMC1_D2 0x2a0d -#define STM32F746_PC10_FUNC_DCMI_D8 0x2a0e -#define STM32F746_PC10_FUNC_LCD_R2 0x2a0f -#define STM32F746_PC10_FUNC_EVENTOUT 0x2a10 -#define STM32F746_PC10_FUNC_ANALOG 0x2a11 - -#define STM32F746_PC11_FUNC_GPIO 0x2b00 -#define STM32F746_PC11_FUNC_SPI3_MISO 0x2b07 -#define STM32F746_PC11_FUNC_USART3_RX 0x2b08 -#define STM32F746_PC11_FUNC_UART4_RX 0x2b09 -#define STM32F746_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a -#define STM32F746_PC11_FUNC_SDMMC1_D3 0x2b0d -#define STM32F746_PC11_FUNC_DCMI_D4 0x2b0e -#define STM32F746_PC11_FUNC_EVENTOUT 0x2b10 -#define STM32F746_PC11_FUNC_ANALOG 0x2b11 - -#define STM32F746_PC12_FUNC_GPIO 0x2c00 -#define STM32F746_PC12_FUNC_TRACED3 0x2c01 -#define STM32F746_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07 -#define STM32F746_PC12_FUNC_USART3_CK 0x2c08 -#define STM32F746_PC12_FUNC_UART5_TX 0x2c09 -#define STM32F746_PC12_FUNC_SDMMC1_CK 0x2c0d -#define STM32F746_PC12_FUNC_DCMI_D9 0x2c0e -#define STM32F746_PC12_FUNC_EVENTOUT 0x2c10 -#define STM32F746_PC12_FUNC_ANALOG 0x2c11 - -#define STM32F746_PC13_FUNC_GPIO 0x2d00 -#define STM32F746_PC13_FUNC_EVENTOUT 0x2d10 -#define STM32F746_PC13_FUNC_ANALOG 0x2d11 - -#define STM32F746_PC14_FUNC_GPIO 0x2e00 -#define STM32F746_PC14_FUNC_EVENTOUT 0x2e10 -#define STM32F746_PC14_FUNC_ANALOG 0x2e11 - -#define STM32F746_PC15_FUNC_GPIO 0x2f00 -#define STM32F746_PC15_FUNC_EVENTOUT 0x2f10 -#define STM32F746_PC15_FUNC_ANALOG 0x2f11 - - -#define STM32F746_PD0_FUNC_GPIO 0x3000 -#define STM32F746_PD0_FUNC_CAN1_RX 0x300a -#define STM32F746_PD0_FUNC_FMC_D2 0x300d -#define STM32F746_PD0_FUNC_EVENTOUT 0x3010 -#define STM32F746_PD0_FUNC_ANALOG 0x3011 - -#define STM32F746_PD1_FUNC_GPIO 0x3100 -#define STM32F746_PD1_FUNC_CAN1_TX 0x310a -#define STM32F746_PD1_FUNC_FMC_D3 0x310d -#define STM32F746_PD1_FUNC_EVENTOUT 0x3110 -#define STM32F746_PD1_FUNC_ANALOG 0x3111 - -#define STM32F746_PD2_FUNC_GPIO 0x3200 -#define STM32F746_PD2_FUNC_TRACED2 0x3201 -#define STM32F746_PD2_FUNC_TIM3_ETR 0x3203 -#define STM32F746_PD2_FUNC_UART5_RX 0x3209 -#define STM32F746_PD2_FUNC_SDMMC1_CMD 0x320d -#define STM32F746_PD2_FUNC_DCMI_D11 0x320e -#define STM32F746_PD2_FUNC_EVENTOUT 0x3210 -#define STM32F746_PD2_FUNC_ANALOG 0x3211 - -#define STM32F746_PD3_FUNC_GPIO 0x3300 -#define STM32F746_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 -#define STM32F746_PD3_FUNC_USART2_CTS 0x3308 -#define STM32F746_PD3_FUNC_FMC_CLK 0x330d -#define STM32F746_PD3_FUNC_DCMI_D5 0x330e -#define STM32F746_PD3_FUNC_LCD_G7 0x330f -#define STM32F746_PD3_FUNC_EVENTOUT 0x3310 -#define STM32F746_PD3_FUNC_ANALOG 0x3311 - -#define STM32F746_PD4_FUNC_GPIO 0x3400 -#define STM32F746_PD4_FUNC_USART2_RTS 0x3408 -#define STM32F746_PD4_FUNC_FMC_NOE 0x340d -#define STM32F746_PD4_FUNC_EVENTOUT 0x3410 -#define STM32F746_PD4_FUNC_ANALOG 0x3411 - -#define STM32F746_PD5_FUNC_GPIO 0x3500 -#define STM32F746_PD5_FUNC_USART2_TX 0x3508 -#define STM32F746_PD5_FUNC_FMC_NWE 0x350d -#define STM32F746_PD5_FUNC_EVENTOUT 0x3510 -#define STM32F746_PD5_FUNC_ANALOG 0x3511 - -#define STM32F746_PD6_FUNC_GPIO 0x3600 -#define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606 -#define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607 -#define STM32F746_PD6_FUNC_USART2_RX 0x3608 -#define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d -#define STM32F746_PD6_FUNC_DCMI_D10 0x360e -#define STM32F746_PD6_FUNC_LCD_B2 0x360f -#define STM32F746_PD6_FUNC_EVENTOUT 0x3610 -#define STM32F746_PD6_FUNC_ANALOG 0x3611 - -#define STM32F746_PD7_FUNC_GPIO 0x3700 -#define STM32F746_PD7_FUNC_USART2_CK 0x3708 -#define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709 -#define STM32F746_PD7_FUNC_FMC_NE1 0x370d -#define STM32F746_PD7_FUNC_EVENTOUT 0x3710 -#define STM32F746_PD7_FUNC_ANALOG 0x3711 - -#define STM32F746_PD8_FUNC_GPIO 0x3800 -#define STM32F746_PD8_FUNC_USART3_TX 0x3808 -#define STM32F746_PD8_FUNC_SPDIFRX_IN1 0x3809 -#define STM32F746_PD8_FUNC_FMC_D13 0x380d -#define STM32F746_PD8_FUNC_EVENTOUT 0x3810 -#define STM32F746_PD8_FUNC_ANALOG 0x3811 - -#define STM32F746_PD9_FUNC_GPIO 0x3900 -#define STM32F746_PD9_FUNC_USART3_RX 0x3908 -#define STM32F746_PD9_FUNC_FMC_D14 0x390d -#define STM32F746_PD9_FUNC_EVENTOUT 0x3910 -#define STM32F746_PD9_FUNC_ANALOG 0x3911 - -#define STM32F746_PD10_FUNC_GPIO 0x3a00 -#define STM32F746_PD10_FUNC_USART3_CK 0x3a08 -#define STM32F746_PD10_FUNC_FMC_D15 0x3a0d -#define STM32F746_PD10_FUNC_LCD_B3 0x3a0f -#define STM32F746_PD10_FUNC_EVENTOUT 0x3a10 -#define STM32F746_PD10_FUNC_ANALOG 0x3a11 - -#define STM32F746_PD11_FUNC_GPIO 0x3b00 -#define STM32F746_PD11_FUNC_I2C4_SMBA 0x3b05 -#define STM32F746_PD11_FUNC_USART3_CTS 0x3b08 -#define STM32F746_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a -#define STM32F746_PD11_FUNC_SAI2_SD_A 0x3b0b -#define STM32F746_PD11_FUNC_FMC_A16_FMC_CLE 0x3b0d -#define STM32F746_PD11_FUNC_EVENTOUT 0x3b10 -#define STM32F746_PD11_FUNC_ANALOG 0x3b11 - -#define STM32F746_PD12_FUNC_GPIO 0x3c00 -#define STM32F746_PD12_FUNC_TIM4_CH1 0x3c03 -#define STM32F746_PD12_FUNC_LPTIM1_IN1 0x3c04 -#define STM32F746_PD12_FUNC_I2C4_SCL 0x3c05 -#define STM32F746_PD12_FUNC_USART3_RTS 0x3c08 -#define STM32F746_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a -#define STM32F746_PD12_FUNC_SAI2_FS_A 0x3c0b -#define STM32F746_PD12_FUNC_FMC_A17_FMC_ALE 0x3c0d -#define STM32F746_PD12_FUNC_EVENTOUT 0x3c10 -#define STM32F746_PD12_FUNC_ANALOG 0x3c11 - -#define STM32F746_PD13_FUNC_GPIO 0x3d00 -#define STM32F746_PD13_FUNC_TIM4_CH2 0x3d03 -#define STM32F746_PD13_FUNC_LPTIM1_OUT 0x3d04 -#define STM32F746_PD13_FUNC_I2C4_SDA 0x3d05 -#define STM32F746_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a -#define STM32F746_PD13_FUNC_SAI2_SCK_A 0x3d0b -#define STM32F746_PD13_FUNC_FMC_A18 0x3d0d -#define STM32F746_PD13_FUNC_EVENTOUT 0x3d10 -#define STM32F746_PD13_FUNC_ANALOG 0x3d11 - -#define STM32F746_PD14_FUNC_GPIO 0x3e00 -#define STM32F746_PD14_FUNC_TIM4_CH3 0x3e03 -#define STM32F746_PD14_FUNC_UART8_CTS 0x3e09 -#define STM32F746_PD14_FUNC_FMC_D0 0x3e0d -#define STM32F746_PD14_FUNC_EVENTOUT 0x3e10 -#define STM32F746_PD14_FUNC_ANALOG 0x3e11 - -#define STM32F746_PD15_FUNC_GPIO 0x3f00 -#define STM32F746_PD15_FUNC_TIM4_CH4 0x3f03 -#define STM32F746_PD15_FUNC_UART8_RTS 0x3f09 -#define STM32F746_PD15_FUNC_FMC_D1 0x3f0d -#define STM32F746_PD15_FUNC_EVENTOUT 0x3f10 -#define STM32F746_PD15_FUNC_ANALOG 0x3f11 - - -#define STM32F746_PE0_FUNC_GPIO 0x4000 -#define STM32F746_PE0_FUNC_TIM4_ETR 0x4003 -#define STM32F746_PE0_FUNC_LPTIM1_ETR 0x4004 -#define STM32F746_PE0_FUNC_UART8_RX 0x4009 -#define STM32F746_PE0_FUNC_SAI2_MCLK_A 0x400b -#define STM32F746_PE0_FUNC_FMC_NBL0 0x400d -#define STM32F746_PE0_FUNC_DCMI_D2 0x400e -#define STM32F746_PE0_FUNC_EVENTOUT 0x4010 -#define STM32F746_PE0_FUNC_ANALOG 0x4011 - -#define STM32F746_PE1_FUNC_GPIO 0x4100 -#define STM32F746_PE1_FUNC_LPTIM1_IN2 0x4104 -#define STM32F746_PE1_FUNC_UART8_TX 0x4109 -#define STM32F746_PE1_FUNC_FMC_NBL1 0x410d -#define STM32F746_PE1_FUNC_DCMI_D3 0x410e -#define STM32F746_PE1_FUNC_EVENTOUT 0x4110 -#define STM32F746_PE1_FUNC_ANALOG 0x4111 - -#define STM32F746_PE2_FUNC_GPIO 0x4200 -#define STM32F746_PE2_FUNC_TRACECLK 0x4201 -#define STM32F746_PE2_FUNC_SPI4_SCK 0x4206 -#define STM32F746_PE2_FUNC_SAI1_MCLK_A 0x4207 -#define STM32F746_PE2_FUNC_QUADSPI_BK1_IO2 0x420a -#define STM32F746_PE2_FUNC_ETH_MII_TXD3 0x420c -#define STM32F746_PE2_FUNC_FMC_A23 0x420d -#define STM32F746_PE2_FUNC_EVENTOUT 0x4210 -#define STM32F746_PE2_FUNC_ANALOG 0x4211 - -#define STM32F746_PE3_FUNC_GPIO 0x4300 -#define STM32F746_PE3_FUNC_TRACED0 0x4301 -#define STM32F746_PE3_FUNC_SAI1_SD_B 0x4307 -#define STM32F746_PE3_FUNC_FMC_A19 0x430d -#define STM32F746_PE3_FUNC_EVENTOUT 0x4310 -#define STM32F746_PE3_FUNC_ANALOG 0x4311 - -#define STM32F746_PE4_FUNC_GPIO 0x4400 -#define STM32F746_PE4_FUNC_TRACED1 0x4401 -#define STM32F746_PE4_FUNC_SPI4_NSS 0x4406 -#define STM32F746_PE4_FUNC_SAI1_FS_A 0x4407 -#define STM32F746_PE4_FUNC_FMC_A20 0x440d -#define STM32F746_PE4_FUNC_DCMI_D4 0x440e -#define STM32F746_PE4_FUNC_LCD_B0 0x440f -#define STM32F746_PE4_FUNC_EVENTOUT 0x4410 -#define STM32F746_PE4_FUNC_ANALOG 0x4411 - -#define STM32F746_PE5_FUNC_GPIO 0x4500 -#define STM32F746_PE5_FUNC_TRACED2 0x4501 -#define STM32F746_PE5_FUNC_TIM9_CH1 0x4504 -#define STM32F746_PE5_FUNC_SPI4_MISO 0x4506 -#define STM32F746_PE5_FUNC_SAI1_SCK_A 0x4507 -#define STM32F746_PE5_FUNC_FMC_A21 0x450d -#define STM32F746_PE5_FUNC_DCMI_D6 0x450e -#define STM32F746_PE5_FUNC_LCD_G0 0x450f -#define STM32F746_PE5_FUNC_EVENTOUT 0x4510 -#define STM32F746_PE5_FUNC_ANALOG 0x4511 - -#define STM32F746_PE6_FUNC_GPIO 0x4600 -#define STM32F746_PE6_FUNC_TRACED3 0x4601 -#define STM32F746_PE6_FUNC_TIM1_BKIN2 0x4602 -#define STM32F746_PE6_FUNC_TIM9_CH2 0x4604 -#define STM32F746_PE6_FUNC_SPI4_MOSI 0x4606 -#define STM32F746_PE6_FUNC_SAI1_SD_A 0x4607 -#define STM32F746_PE6_FUNC_SAI2_MCLK_B 0x460b -#define STM32F746_PE6_FUNC_FMC_A22 0x460d -#define STM32F746_PE6_FUNC_DCMI_D7 0x460e -#define STM32F746_PE6_FUNC_LCD_G1 0x460f -#define STM32F746_PE6_FUNC_EVENTOUT 0x4610 -#define STM32F746_PE6_FUNC_ANALOG 0x4611 - -#define STM32F746_PE7_FUNC_GPIO 0x4700 -#define STM32F746_PE7_FUNC_TIM1_ETR 0x4702 -#define STM32F746_PE7_FUNC_UART7_RX 0x4709 -#define STM32F746_PE7_FUNC_QUADSPI_BK2_IO0 0x470b -#define STM32F746_PE7_FUNC_FMC_D4 0x470d -#define STM32F746_PE7_FUNC_EVENTOUT 0x4710 -#define STM32F746_PE7_FUNC_ANALOG 0x4711 - -#define STM32F746_PE8_FUNC_GPIO 0x4800 -#define STM32F746_PE8_FUNC_TIM1_CH1N 0x4802 -#define STM32F746_PE8_FUNC_UART7_TX 0x4809 -#define STM32F746_PE8_FUNC_QUADSPI_BK2_IO1 0x480b -#define STM32F746_PE8_FUNC_FMC_D5 0x480d -#define STM32F746_PE8_FUNC_EVENTOUT 0x4810 -#define STM32F746_PE8_FUNC_ANALOG 0x4811 - -#define STM32F746_PE9_FUNC_GPIO 0x4900 -#define STM32F746_PE9_FUNC_TIM1_CH1 0x4902 -#define STM32F746_PE9_FUNC_UART7_RTS 0x4909 -#define STM32F746_PE9_FUNC_QUADSPI_BK2_IO2 0x490b -#define STM32F746_PE9_FUNC_FMC_D6 0x490d -#define STM32F746_PE9_FUNC_EVENTOUT 0x4910 -#define STM32F746_PE9_FUNC_ANALOG 0x4911 - -#define STM32F746_PE10_FUNC_GPIO 0x4a00 -#define STM32F746_PE10_FUNC_TIM1_CH2N 0x4a02 -#define STM32F746_PE10_FUNC_UART7_CTS 0x4a09 -#define STM32F746_PE10_FUNC_QUADSPI_BK2_IO3 0x4a0b -#define STM32F746_PE10_FUNC_FMC_D7 0x4a0d -#define STM32F746_PE10_FUNC_EVENTOUT 0x4a10 -#define STM32F746_PE10_FUNC_ANALOG 0x4a11 - -#define STM32F746_PE11_FUNC_GPIO 0x4b00 -#define STM32F746_PE11_FUNC_TIM1_CH2 0x4b02 -#define STM32F746_PE11_FUNC_SPI4_NSS 0x4b06 -#define STM32F746_PE11_FUNC_SAI2_SD_B 0x4b0b -#define STM32F746_PE11_FUNC_FMC_D8 0x4b0d -#define STM32F746_PE11_FUNC_LCD_G3 0x4b0f -#define STM32F746_PE11_FUNC_EVENTOUT 0x4b10 -#define STM32F746_PE11_FUNC_ANALOG 0x4b11 - -#define STM32F746_PE12_FUNC_GPIO 0x4c00 -#define STM32F746_PE12_FUNC_TIM1_CH3N 0x4c02 -#define STM32F746_PE12_FUNC_SPI4_SCK 0x4c06 -#define STM32F746_PE12_FUNC_SAI2_SCK_B 0x4c0b -#define STM32F746_PE12_FUNC_FMC_D9 0x4c0d -#define STM32F746_PE12_FUNC_LCD_B4 0x4c0f -#define STM32F746_PE12_FUNC_EVENTOUT 0x4c10 -#define STM32F746_PE12_FUNC_ANALOG 0x4c11 - -#define STM32F746_PE13_FUNC_GPIO 0x4d00 -#define STM32F746_PE13_FUNC_TIM1_CH3 0x4d02 -#define STM32F746_PE13_FUNC_SPI4_MISO 0x4d06 -#define STM32F746_PE13_FUNC_SAI2_FS_B 0x4d0b -#define STM32F746_PE13_FUNC_FMC_D10 0x4d0d -#define STM32F746_PE13_FUNC_LCD_DE 0x4d0f -#define STM32F746_PE13_FUNC_EVENTOUT 0x4d10 -#define STM32F746_PE13_FUNC_ANALOG 0x4d11 - -#define STM32F746_PE14_FUNC_GPIO 0x4e00 -#define STM32F746_PE14_FUNC_TIM1_CH4 0x4e02 -#define STM32F746_PE14_FUNC_SPI4_MOSI 0x4e06 -#define STM32F746_PE14_FUNC_SAI2_MCLK_B 0x4e0b -#define STM32F746_PE14_FUNC_FMC_D11 0x4e0d -#define STM32F746_PE14_FUNC_LCD_CLK 0x4e0f -#define STM32F746_PE14_FUNC_EVENTOUT 0x4e10 -#define STM32F746_PE14_FUNC_ANALOG 0x4e11 - -#define STM32F746_PE15_FUNC_GPIO 0x4f00 -#define STM32F746_PE15_FUNC_TIM1_BKIN 0x4f02 -#define STM32F746_PE15_FUNC_FMC_D12 0x4f0d -#define STM32F746_PE15_FUNC_LCD_R7 0x4f0f -#define STM32F746_PE15_FUNC_EVENTOUT 0x4f10 -#define STM32F746_PE15_FUNC_ANALOG 0x4f11 - - -#define STM32F746_PF0_FUNC_GPIO 0x5000 -#define STM32F746_PF0_FUNC_I2C2_SDA 0x5005 -#define STM32F746_PF0_FUNC_FMC_A0 0x500d -#define STM32F746_PF0_FUNC_EVENTOUT 0x5010 -#define STM32F746_PF0_FUNC_ANALOG 0x5011 - -#define STM32F746_PF1_FUNC_GPIO 0x5100 -#define STM32F746_PF1_FUNC_I2C2_SCL 0x5105 -#define STM32F746_PF1_FUNC_FMC_A1 0x510d -#define STM32F746_PF1_FUNC_EVENTOUT 0x5110 -#define STM32F746_PF1_FUNC_ANALOG 0x5111 - -#define STM32F746_PF2_FUNC_GPIO 0x5200 -#define STM32F746_PF2_FUNC_I2C2_SMBA 0x5205 -#define STM32F746_PF2_FUNC_FMC_A2 0x520d -#define STM32F746_PF2_FUNC_EVENTOUT 0x5210 -#define STM32F746_PF2_FUNC_ANALOG 0x5211 - -#define STM32F746_PF3_FUNC_GPIO 0x5300 -#define STM32F746_PF3_FUNC_FMC_A3 0x530d -#define STM32F746_PF3_FUNC_EVENTOUT 0x5310 -#define STM32F746_PF3_FUNC_ANALOG 0x5311 - -#define STM32F746_PF4_FUNC_GPIO 0x5400 -#define STM32F746_PF4_FUNC_FMC_A4 0x540d -#define STM32F746_PF4_FUNC_EVENTOUT 0x5410 -#define STM32F746_PF4_FUNC_ANALOG 0x5411 - -#define STM32F746_PF5_FUNC_GPIO 0x5500 -#define STM32F746_PF5_FUNC_FMC_A5 0x550d -#define STM32F746_PF5_FUNC_EVENTOUT 0x5510 -#define STM32F746_PF5_FUNC_ANALOG 0x5511 - -#define STM32F746_PF6_FUNC_GPIO 0x5600 -#define STM32F746_PF6_FUNC_TIM10_CH1 0x5604 -#define STM32F746_PF6_FUNC_SPI5_NSS 0x5606 -#define STM32F746_PF6_FUNC_SAI1_SD_B 0x5607 -#define STM32F746_PF6_FUNC_UART7_RX 0x5609 -#define STM32F746_PF6_FUNC_QUADSPI_BK1_IO3 0x560a -#define STM32F746_PF6_FUNC_EVENTOUT 0x5610 -#define STM32F746_PF6_FUNC_ANALOG 0x5611 - -#define STM32F746_PF7_FUNC_GPIO 0x5700 -#define STM32F746_PF7_FUNC_TIM11_CH1 0x5704 -#define STM32F746_PF7_FUNC_SPI5_SCK 0x5706 -#define STM32F746_PF7_FUNC_SAI1_MCLK_B 0x5707 -#define STM32F746_PF7_FUNC_UART7_TX 0x5709 -#define STM32F746_PF7_FUNC_QUADSPI_BK1_IO2 0x570a -#define STM32F746_PF7_FUNC_EVENTOUT 0x5710 -#define STM32F746_PF7_FUNC_ANALOG 0x5711 - -#define STM32F746_PF8_FUNC_GPIO 0x5800 -#define STM32F746_PF8_FUNC_SPI5_MISO 0x5806 -#define STM32F746_PF8_FUNC_SAI1_SCK_B 0x5807 -#define STM32F746_PF8_FUNC_UART7_RTS 0x5809 -#define STM32F746_PF8_FUNC_TIM13_CH1 0x580a -#define STM32F746_PF8_FUNC_QUADSPI_BK1_IO0 0x580b -#define STM32F746_PF8_FUNC_EVENTOUT 0x5810 -#define STM32F746_PF8_FUNC_ANALOG 0x5811 - -#define STM32F746_PF9_FUNC_GPIO 0x5900 -#define STM32F746_PF9_FUNC_SPI5_MOSI 0x5906 -#define STM32F746_PF9_FUNC_SAI1_FS_B 0x5907 -#define STM32F746_PF9_FUNC_UART7_CTS 0x5909 -#define STM32F746_PF9_FUNC_TIM14_CH1 0x590a -#define STM32F746_PF9_FUNC_QUADSPI_BK1_IO1 0x590b -#define STM32F746_PF9_FUNC_EVENTOUT 0x5910 -#define STM32F746_PF9_FUNC_ANALOG 0x5911 - -#define STM32F746_PF10_FUNC_GPIO 0x5a00 -#define STM32F746_PF10_FUNC_DCMI_D11 0x5a0e -#define STM32F746_PF10_FUNC_LCD_DE 0x5a0f -#define STM32F746_PF10_FUNC_EVENTOUT 0x5a10 -#define STM32F746_PF10_FUNC_ANALOG 0x5a11 - -#define STM32F746_PF11_FUNC_GPIO 0x5b00 -#define STM32F746_PF11_FUNC_SPI5_MOSI 0x5b06 -#define STM32F746_PF11_FUNC_SAI2_SD_B 0x5b0b -#define STM32F746_PF11_FUNC_FMC_SDNRAS 0x5b0d -#define STM32F746_PF11_FUNC_DCMI_D12 0x5b0e -#define STM32F746_PF11_FUNC_EVENTOUT 0x5b10 -#define STM32F746_PF11_FUNC_ANALOG 0x5b11 - -#define STM32F746_PF12_FUNC_GPIO 0x5c00 -#define STM32F746_PF12_FUNC_FMC_A6 0x5c0d -#define STM32F746_PF12_FUNC_EVENTOUT 0x5c10 -#define STM32F746_PF12_FUNC_ANALOG 0x5c11 - -#define STM32F746_PF13_FUNC_GPIO 0x5d00 -#define STM32F746_PF13_FUNC_I2C4_SMBA 0x5d05 -#define STM32F746_PF13_FUNC_FMC_A7 0x5d0d -#define STM32F746_PF13_FUNC_EVENTOUT 0x5d10 -#define STM32F746_PF13_FUNC_ANALOG 0x5d11 - -#define STM32F746_PF14_FUNC_GPIO 0x5e00 -#define STM32F746_PF14_FUNC_I2C4_SCL 0x5e05 -#define STM32F746_PF14_FUNC_FMC_A8 0x5e0d -#define STM32F746_PF14_FUNC_EVENTOUT 0x5e10 -#define STM32F746_PF14_FUNC_ANALOG 0x5e11 - -#define STM32F746_PF15_FUNC_GPIO 0x5f00 -#define STM32F746_PF15_FUNC_I2C4_SDA 0x5f05 -#define STM32F746_PF15_FUNC_FMC_A9 0x5f0d -#define STM32F746_PF15_FUNC_EVENTOUT 0x5f10 -#define STM32F746_PF15_FUNC_ANALOG 0x5f11 - - -#define STM32F746_PG0_FUNC_GPIO 0x6000 -#define STM32F746_PG0_FUNC_FMC_A10 0x600d -#define STM32F746_PG0_FUNC_EVENTOUT 0x6010 -#define STM32F746_PG0_FUNC_ANALOG 0x6011 - -#define STM32F746_PG1_FUNC_GPIO 0x6100 -#define STM32F746_PG1_FUNC_FMC_A11 0x610d -#define STM32F746_PG1_FUNC_EVENTOUT 0x6110 -#define STM32F746_PG1_FUNC_ANALOG 0x6111 - -#define STM32F746_PG2_FUNC_GPIO 0x6200 -#define STM32F746_PG2_FUNC_FMC_A12 0x620d -#define STM32F746_PG2_FUNC_EVENTOUT 0x6210 -#define STM32F746_PG2_FUNC_ANALOG 0x6211 - -#define STM32F746_PG3_FUNC_GPIO 0x6300 -#define STM32F746_PG3_FUNC_FMC_A13 0x630d -#define STM32F746_PG3_FUNC_EVENTOUT 0x6310 -#define STM32F746_PG3_FUNC_ANALOG 0x6311 - -#define STM32F746_PG4_FUNC_GPIO 0x6400 -#define STM32F746_PG4_FUNC_FMC_A14_FMC_BA0 0x640d -#define STM32F746_PG4_FUNC_EVENTOUT 0x6410 -#define STM32F746_PG4_FUNC_ANALOG 0x6411 - -#define STM32F746_PG5_FUNC_GPIO 0x6500 -#define STM32F746_PG5_FUNC_FMC_A15_FMC_BA1 0x650d -#define STM32F746_PG5_FUNC_EVENTOUT 0x6510 -#define STM32F746_PG5_FUNC_ANALOG 0x6511 - -#define STM32F746_PG6_FUNC_GPIO 0x6600 -#define STM32F746_PG6_FUNC_DCMI_D12 0x660e -#define STM32F746_PG6_FUNC_LCD_R7 0x660f -#define STM32F746_PG6_FUNC_EVENTOUT 0x6610 -#define STM32F746_PG6_FUNC_ANALOG 0x6611 - -#define STM32F746_PG7_FUNC_GPIO 0x6700 -#define STM32F746_PG7_FUNC_USART6_CK 0x6709 -#define STM32F746_PG7_FUNC_FMC_INT 0x670d -#define STM32F746_PG7_FUNC_DCMI_D13 0x670e -#define STM32F746_PG7_FUNC_LCD_CLK 0x670f -#define STM32F746_PG7_FUNC_EVENTOUT 0x6710 -#define STM32F746_PG7_FUNC_ANALOG 0x6711 - -#define STM32F746_PG8_FUNC_GPIO 0x6800 -#define STM32F746_PG8_FUNC_SPI6_NSS 0x6806 -#define STM32F746_PG8_FUNC_SPDIFRX_IN2 0x6808 -#define STM32F746_PG8_FUNC_USART6_RTS 0x6809 -#define STM32F746_PG8_FUNC_ETH_PPS_OUT 0x680c -#define STM32F746_PG8_FUNC_FMC_SDCLK 0x680d -#define STM32F746_PG8_FUNC_EVENTOUT 0x6810 -#define STM32F746_PG8_FUNC_ANALOG 0x6811 - -#define STM32F746_PG9_FUNC_GPIO 0x6900 -#define STM32F746_PG9_FUNC_SPDIFRX_IN3 0x6908 -#define STM32F746_PG9_FUNC_USART6_RX 0x6909 -#define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a -#define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b -#define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d -#define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e -#define STM32F746_PG9_FUNC_EVENTOUT 0x6910 -#define STM32F746_PG9_FUNC_ANALOG 0x6911 - -#define STM32F746_PG10_FUNC_GPIO 0x6a00 -#define STM32F746_PG10_FUNC_LCD_G3 0x6a0a -#define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b -#define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d -#define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e -#define STM32F746_PG10_FUNC_LCD_B2 0x6a0f -#define STM32F746_PG10_FUNC_EVENTOUT 0x6a10 -#define STM32F746_PG10_FUNC_ANALOG 0x6a11 - -#define STM32F746_PG11_FUNC_GPIO 0x6b00 -#define STM32F746_PG11_FUNC_SPDIFRX_IN0 0x6b08 -#define STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c -#define STM32F746_PG11_FUNC_DCMI_D3 0x6b0e -#define STM32F746_PG11_FUNC_LCD_B3 0x6b0f -#define STM32F746_PG11_FUNC_EVENTOUT 0x6b10 -#define STM32F746_PG11_FUNC_ANALOG 0x6b11 - -#define STM32F746_PG12_FUNC_GPIO 0x6c00 -#define STM32F746_PG12_FUNC_LPTIM1_IN1 0x6c04 -#define STM32F746_PG12_FUNC_SPI6_MISO 0x6c06 -#define STM32F746_PG12_FUNC_SPDIFRX_IN1 0x6c08 -#define STM32F746_PG12_FUNC_USART6_RTS 0x6c09 -#define STM32F746_PG12_FUNC_LCD_B4 0x6c0a -#define STM32F746_PG12_FUNC_FMC_NE4 0x6c0d -#define STM32F746_PG12_FUNC_LCD_B1 0x6c0f -#define STM32F746_PG12_FUNC_EVENTOUT 0x6c10 -#define STM32F746_PG12_FUNC_ANALOG 0x6c11 - -#define STM32F746_PG13_FUNC_GPIO 0x6d00 -#define STM32F746_PG13_FUNC_TRACED0 0x6d01 -#define STM32F746_PG13_FUNC_LPTIM1_OUT 0x6d04 -#define STM32F746_PG13_FUNC_SPI6_SCK 0x6d06 -#define STM32F746_PG13_FUNC_USART6_CTS 0x6d09 -#define STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c -#define STM32F746_PG13_FUNC_FMC_A24 0x6d0d -#define STM32F746_PG13_FUNC_LCD_R0 0x6d0f -#define STM32F746_PG13_FUNC_EVENTOUT 0x6d10 -#define STM32F746_PG13_FUNC_ANALOG 0x6d11 - -#define STM32F746_PG14_FUNC_GPIO 0x6e00 -#define STM32F746_PG14_FUNC_TRACED1 0x6e01 -#define STM32F746_PG14_FUNC_LPTIM1_ETR 0x6e04 -#define STM32F746_PG14_FUNC_SPI6_MOSI 0x6e06 -#define STM32F746_PG14_FUNC_USART6_TX 0x6e09 -#define STM32F746_PG14_FUNC_QUADSPI_BK2_IO3 0x6e0a -#define STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c -#define STM32F746_PG14_FUNC_FMC_A25 0x6e0d -#define STM32F746_PG14_FUNC_LCD_B0 0x6e0f -#define STM32F746_PG14_FUNC_EVENTOUT 0x6e10 -#define STM32F746_PG14_FUNC_ANALOG 0x6e11 - -#define STM32F746_PG15_FUNC_GPIO 0x6f00 -#define STM32F746_PG15_FUNC_USART6_CTS 0x6f09 -#define STM32F746_PG15_FUNC_FMC_SDNCAS 0x6f0d -#define STM32F746_PG15_FUNC_DCMI_D13 0x6f0e -#define STM32F746_PG15_FUNC_EVENTOUT 0x6f10 -#define STM32F746_PG15_FUNC_ANALOG 0x6f11 - - -#define STM32F746_PH0_FUNC_GPIO 0x7000 -#define STM32F746_PH0_FUNC_EVENTOUT 0x7010 -#define STM32F746_PH0_FUNC_ANALOG 0x7011 - -#define STM32F746_PH1_FUNC_GPIO 0x7100 -#define STM32F746_PH1_FUNC_EVENTOUT 0x7110 -#define STM32F746_PH1_FUNC_ANALOG 0x7111 - -#define STM32F746_PH2_FUNC_GPIO 0x7200 -#define STM32F746_PH2_FUNC_LPTIM1_IN2 0x7204 -#define STM32F746_PH2_FUNC_QUADSPI_BK2_IO0 0x720a -#define STM32F746_PH2_FUNC_SAI2_SCK_B 0x720b -#define STM32F746_PH2_FUNC_ETH_MII_CRS 0x720c -#define STM32F746_PH2_FUNC_FMC_SDCKE0 0x720d -#define STM32F746_PH2_FUNC_LCD_R0 0x720f -#define STM32F746_PH2_FUNC_EVENTOUT 0x7210 -#define STM32F746_PH2_FUNC_ANALOG 0x7211 - -#define STM32F746_PH3_FUNC_GPIO 0x7300 -#define STM32F746_PH3_FUNC_QUADSPI_BK2_IO1 0x730a -#define STM32F746_PH3_FUNC_SAI2_MCLK_B 0x730b -#define STM32F746_PH3_FUNC_ETH_MII_COL 0x730c -#define STM32F746_PH3_FUNC_FMC_SDNE0 0x730d -#define STM32F746_PH3_FUNC_LCD_R1 0x730f -#define STM32F746_PH3_FUNC_EVENTOUT 0x7310 -#define STM32F746_PH3_FUNC_ANALOG 0x7311 - -#define STM32F746_PH4_FUNC_GPIO 0x7400 -#define STM32F746_PH4_FUNC_I2C2_SCL 0x7405 -#define STM32F746_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b -#define STM32F746_PH4_FUNC_EVENTOUT 0x7410 -#define STM32F746_PH4_FUNC_ANALOG 0x7411 - -#define STM32F746_PH5_FUNC_GPIO 0x7500 -#define STM32F746_PH5_FUNC_I2C2_SDA 0x7505 -#define STM32F746_PH5_FUNC_SPI5_NSS 0x7506 -#define STM32F746_PH5_FUNC_FMC_SDNWE 0x750d -#define STM32F746_PH5_FUNC_EVENTOUT 0x7510 -#define STM32F746_PH5_FUNC_ANALOG 0x7511 - -#define STM32F746_PH6_FUNC_GPIO 0x7600 -#define STM32F746_PH6_FUNC_I2C2_SMBA 0x7605 -#define STM32F746_PH6_FUNC_SPI5_SCK 0x7606 -#define STM32F746_PH6_FUNC_TIM12_CH1 0x760a -#define STM32F746_PH6_FUNC_ETH_MII_RXD2 0x760c -#define STM32F746_PH6_FUNC_FMC_SDNE1 0x760d -#define STM32F746_PH6_FUNC_DCMI_D8 0x760e -#define STM32F746_PH6_FUNC_EVENTOUT 0x7610 -#define STM32F746_PH6_FUNC_ANALOG 0x7611 - -#define STM32F746_PH7_FUNC_GPIO 0x7700 -#define STM32F746_PH7_FUNC_I2C3_SCL 0x7705 -#define STM32F746_PH7_FUNC_SPI5_MISO 0x7706 -#define STM32F746_PH7_FUNC_ETH_MII_RXD3 0x770c -#define STM32F746_PH7_FUNC_FMC_SDCKE1 0x770d -#define STM32F746_PH7_FUNC_DCMI_D9 0x770e -#define STM32F746_PH7_FUNC_EVENTOUT 0x7710 -#define STM32F746_PH7_FUNC_ANALOG 0x7711 - -#define STM32F746_PH8_FUNC_GPIO 0x7800 -#define STM32F746_PH8_FUNC_I2C3_SDA 0x7805 -#define STM32F746_PH8_FUNC_FMC_D16 0x780d -#define STM32F746_PH8_FUNC_DCMI_HSYNC 0x780e -#define STM32F746_PH8_FUNC_LCD_R2 0x780f -#define STM32F746_PH8_FUNC_EVENTOUT 0x7810 -#define STM32F746_PH8_FUNC_ANALOG 0x7811 - -#define STM32F746_PH9_FUNC_GPIO 0x7900 -#define STM32F746_PH9_FUNC_I2C3_SMBA 0x7905 -#define STM32F746_PH9_FUNC_TIM12_CH2 0x790a -#define STM32F746_PH9_FUNC_FMC_D17 0x790d -#define STM32F746_PH9_FUNC_DCMI_D0 0x790e -#define STM32F746_PH9_FUNC_LCD_R3 0x790f -#define STM32F746_PH9_FUNC_EVENTOUT 0x7910 -#define STM32F746_PH9_FUNC_ANALOG 0x7911 - -#define STM32F746_PH10_FUNC_GPIO 0x7a00 -#define STM32F746_PH10_FUNC_TIM5_CH1 0x7a03 -#define STM32F746_PH10_FUNC_I2C4_SMBA 0x7a05 -#define STM32F746_PH10_FUNC_FMC_D18 0x7a0d -#define STM32F746_PH10_FUNC_DCMI_D1 0x7a0e -#define STM32F746_PH10_FUNC_LCD_R4 0x7a0f -#define STM32F746_PH10_FUNC_EVENTOUT 0x7a10 -#define STM32F746_PH10_FUNC_ANALOG 0x7a11 - -#define STM32F746_PH11_FUNC_GPIO 0x7b00 -#define STM32F746_PH11_FUNC_TIM5_CH2 0x7b03 -#define STM32F746_PH11_FUNC_I2C4_SCL 0x7b05 -#define STM32F746_PH11_FUNC_FMC_D19 0x7b0d -#define STM32F746_PH11_FUNC_DCMI_D2 0x7b0e -#define STM32F746_PH11_FUNC_LCD_R5 0x7b0f -#define STM32F746_PH11_FUNC_EVENTOUT 0x7b10 -#define STM32F746_PH11_FUNC_ANALOG 0x7b11 - -#define STM32F746_PH12_FUNC_GPIO 0x7c00 -#define STM32F746_PH12_FUNC_TIM5_CH3 0x7c03 -#define STM32F746_PH12_FUNC_I2C4_SDA 0x7c05 -#define STM32F746_PH12_FUNC_FMC_D20 0x7c0d -#define STM32F746_PH12_FUNC_DCMI_D3 0x7c0e -#define STM32F746_PH12_FUNC_LCD_R6 0x7c0f -#define STM32F746_PH12_FUNC_EVENTOUT 0x7c10 -#define STM32F746_PH12_FUNC_ANALOG 0x7c11 - -#define STM32F746_PH13_FUNC_GPIO 0x7d00 -#define STM32F746_PH13_FUNC_TIM8_CH1N 0x7d04 -#define STM32F746_PH13_FUNC_CAN1_TX 0x7d0a -#define STM32F746_PH13_FUNC_FMC_D21 0x7d0d -#define STM32F746_PH13_FUNC_LCD_G2 0x7d0f -#define STM32F746_PH13_FUNC_EVENTOUT 0x7d10 -#define STM32F746_PH13_FUNC_ANALOG 0x7d11 - -#define STM32F746_PH14_FUNC_GPIO 0x7e00 -#define STM32F746_PH14_FUNC_TIM8_CH2N 0x7e04 -#define STM32F746_PH14_FUNC_FMC_D22 0x7e0d -#define STM32F746_PH14_FUNC_DCMI_D4 0x7e0e -#define STM32F746_PH14_FUNC_LCD_G3 0x7e0f -#define STM32F746_PH14_FUNC_EVENTOUT 0x7e10 -#define STM32F746_PH14_FUNC_ANALOG 0x7e11 - -#define STM32F746_PH15_FUNC_GPIO 0x7f00 -#define STM32F746_PH15_FUNC_TIM8_CH3N 0x7f04 -#define STM32F746_PH15_FUNC_FMC_D23 0x7f0d -#define STM32F746_PH15_FUNC_DCMI_D11 0x7f0e -#define STM32F746_PH15_FUNC_LCD_G4 0x7f0f -#define STM32F746_PH15_FUNC_EVENTOUT 0x7f10 -#define STM32F746_PH15_FUNC_ANALOG 0x7f11 - - -#define STM32F746_PI0_FUNC_GPIO 0x8000 -#define STM32F746_PI0_FUNC_TIM5_CH4 0x8003 -#define STM32F746_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 -#define STM32F746_PI0_FUNC_FMC_D24 0x800d -#define STM32F746_PI0_FUNC_DCMI_D13 0x800e -#define STM32F746_PI0_FUNC_LCD_G5 0x800f -#define STM32F746_PI0_FUNC_EVENTOUT 0x8010 -#define STM32F746_PI0_FUNC_ANALOG 0x8011 - -#define STM32F746_PI1_FUNC_GPIO 0x8100 -#define STM32F746_PI1_FUNC_TIM8_BKIN2 0x8104 -#define STM32F746_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 -#define STM32F746_PI1_FUNC_FMC_D25 0x810d -#define STM32F746_PI1_FUNC_DCMI_D8 0x810e -#define STM32F746_PI1_FUNC_LCD_G6 0x810f -#define STM32F746_PI1_FUNC_EVENTOUT 0x8110 -#define STM32F746_PI1_FUNC_ANALOG 0x8111 - -#define STM32F746_PI2_FUNC_GPIO 0x8200 -#define STM32F746_PI2_FUNC_TIM8_CH4 0x8204 -#define STM32F746_PI2_FUNC_SPI2_MISO 0x8206 -#define STM32F746_PI2_FUNC_FMC_D26 0x820d -#define STM32F746_PI2_FUNC_DCMI_D9 0x820e -#define STM32F746_PI2_FUNC_LCD_G7 0x820f -#define STM32F746_PI2_FUNC_EVENTOUT 0x8210 -#define STM32F746_PI2_FUNC_ANALOG 0x8211 - -#define STM32F746_PI3_FUNC_GPIO 0x8300 -#define STM32F746_PI3_FUNC_TIM8_ETR 0x8304 -#define STM32F746_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306 -#define STM32F746_PI3_FUNC_FMC_D27 0x830d -#define STM32F746_PI3_FUNC_DCMI_D10 0x830e -#define STM32F746_PI3_FUNC_EVENTOUT 0x8310 -#define STM32F746_PI3_FUNC_ANALOG 0x8311 - -#define STM32F746_PI4_FUNC_GPIO 0x8400 -#define STM32F746_PI4_FUNC_TIM8_BKIN 0x8404 -#define STM32F746_PI4_FUNC_SAI2_MCLK_A 0x840b -#define STM32F746_PI4_FUNC_FMC_NBL2 0x840d -#define STM32F746_PI4_FUNC_DCMI_D5 0x840e -#define STM32F746_PI4_FUNC_LCD_B4 0x840f -#define STM32F746_PI4_FUNC_EVENTOUT 0x8410 -#define STM32F746_PI4_FUNC_ANALOG 0x8411 - -#define STM32F746_PI5_FUNC_GPIO 0x8500 -#define STM32F746_PI5_FUNC_TIM8_CH1 0x8504 -#define STM32F746_PI5_FUNC_SAI2_SCK_A 0x850b -#define STM32F746_PI5_FUNC_FMC_NBL3 0x850d -#define STM32F746_PI5_FUNC_DCMI_VSYNC 0x850e -#define STM32F746_PI5_FUNC_LCD_B5 0x850f -#define STM32F746_PI5_FUNC_EVENTOUT 0x8510 -#define STM32F746_PI5_FUNC_ANALOG 0x8511 - -#define STM32F746_PI6_FUNC_GPIO 0x8600 -#define STM32F746_PI6_FUNC_TIM8_CH2 0x8604 -#define STM32F746_PI6_FUNC_SAI2_SD_A 0x860b -#define STM32F746_PI6_FUNC_FMC_D28 0x860d -#define STM32F746_PI6_FUNC_DCMI_D6 0x860e -#define STM32F746_PI6_FUNC_LCD_B6 0x860f -#define STM32F746_PI6_FUNC_EVENTOUT 0x8610 -#define STM32F746_PI6_FUNC_ANALOG 0x8611 - -#define STM32F746_PI7_FUNC_GPIO 0x8700 -#define STM32F746_PI7_FUNC_TIM8_CH3 0x8704 -#define STM32F746_PI7_FUNC_SAI2_FS_A 0x870b -#define STM32F746_PI7_FUNC_FMC_D29 0x870d -#define STM32F746_PI7_FUNC_DCMI_D7 0x870e -#define STM32F746_PI7_FUNC_LCD_B7 0x870f -#define STM32F746_PI7_FUNC_EVENTOUT 0x8710 -#define STM32F746_PI7_FUNC_ANALOG 0x8711 - -#define STM32F746_PI8_FUNC_GPIO 0x8800 -#define STM32F746_PI8_FUNC_EVENTOUT 0x8810 -#define STM32F746_PI8_FUNC_ANALOG 0x8811 - -#define STM32F746_PI9_FUNC_GPIO 0x8900 -#define STM32F746_PI9_FUNC_CAN1_RX 0x890a -#define STM32F746_PI9_FUNC_FMC_D30 0x890d -#define STM32F746_PI9_FUNC_LCD_VSYNC 0x890f -#define STM32F746_PI9_FUNC_EVENTOUT 0x8910 -#define STM32F746_PI9_FUNC_ANALOG 0x8911 - -#define STM32F746_PI10_FUNC_GPIO 0x8a00 -#define STM32F746_PI10_FUNC_ETH_MII_RX_ER 0x8a0c -#define STM32F746_PI10_FUNC_FMC_D31 0x8a0d -#define STM32F746_PI10_FUNC_LCD_HSYNC 0x8a0f -#define STM32F746_PI10_FUNC_EVENTOUT 0x8a10 -#define STM32F746_PI10_FUNC_ANALOG 0x8a11 - -#define STM32F746_PI11_FUNC_GPIO 0x8b00 -#define STM32F746_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b -#define STM32F746_PI11_FUNC_EVENTOUT 0x8b10 -#define STM32F746_PI11_FUNC_ANALOG 0x8b11 - -#define STM32F746_PI12_FUNC_GPIO 0x8c00 -#define STM32F746_PI12_FUNC_LCD_HSYNC 0x8c0f -#define STM32F746_PI12_FUNC_EVENTOUT 0x8c10 -#define STM32F746_PI12_FUNC_ANALOG 0x8c11 - -#define STM32F746_PI13_FUNC_GPIO 0x8d00 -#define STM32F746_PI13_FUNC_LCD_VSYNC 0x8d0f -#define STM32F746_PI13_FUNC_EVENTOUT 0x8d10 -#define STM32F746_PI13_FUNC_ANALOG 0x8d11 - -#define STM32F746_PI14_FUNC_GPIO 0x8e00 -#define STM32F746_PI14_FUNC_LCD_CLK 0x8e0f -#define STM32F746_PI14_FUNC_EVENTOUT 0x8e10 -#define STM32F746_PI14_FUNC_ANALOG 0x8e11 - -#define STM32F746_PI15_FUNC_GPIO 0x8f00 -#define STM32F746_PI15_FUNC_LCD_R0 0x8f0f -#define STM32F746_PI15_FUNC_EVENTOUT 0x8f10 -#define STM32F746_PI15_FUNC_ANALOG 0x8f11 - - -#define STM32F746_PJ0_FUNC_GPIO 0x9000 -#define STM32F746_PJ0_FUNC_LCD_R1 0x900f -#define STM32F746_PJ0_FUNC_EVENTOUT 0x9010 -#define STM32F746_PJ0_FUNC_ANALOG 0x9011 - -#define STM32F746_PJ1_FUNC_GPIO 0x9100 -#define STM32F746_PJ1_FUNC_LCD_R2 0x910f -#define STM32F746_PJ1_FUNC_EVENTOUT 0x9110 -#define STM32F746_PJ1_FUNC_ANALOG 0x9111 - -#define STM32F746_PJ2_FUNC_GPIO 0x9200 -#define STM32F746_PJ2_FUNC_LCD_R3 0x920f -#define STM32F746_PJ2_FUNC_EVENTOUT 0x9210 -#define STM32F746_PJ2_FUNC_ANALOG 0x9211 - -#define STM32F746_PJ3_FUNC_GPIO 0x9300 -#define STM32F746_PJ3_FUNC_LCD_R4 0x930f -#define STM32F746_PJ3_FUNC_EVENTOUT 0x9310 -#define STM32F746_PJ3_FUNC_ANALOG 0x9311 - -#define STM32F746_PJ4_FUNC_GPIO 0x9400 -#define STM32F746_PJ4_FUNC_LCD_R5 0x940f -#define STM32F746_PJ4_FUNC_EVENTOUT 0x9410 -#define STM32F746_PJ4_FUNC_ANALOG 0x9411 - -#define STM32F746_PJ5_FUNC_GPIO 0x9500 -#define STM32F746_PJ5_FUNC_LCD_R6 0x950f -#define STM32F746_PJ5_FUNC_EVENTOUT 0x9510 -#define STM32F746_PJ5_FUNC_ANALOG 0x9511 - -#define STM32F746_PJ6_FUNC_GPIO 0x9600 -#define STM32F746_PJ6_FUNC_LCD_R7 0x960f -#define STM32F746_PJ6_FUNC_EVENTOUT 0x9610 -#define STM32F746_PJ6_FUNC_ANALOG 0x9611 - -#define STM32F746_PJ7_FUNC_GPIO 0x9700 -#define STM32F746_PJ7_FUNC_LCD_G0 0x970f -#define STM32F746_PJ7_FUNC_EVENTOUT 0x9710 -#define STM32F746_PJ7_FUNC_ANALOG 0x9711 - -#define STM32F746_PJ8_FUNC_GPIO 0x9800 -#define STM32F746_PJ8_FUNC_LCD_G1 0x980f -#define STM32F746_PJ8_FUNC_EVENTOUT 0x9810 -#define STM32F746_PJ8_FUNC_ANALOG 0x9811 - -#define STM32F746_PJ9_FUNC_GPIO 0x9900 -#define STM32F746_PJ9_FUNC_LCD_G2 0x990f -#define STM32F746_PJ9_FUNC_EVENTOUT 0x9910 -#define STM32F746_PJ9_FUNC_ANALOG 0x9911 - -#define STM32F746_PJ10_FUNC_GPIO 0x9a00 -#define STM32F746_PJ10_FUNC_LCD_G3 0x9a0f -#define STM32F746_PJ10_FUNC_EVENTOUT 0x9a10 -#define STM32F746_PJ10_FUNC_ANALOG 0x9a11 - -#define STM32F746_PJ11_FUNC_GPIO 0x9b00 -#define STM32F746_PJ11_FUNC_LCD_G4 0x9b0f -#define STM32F746_PJ11_FUNC_EVENTOUT 0x9b10 -#define STM32F746_PJ11_FUNC_ANALOG 0x9b11 - -#define STM32F746_PJ12_FUNC_GPIO 0x9c00 -#define STM32F746_PJ12_FUNC_LCD_B0 0x9c0f -#define STM32F746_PJ12_FUNC_EVENTOUT 0x9c10 -#define STM32F746_PJ12_FUNC_ANALOG 0x9c11 - -#define STM32F746_PJ13_FUNC_GPIO 0x9d00 -#define STM32F746_PJ13_FUNC_LCD_B1 0x9d0f -#define STM32F746_PJ13_FUNC_EVENTOUT 0x9d10 -#define STM32F746_PJ13_FUNC_ANALOG 0x9d11 - -#define STM32F746_PJ14_FUNC_GPIO 0x9e00 -#define STM32F746_PJ14_FUNC_LCD_B2 0x9e0f -#define STM32F746_PJ14_FUNC_EVENTOUT 0x9e10 -#define STM32F746_PJ14_FUNC_ANALOG 0x9e11 - -#define STM32F746_PJ15_FUNC_GPIO 0x9f00 -#define STM32F746_PJ15_FUNC_LCD_B3 0x9f0f -#define STM32F746_PJ15_FUNC_EVENTOUT 0x9f10 -#define STM32F746_PJ15_FUNC_ANALOG 0x9f11 - - -#define STM32F746_PK0_FUNC_GPIO 0xa000 -#define STM32F746_PK0_FUNC_LCD_G5 0xa00f -#define STM32F746_PK0_FUNC_EVENTOUT 0xa010 -#define STM32F746_PK0_FUNC_ANALOG 0xa011 - -#define STM32F746_PK1_FUNC_GPIO 0xa100 -#define STM32F746_PK1_FUNC_LCD_G6 0xa10f -#define STM32F746_PK1_FUNC_EVENTOUT 0xa110 -#define STM32F746_PK1_FUNC_ANALOG 0xa111 - -#define STM32F746_PK2_FUNC_GPIO 0xa200 -#define STM32F746_PK2_FUNC_LCD_G7 0xa20f -#define STM32F746_PK2_FUNC_EVENTOUT 0xa210 -#define STM32F746_PK2_FUNC_ANALOG 0xa211 - -#define STM32F746_PK3_FUNC_GPIO 0xa300 -#define STM32F746_PK3_FUNC_LCD_B4 0xa30f -#define STM32F746_PK3_FUNC_EVENTOUT 0xa310 -#define STM32F746_PK3_FUNC_ANALOG 0xa311 - -#define STM32F746_PK4_FUNC_GPIO 0xa400 -#define STM32F746_PK4_FUNC_LCD_B5 0xa40f -#define STM32F746_PK4_FUNC_EVENTOUT 0xa410 -#define STM32F746_PK4_FUNC_ANALOG 0xa411 - -#define STM32F746_PK5_FUNC_GPIO 0xa500 -#define STM32F746_PK5_FUNC_LCD_B6 0xa50f -#define STM32F746_PK5_FUNC_EVENTOUT 0xa510 -#define STM32F746_PK5_FUNC_ANALOG 0xa511 - -#define STM32F746_PK6_FUNC_GPIO 0xa600 -#define STM32F746_PK6_FUNC_LCD_B7 0xa60f -#define STM32F746_PK6_FUNC_EVENTOUT 0xa610 -#define STM32F746_PK6_FUNC_ANALOG 0xa611 - -#define STM32F746_PK7_FUNC_GPIO 0xa700 -#define STM32F746_PK7_FUNC_LCD_DE 0xa70f -#define STM32F746_PK7_FUNC_EVENTOUT 0xa710 -#define STM32F746_PK7_FUNC_ANALOG 0xa711 - -#endif /* _DT_BINDINGS_STM32F746_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/stm32h7-pinfunc.h b/include/dt-bindings/pinctrl/stm32h7-pinfunc.h deleted file mode 100644 index 06d99a8ddbc6..000000000000 --- a/include/dt-bindings/pinctrl/stm32h7-pinfunc.h +++ /dev/null @@ -1,1613 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_STM32H7_PINFUNC_H -#define _DT_BINDINGS_STM32H7_PINFUNC_H - -#define STM32H7_PA0_FUNC_GPIO 0x0 -#define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 -#define STM32H7_PA0_FUNC_TIM5_CH1 0x3 -#define STM32H7_PA0_FUNC_TIM8_ETR 0x4 -#define STM32H7_PA0_FUNC_TIM15_BKIN 0x5 -#define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8 -#define STM32H7_PA0_FUNC_UART4_TX 0x9 -#define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa -#define STM32H7_PA0_FUNC_SAI2_SD_B 0xb -#define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc -#define STM32H7_PA0_FUNC_EVENTOUT 0x10 -#define STM32H7_PA0_FUNC_ANALOG 0x11 - -#define STM32H7_PA1_FUNC_GPIO 0x100 -#define STM32H7_PA1_FUNC_TIM2_CH2 0x102 -#define STM32H7_PA1_FUNC_TIM5_CH2 0x103 -#define STM32H7_PA1_FUNC_LPTIM3_OUT 0x104 -#define STM32H7_PA1_FUNC_TIM15_CH1N 0x105 -#define STM32H7_PA1_FUNC_USART2_RTS 0x108 -#define STM32H7_PA1_FUNC_UART4_RX 0x109 -#define STM32H7_PA1_FUNC_QUADSPI_BK1_IO3 0x10a -#define STM32H7_PA1_FUNC_SAI2_MCK_B 0x10b -#define STM32H7_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c -#define STM32H7_PA1_FUNC_LCD_R2 0x10f -#define STM32H7_PA1_FUNC_EVENTOUT 0x110 -#define STM32H7_PA1_FUNC_ANALOG 0x111 - -#define STM32H7_PA2_FUNC_GPIO 0x200 -#define STM32H7_PA2_FUNC_TIM2_CH3 0x202 -#define STM32H7_PA2_FUNC_TIM5_CH3 0x203 -#define STM32H7_PA2_FUNC_LPTIM4_OUT 0x204 -#define STM32H7_PA2_FUNC_TIM15_CH1 0x205 -#define STM32H7_PA2_FUNC_USART2_TX 0x208 -#define STM32H7_PA2_FUNC_SAI2_SCK_B 0x209 -#define STM32H7_PA2_FUNC_ETH_MDIO 0x20c -#define STM32H7_PA2_FUNC_MDIOS_MDIO 0x20d -#define STM32H7_PA2_FUNC_LCD_R1 0x20f -#define STM32H7_PA2_FUNC_EVENTOUT 0x210 -#define STM32H7_PA2_FUNC_ANALOG 0x211 - -#define STM32H7_PA3_FUNC_GPIO 0x300 -#define STM32H7_PA3_FUNC_TIM2_CH4 0x302 -#define STM32H7_PA3_FUNC_TIM5_CH4 0x303 -#define STM32H7_PA3_FUNC_LPTIM5_OUT 0x304 -#define STM32H7_PA3_FUNC_TIM15_CH2 0x305 -#define STM32H7_PA3_FUNC_USART2_RX 0x308 -#define STM32H7_PA3_FUNC_LCD_B2 0x30a -#define STM32H7_PA3_FUNC_OTG_HS_ULPI_D0 0x30b -#define STM32H7_PA3_FUNC_ETH_MII_COL 0x30c -#define STM32H7_PA3_FUNC_LCD_B5 0x30f -#define STM32H7_PA3_FUNC_EVENTOUT 0x310 -#define STM32H7_PA3_FUNC_ANALOG 0x311 - -#define STM32H7_PA4_FUNC_GPIO 0x400 -#define STM32H7_PA4_FUNC_TIM5_ETR 0x403 -#define STM32H7_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406 -#define STM32H7_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 -#define STM32H7_PA4_FUNC_USART2_CK 0x408 -#define STM32H7_PA4_FUNC_SPI6_NSS 0x409 -#define STM32H7_PA4_FUNC_OTG_HS_SOF 0x40d -#define STM32H7_PA4_FUNC_DCMI_HSYNC 0x40e -#define STM32H7_PA4_FUNC_LCD_VSYNC 0x40f -#define STM32H7_PA4_FUNC_EVENTOUT 0x410 -#define STM32H7_PA4_FUNC_ANALOG 0x411 - -#define STM32H7_PA5_FUNC_GPIO 0x500 -#define STM32H7_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 -#define STM32H7_PA5_FUNC_TIM8_CH1N 0x504 -#define STM32H7_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506 -#define STM32H7_PA5_FUNC_SPI6_SCK 0x509 -#define STM32H7_PA5_FUNC_OTG_HS_ULPI_CK 0x50b -#define STM32H7_PA5_FUNC_LCD_R4 0x50f -#define STM32H7_PA5_FUNC_EVENTOUT 0x510 -#define STM32H7_PA5_FUNC_ANALOG 0x511 - -#define STM32H7_PA6_FUNC_GPIO 0x600 -#define STM32H7_PA6_FUNC_TIM1_BKIN 0x602 -#define STM32H7_PA6_FUNC_TIM3_CH1 0x603 -#define STM32H7_PA6_FUNC_TIM8_BKIN 0x604 -#define STM32H7_PA6_FUNC_SPI1_MISO_I2S1_SDI 0x606 -#define STM32H7_PA6_FUNC_SPI6_MISO 0x609 -#define STM32H7_PA6_FUNC_TIM13_CH1 0x60a -#define STM32H7_PA6_FUNC_TIM8_BKIN_COMP12 0x60b -#define STM32H7_PA6_FUNC_MDIOS_MDC 0x60c -#define STM32H7_PA6_FUNC_TIM1_BKIN_COMP12 0x60d -#define STM32H7_PA6_FUNC_DCMI_PIXCLK 0x60e -#define STM32H7_PA6_FUNC_LCD_G2 0x60f -#define STM32H7_PA6_FUNC_EVENTOUT 0x610 -#define STM32H7_PA6_FUNC_ANALOG 0x611 - -#define STM32H7_PA7_FUNC_GPIO 0x700 -#define STM32H7_PA7_FUNC_TIM1_CH1N 0x702 -#define STM32H7_PA7_FUNC_TIM3_CH2 0x703 -#define STM32H7_PA7_FUNC_TIM8_CH1N 0x704 -#define STM32H7_PA7_FUNC_SPI1_MOSI_I2S1_SDO 0x706 -#define STM32H7_PA7_FUNC_SPI6_MOSI 0x709 -#define STM32H7_PA7_FUNC_TIM14_CH1 0x70a -#define STM32H7_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c -#define STM32H7_PA7_FUNC_FMC_SDNWE 0x70d -#define STM32H7_PA7_FUNC_EVENTOUT 0x710 -#define STM32H7_PA7_FUNC_ANALOG 0x711 - -#define STM32H7_PA8_FUNC_GPIO 0x800 -#define STM32H7_PA8_FUNC_MCO1 0x801 -#define STM32H7_PA8_FUNC_TIM1_CH1 0x802 -#define STM32H7_PA8_FUNC_HRTIM_CHB2 0x803 -#define STM32H7_PA8_FUNC_TIM8_BKIN2 0x804 -#define STM32H7_PA8_FUNC_I2C3_SCL 0x805 -#define STM32H7_PA8_FUNC_USART1_CK 0x808 -#define STM32H7_PA8_FUNC_OTG_FS_SOF 0x80b -#define STM32H7_PA8_FUNC_UART7_RX 0x80c -#define STM32H7_PA8_FUNC_TIM8_BKIN2_COMP12 0x80d -#define STM32H7_PA8_FUNC_LCD_B3 0x80e -#define STM32H7_PA8_FUNC_LCD_R6 0x80f -#define STM32H7_PA8_FUNC_EVENTOUT 0x810 -#define STM32H7_PA8_FUNC_ANALOG 0x811 - -#define STM32H7_PA9_FUNC_GPIO 0x900 -#define STM32H7_PA9_FUNC_TIM1_CH2 0x902 -#define STM32H7_PA9_FUNC_HRTIM_CHC1 0x903 -#define STM32H7_PA9_FUNC_LPUART1_TX 0x904 -#define STM32H7_PA9_FUNC_I2C3_SMBA 0x905 -#define STM32H7_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906 -#define STM32H7_PA9_FUNC_USART1_TX 0x908 -#define STM32H7_PA9_FUNC_CAN1_RXFD 0x90a -#define STM32H7_PA9_FUNC_ETH_TX_ER 0x90c -#define STM32H7_PA9_FUNC_DCMI_D0 0x90e -#define STM32H7_PA9_FUNC_LCD_R5 0x90f -#define STM32H7_PA9_FUNC_EVENTOUT 0x910 -#define STM32H7_PA9_FUNC_ANALOG 0x911 - -#define STM32H7_PA10_FUNC_GPIO 0xa00 -#define STM32H7_PA10_FUNC_TIM1_CH3 0xa02 -#define STM32H7_PA10_FUNC_HRTIM_CHC2 0xa03 -#define STM32H7_PA10_FUNC_LPUART1_RX 0xa04 -#define STM32H7_PA10_FUNC_USART1_RX 0xa08 -#define STM32H7_PA10_FUNC_CAN1_TXFD 0xa0a -#define STM32H7_PA10_FUNC_OTG_FS_ID 0xa0b -#define STM32H7_PA10_FUNC_MDIOS_MDIO 0xa0c -#define STM32H7_PA10_FUNC_LCD_B4 0xa0d -#define STM32H7_PA10_FUNC_DCMI_D1 0xa0e -#define STM32H7_PA10_FUNC_LCD_B1 0xa0f -#define STM32H7_PA10_FUNC_EVENTOUT 0xa10 -#define STM32H7_PA10_FUNC_ANALOG 0xa11 - -#define STM32H7_PA11_FUNC_GPIO 0xb00 -#define STM32H7_PA11_FUNC_TIM1_CH4 0xb02 -#define STM32H7_PA11_FUNC_HRTIM_CHD1 0xb03 -#define STM32H7_PA11_FUNC_LPUART1_CTS 0xb04 -#define STM32H7_PA11_FUNC_SPI2_NSS_I2S2_WS 0xb06 -#define STM32H7_PA11_FUNC_UART4_RX 0xb07 -#define STM32H7_PA11_FUNC_USART1_CTS_NSS 0xb08 -#define STM32H7_PA11_FUNC_CAN1_RX 0xb0a -#define STM32H7_PA11_FUNC_OTG_FS_DM 0xb0b -#define STM32H7_PA11_FUNC_LCD_R4 0xb0f -#define STM32H7_PA11_FUNC_EVENTOUT 0xb10 -#define STM32H7_PA11_FUNC_ANALOG 0xb11 - -#define STM32H7_PA12_FUNC_GPIO 0xc00 -#define STM32H7_PA12_FUNC_TIM1_ETR 0xc02 -#define STM32H7_PA12_FUNC_HRTIM_CHD2 0xc03 -#define STM32H7_PA12_FUNC_LPUART1_RTS 0xc04 -#define STM32H7_PA12_FUNC_SPI2_SCK_I2S2_CK 0xc06 -#define STM32H7_PA12_FUNC_UART4_TX 0xc07 -#define STM32H7_PA12_FUNC_USART1_RTS 0xc08 -#define STM32H7_PA12_FUNC_SAI2_FS_B 0xc09 -#define STM32H7_PA12_FUNC_CAN1_TX 0xc0a -#define STM32H7_PA12_FUNC_OTG_FS_DP 0xc0b -#define STM32H7_PA12_FUNC_LCD_R5 0xc0f -#define STM32H7_PA12_FUNC_EVENTOUT 0xc10 -#define STM32H7_PA12_FUNC_ANALOG 0xc11 - -#define STM32H7_PA13_FUNC_GPIO 0xd00 -#define STM32H7_PA13_FUNC_JTMS_SWDIO 0xd01 -#define STM32H7_PA13_FUNC_EVENTOUT 0xd10 -#define STM32H7_PA13_FUNC_ANALOG 0xd11 - -#define STM32H7_PA14_FUNC_GPIO 0xe00 -#define STM32H7_PA14_FUNC_JTCK_SWCLK 0xe01 -#define STM32H7_PA14_FUNC_EVENTOUT 0xe10 -#define STM32H7_PA14_FUNC_ANALOG 0xe11 - -#define STM32H7_PA15_FUNC_GPIO 0xf00 -#define STM32H7_PA15_FUNC_JTDI 0xf01 -#define STM32H7_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 -#define STM32H7_PA15_FUNC_HRTIM_FLT1 0xf03 -#define STM32H7_PA15_FUNC_HDMI_CEC 0xf05 -#define STM32H7_PA15_FUNC_SPI1_NSS_I2S1_WS 0xf06 -#define STM32H7_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 -#define STM32H7_PA15_FUNC_SPI6_NSS 0xf08 -#define STM32H7_PA15_FUNC_UART4_RTS 0xf09 -#define STM32H7_PA15_FUNC_UART7_TX 0xf0c -#define STM32H7_PA15_FUNC_DSI_TE 0xf0e -#define STM32H7_PA15_FUNC_EVENTOUT 0xf10 -#define STM32H7_PA15_FUNC_ANALOG 0xf11 - -#define STM32H7_PB0_FUNC_GPIO 0x1000 -#define STM32H7_PB0_FUNC_TIM1_CH2N 0x1002 -#define STM32H7_PB0_FUNC_TIM3_CH3 0x1003 -#define STM32H7_PB0_FUNC_TIM8_CH2N 0x1004 -#define STM32H7_PB0_FUNC_DFSDM_CKOUT 0x1007 -#define STM32H7_PB0_FUNC_UART4_CTS 0x1009 -#define STM32H7_PB0_FUNC_LCD_R3 0x100a -#define STM32H7_PB0_FUNC_OTG_HS_ULPI_D1 0x100b -#define STM32H7_PB0_FUNC_ETH_MII_RXD2 0x100c -#define STM32H7_PB0_FUNC_LCD_G1 0x100f -#define STM32H7_PB0_FUNC_EVENTOUT 0x1010 -#define STM32H7_PB0_FUNC_ANALOG 0x1011 - -#define STM32H7_PB1_FUNC_GPIO 0x1100 -#define STM32H7_PB1_FUNC_TIM1_CH3N 0x1102 -#define STM32H7_PB1_FUNC_TIM3_CH4 0x1103 -#define STM32H7_PB1_FUNC_TIM8_CH3N 0x1104 -#define STM32H7_PB1_FUNC_DFSDM_DATIN1 0x1107 -#define STM32H7_PB1_FUNC_LCD_R6 0x110a -#define STM32H7_PB1_FUNC_OTG_HS_ULPI_D2 0x110b -#define STM32H7_PB1_FUNC_ETH_MII_RXD3 0x110c -#define STM32H7_PB1_FUNC_LCD_G0 0x110f -#define STM32H7_PB1_FUNC_EVENTOUT 0x1110 -#define STM32H7_PB1_FUNC_ANALOG 0x1111 - -#define STM32H7_PB2_FUNC_GPIO 0x1200 -#define STM32H7_PB2_FUNC_SAI1_D1 0x1203 -#define STM32H7_PB2_FUNC_DFSDM_CKIN1 0x1205 -#define STM32H7_PB2_FUNC_SAI1_SD_A 0x1207 -#define STM32H7_PB2_FUNC_SPI3_MOSI_I2S3_SDO 0x1208 -#define STM32H7_PB2_FUNC_SAI4_SD_A 0x1209 -#define STM32H7_PB2_FUNC_QUADSPI_CLK 0x120a -#define STM32H7_PB2_FUNC_SAI4_D1 0x120b -#define STM32H7_PB2_FUNC_ETH_TX_ER 0x120c -#define STM32H7_PB2_FUNC_EVENTOUT 0x1210 -#define STM32H7_PB2_FUNC_ANALOG 0x1211 - -#define STM32H7_PB3_FUNC_GPIO 0x1300 -#define STM32H7_PB3_FUNC_JTDO_TRACESWO 0x1301 -#define STM32H7_PB3_FUNC_TIM2_CH2 0x1302 -#define STM32H7_PB3_FUNC_HRTIM_FLT4 0x1303 -#define STM32H7_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306 -#define STM32H7_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 -#define STM32H7_PB3_FUNC_SPI6_SCK 0x1309 -#define STM32H7_PB3_FUNC_SDMMC2_D2 0x130a -#define STM32H7_PB3_FUNC_UART7_RX 0x130c -#define STM32H7_PB3_FUNC_EVENTOUT 0x1310 -#define STM32H7_PB3_FUNC_ANALOG 0x1311 - -#define STM32H7_PB4_FUNC_GPIO 0x1400 -#define STM32H7_PB4_FUNC_NJTRST 0x1401 -#define STM32H7_PB4_FUNC_TIM16_BKIN 0x1402 -#define STM32H7_PB4_FUNC_TIM3_CH1 0x1403 -#define STM32H7_PB4_FUNC_HRTIM_EEV6 0x1404 -#define STM32H7_PB4_FUNC_SPI1_MISO_I2S1_SDI 0x1406 -#define STM32H7_PB4_FUNC_SPI3_MISO_I2S3_SDI 0x1407 -#define STM32H7_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408 -#define STM32H7_PB4_FUNC_SPI6_MISO 0x1409 -#define STM32H7_PB4_FUNC_SDMMC2_D3 0x140a -#define STM32H7_PB4_FUNC_UART7_TX 0x140c -#define STM32H7_PB4_FUNC_EVENTOUT 0x1410 -#define STM32H7_PB4_FUNC_ANALOG 0x1411 - -#define STM32H7_PB5_FUNC_GPIO 0x1500 -#define STM32H7_PB5_FUNC_TIM17_BKIN 0x1502 -#define STM32H7_PB5_FUNC_TIM3_CH2 0x1503 -#define STM32H7_PB5_FUNC_HRTIM_EEV7 0x1504 -#define STM32H7_PB5_FUNC_I2C1_SMBA 0x1505 -#define STM32H7_PB5_FUNC_SPI1_MOSI_I2S1_SDO 0x1506 -#define STM32H7_PB5_FUNC_I2C4_SMBA 0x1507 -#define STM32H7_PB5_FUNC_SPI3_MOSI_I2S3_SDO 0x1508 -#define STM32H7_PB5_FUNC_SPI6_MOSI 0x1509 -#define STM32H7_PB5_FUNC_CAN2_RX 0x150a -#define STM32H7_PB5_FUNC_OTG_HS_ULPI_D7 0x150b -#define STM32H7_PB5_FUNC_ETH_PPS_OUT 0x150c -#define STM32H7_PB5_FUNC_FMC_SDCKE1 0x150d -#define STM32H7_PB5_FUNC_DCMI_D10 0x150e -#define STM32H7_PB5_FUNC_UART5_RX 0x150f -#define STM32H7_PB5_FUNC_EVENTOUT 0x1510 -#define STM32H7_PB5_FUNC_ANALOG 0x1511 - -#define STM32H7_PB6_FUNC_GPIO 0x1600 -#define STM32H7_PB6_FUNC_TIM16_CH1N 0x1602 -#define STM32H7_PB6_FUNC_TIM4_CH1 0x1603 -#define STM32H7_PB6_FUNC_HRTIM_EEV8 0x1604 -#define STM32H7_PB6_FUNC_I2C1_SCL 0x1605 -#define STM32H7_PB6_FUNC_HDMI_CEC 0x1606 -#define STM32H7_PB6_FUNC_I2C4_SCL 0x1607 -#define STM32H7_PB6_FUNC_USART1_TX 0x1608 -#define STM32H7_PB6_FUNC_LPUART1_TX 0x1609 -#define STM32H7_PB6_FUNC_CAN2_TX 0x160a -#define STM32H7_PB6_FUNC_QUADSPI_BK1_NCS 0x160b -#define STM32H7_PB6_FUNC_DFSDM_DATIN5 0x160c -#define STM32H7_PB6_FUNC_FMC_SDNE1 0x160d -#define STM32H7_PB6_FUNC_DCMI_D5 0x160e -#define STM32H7_PB6_FUNC_UART5_TX 0x160f -#define STM32H7_PB6_FUNC_EVENTOUT 0x1610 -#define STM32H7_PB6_FUNC_ANALOG 0x1611 - -#define STM32H7_PB7_FUNC_GPIO 0x1700 -#define STM32H7_PB7_FUNC_TIM17_CH1N 0x1702 -#define STM32H7_PB7_FUNC_TIM4_CH2 0x1703 -#define STM32H7_PB7_FUNC_HRTIM_EEV9 0x1704 -#define STM32H7_PB7_FUNC_I2C1_SDA 0x1705 -#define STM32H7_PB7_FUNC_I2C4_SDA 0x1707 -#define STM32H7_PB7_FUNC_USART1_RX 0x1708 -#define STM32H7_PB7_FUNC_LPUART1_RX 0x1709 -#define STM32H7_PB7_FUNC_CAN2_TXFD 0x170a -#define STM32H7_PB7_FUNC_DFSDM_CKIN5 0x170c -#define STM32H7_PB7_FUNC_FMC_NL 0x170d -#define STM32H7_PB7_FUNC_DCMI_VSYNC 0x170e -#define STM32H7_PB7_FUNC_EVENTOUT 0x1710 -#define STM32H7_PB7_FUNC_ANALOG 0x1711 - -#define STM32H7_PB8_FUNC_GPIO 0x1800 -#define STM32H7_PB8_FUNC_TIM16_CH1 0x1802 -#define STM32H7_PB8_FUNC_TIM4_CH3 0x1803 -#define STM32H7_PB8_FUNC_DFSDM_CKIN7 0x1804 -#define STM32H7_PB8_FUNC_I2C1_SCL 0x1805 -#define STM32H7_PB8_FUNC_I2C4_SCL 0x1807 -#define STM32H7_PB8_FUNC_SDMMC1_CKIN 0x1808 -#define STM32H7_PB8_FUNC_UART4_RX 0x1809 -#define STM32H7_PB8_FUNC_CAN1_RX 0x180a -#define STM32H7_PB8_FUNC_SDMMC2_D4 0x180b -#define STM32H7_PB8_FUNC_ETH_MII_TXD3 0x180c -#define STM32H7_PB8_FUNC_SDMMC1_D4 0x180d -#define STM32H7_PB8_FUNC_DCMI_D6 0x180e -#define STM32H7_PB8_FUNC_LCD_B6 0x180f -#define STM32H7_PB8_FUNC_EVENTOUT 0x1810 -#define STM32H7_PB8_FUNC_ANALOG 0x1811 - -#define STM32H7_PB9_FUNC_GPIO 0x1900 -#define STM32H7_PB9_FUNC_TIM17_CH1 0x1902 -#define STM32H7_PB9_FUNC_TIM4_CH4 0x1903 -#define STM32H7_PB9_FUNC_DFSDM_DATIN7 0x1904 -#define STM32H7_PB9_FUNC_I2C1_SDA 0x1905 -#define STM32H7_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 -#define STM32H7_PB9_FUNC_I2C4_SDA 0x1907 -#define STM32H7_PB9_FUNC_SDMMC1_CDIR 0x1908 -#define STM32H7_PB9_FUNC_UART4_TX 0x1909 -#define STM32H7_PB9_FUNC_CAN1_TX 0x190a -#define STM32H7_PB9_FUNC_SDMMC2_D5 0x190b -#define STM32H7_PB9_FUNC_I2C4_SMBA 0x190c -#define STM32H7_PB9_FUNC_SDMMC1_D5 0x190d -#define STM32H7_PB9_FUNC_DCMI_D7 0x190e -#define STM32H7_PB9_FUNC_LCD_B7 0x190f -#define STM32H7_PB9_FUNC_EVENTOUT 0x1910 -#define STM32H7_PB9_FUNC_ANALOG 0x1911 - -#define STM32H7_PB10_FUNC_GPIO 0x1a00 -#define STM32H7_PB10_FUNC_TIM2_CH3 0x1a02 -#define STM32H7_PB10_FUNC_HRTIM_SCOUT 0x1a03 -#define STM32H7_PB10_FUNC_LPTIM2_IN1 0x1a04 -#define STM32H7_PB10_FUNC_I2C2_SCL 0x1a05 -#define STM32H7_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 -#define STM32H7_PB10_FUNC_DFSDM_DATIN7 0x1a07 -#define STM32H7_PB10_FUNC_USART3_TX 0x1a08 -#define STM32H7_PB10_FUNC_QUADSPI_BK1_NCS 0x1a0a -#define STM32H7_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b -#define STM32H7_PB10_FUNC_ETH_MII_RX_ER 0x1a0c -#define STM32H7_PB10_FUNC_LCD_G4 0x1a0f -#define STM32H7_PB10_FUNC_EVENTOUT 0x1a10 -#define STM32H7_PB10_FUNC_ANALOG 0x1a11 - -#define STM32H7_PB11_FUNC_GPIO 0x1b00 -#define STM32H7_PB11_FUNC_TIM2_CH4 0x1b02 -#define STM32H7_PB11_FUNC_HRTIM_SCIN 0x1b03 -#define STM32H7_PB11_FUNC_LPTIM2_ETR 0x1b04 -#define STM32H7_PB11_FUNC_I2C2_SDA 0x1b05 -#define STM32H7_PB11_FUNC_DFSDM_CKIN7 0x1b07 -#define STM32H7_PB11_FUNC_USART3_RX 0x1b08 -#define STM32H7_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b -#define STM32H7_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c -#define STM32H7_PB11_FUNC_DSI_TE 0x1b0e -#define STM32H7_PB11_FUNC_LCD_G5 0x1b0f -#define STM32H7_PB11_FUNC_EVENTOUT 0x1b10 -#define STM32H7_PB11_FUNC_ANALOG 0x1b11 - -#define STM32H7_PB12_FUNC_GPIO 0x1c00 -#define STM32H7_PB12_FUNC_TIM1_BKIN 0x1c02 -#define STM32H7_PB12_FUNC_I2C2_SMBA 0x1c05 -#define STM32H7_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 -#define STM32H7_PB12_FUNC_DFSDM_DATIN1 0x1c07 -#define STM32H7_PB12_FUNC_USART3_CK 0x1c08 -#define STM32H7_PB12_FUNC_CAN2_RX 0x1c0a -#define STM32H7_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b -#define STM32H7_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c -#define STM32H7_PB12_FUNC_OTG_HS_ID 0x1c0d -#define STM32H7_PB12_FUNC_TIM1_BKIN_COMP12 0x1c0e -#define STM32H7_PB12_FUNC_UART5_RX 0x1c0f -#define STM32H7_PB12_FUNC_EVENTOUT 0x1c10 -#define STM32H7_PB12_FUNC_ANALOG 0x1c11 - -#define STM32H7_PB13_FUNC_GPIO 0x1d00 -#define STM32H7_PB13_FUNC_TIM1_CH1N 0x1d02 -#define STM32H7_PB13_FUNC_LPTIM2_OUT 0x1d04 -#define STM32H7_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 -#define STM32H7_PB13_FUNC_DFSDM_CKIN1 0x1d07 -#define STM32H7_PB13_FUNC_USART3_CTS_NSS 0x1d08 -#define STM32H7_PB13_FUNC_CAN2_TX 0x1d0a -#define STM32H7_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b -#define STM32H7_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c -#define STM32H7_PB13_FUNC_UART5_TX 0x1d0f -#define STM32H7_PB13_FUNC_EVENTOUT 0x1d10 -#define STM32H7_PB13_FUNC_ANALOG 0x1d11 - -#define STM32H7_PB14_FUNC_GPIO 0x1e00 -#define STM32H7_PB14_FUNC_TIM1_CH2N 0x1e02 -#define STM32H7_PB14_FUNC_TIM8_CH2N 0x1e04 -#define STM32H7_PB14_FUNC_USART1_TX 0x1e05 -#define STM32H7_PB14_FUNC_SPI2_MISO_I2S2_SDI 0x1e06 -#define STM32H7_PB14_FUNC_DFSDM_DATIN2 0x1e07 -#define STM32H7_PB14_FUNC_USART3_RTS 0x1e08 -#define STM32H7_PB14_FUNC_UART4_RTS 0x1e09 -#define STM32H7_PB14_FUNC_SDMMC2_D0 0x1e0a -#define STM32H7_PB14_FUNC_OTG_HS_DM 0x1e0d -#define STM32H7_PB14_FUNC_EVENTOUT 0x1e10 -#define STM32H7_PB14_FUNC_ANALOG 0x1e11 - -#define STM32H7_PB15_FUNC_GPIO 0x1f00 -#define STM32H7_PB15_FUNC_RTC_REFIN 0x1f01 -#define STM32H7_PB15_FUNC_TIM1_CH3N 0x1f02 -#define STM32H7_PB15_FUNC_TIM8_CH3N 0x1f04 -#define STM32H7_PB15_FUNC_USART1_RX 0x1f05 -#define STM32H7_PB15_FUNC_SPI2_MOSI_I2S2_SDO 0x1f06 -#define STM32H7_PB15_FUNC_DFSDM_CKIN2 0x1f07 -#define STM32H7_PB15_FUNC_UART4_CTS 0x1f09 -#define STM32H7_PB15_FUNC_SDMMC2_D1 0x1f0a -#define STM32H7_PB15_FUNC_OTG_HS_DP 0x1f0d -#define STM32H7_PB15_FUNC_EVENTOUT 0x1f10 -#define STM32H7_PB15_FUNC_ANALOG 0x1f11 - -#define STM32H7_PC0_FUNC_GPIO 0x2000 -#define STM32H7_PC0_FUNC_DFSDM_CKIN0 0x2004 -#define STM32H7_PC0_FUNC_DFSDM_DATIN4 0x2007 -#define STM32H7_PC0_FUNC_SAI2_FS_B 0x2009 -#define STM32H7_PC0_FUNC_OTG_HS_ULPI_STP 0x200b -#define STM32H7_PC0_FUNC_FMC_SDNWE 0x200d -#define STM32H7_PC0_FUNC_LCD_R5 0x200f -#define STM32H7_PC0_FUNC_EVENTOUT 0x2010 -#define STM32H7_PC0_FUNC_ANALOG 0x2011 - -#define STM32H7_PC1_FUNC_GPIO 0x2100 -#define STM32H7_PC1_FUNC_TRACED0 0x2101 -#define STM32H7_PC1_FUNC_SAI1_D1 0x2103 -#define STM32H7_PC1_FUNC_DFSDM_DATIN0 0x2104 -#define STM32H7_PC1_FUNC_DFSDM_CKIN4 0x2105 -#define STM32H7_PC1_FUNC_SPI2_MOSI_I2S2_SDO 0x2106 -#define STM32H7_PC1_FUNC_SAI1_SD_A 0x2107 -#define STM32H7_PC1_FUNC_SAI4_SD_A 0x2109 -#define STM32H7_PC1_FUNC_SDMMC2_CK 0x210a -#define STM32H7_PC1_FUNC_SAI4_D1 0x210b -#define STM32H7_PC1_FUNC_ETH_MDC 0x210c -#define STM32H7_PC1_FUNC_MDIOS_MDC 0x210d -#define STM32H7_PC1_FUNC_EVENTOUT 0x2110 -#define STM32H7_PC1_FUNC_ANALOG 0x2111 - -#define STM32H7_PC2_FUNC_GPIO 0x2200 -#define STM32H7_PC2_FUNC_DFSDM_CKIN1 0x2204 -#define STM32H7_PC2_FUNC_SPI2_MISO_I2S2_SDI 0x2206 -#define STM32H7_PC2_FUNC_DFSDM_CKOUT 0x2207 -#define STM32H7_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b -#define STM32H7_PC2_FUNC_ETH_MII_TXD2 0x220c -#define STM32H7_PC2_FUNC_FMC_SDNE0 0x220d -#define STM32H7_PC2_FUNC_EVENTOUT 0x2210 -#define STM32H7_PC2_FUNC_ANALOG 0x2211 - -#define STM32H7_PC3_FUNC_GPIO 0x2300 -#define STM32H7_PC3_FUNC_DFSDM_DATIN1 0x2304 -#define STM32H7_PC3_FUNC_SPI2_MOSI_I2S2_SDO 0x2306 -#define STM32H7_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b -#define STM32H7_PC3_FUNC_ETH_MII_TX_CLK 0x230c -#define STM32H7_PC3_FUNC_FMC_SDCKE0 0x230d -#define STM32H7_PC3_FUNC_EVENTOUT 0x2310 -#define STM32H7_PC3_FUNC_ANALOG 0x2311 - -#define STM32H7_PC4_FUNC_GPIO 0x2400 -#define STM32H7_PC4_FUNC_DFSDM_CKIN2 0x2404 -#define STM32H7_PC4_FUNC_I2S1_MCK 0x2406 -#define STM32H7_PC4_FUNC_SPDIFRX_IN2 0x240a -#define STM32H7_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c -#define STM32H7_PC4_FUNC_FMC_SDNE0 0x240d -#define STM32H7_PC4_FUNC_EVENTOUT 0x2410 -#define STM32H7_PC4_FUNC_ANALOG 0x2411 - -#define STM32H7_PC5_FUNC_GPIO 0x2500 -#define STM32H7_PC5_FUNC_SAI1_D3 0x2503 -#define STM32H7_PC5_FUNC_DFSDM_DATIN2 0x2504 -#define STM32H7_PC5_FUNC_SPDIFRX_IN3 0x250a -#define STM32H7_PC5_FUNC_SAI4_D3 0x250b -#define STM32H7_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c -#define STM32H7_PC5_FUNC_FMC_SDCKE0 0x250d -#define STM32H7_PC5_FUNC_COMP_1_OUT 0x250e -#define STM32H7_PC5_FUNC_EVENTOUT 0x2510 -#define STM32H7_PC5_FUNC_ANALOG 0x2511 - -#define STM32H7_PC6_FUNC_GPIO 0x2600 -#define STM32H7_PC6_FUNC_HRTIM_CHA1 0x2602 -#define STM32H7_PC6_FUNC_TIM3_CH1 0x2603 -#define STM32H7_PC6_FUNC_TIM8_CH1 0x2604 -#define STM32H7_PC6_FUNC_DFSDM_CKIN3 0x2605 -#define STM32H7_PC6_FUNC_I2S2_MCK 0x2606 -#define STM32H7_PC6_FUNC_USART6_TX 0x2608 -#define STM32H7_PC6_FUNC_SDMMC1_D0DIR 0x2609 -#define STM32H7_PC6_FUNC_FMC_NWAIT 0x260a -#define STM32H7_PC6_FUNC_SDMMC2_D6 0x260b -#define STM32H7_PC6_FUNC_SDMMC1_D6 0x260d -#define STM32H7_PC6_FUNC_DCMI_D0 0x260e -#define STM32H7_PC6_FUNC_LCD_HSYNC 0x260f -#define STM32H7_PC6_FUNC_EVENTOUT 0x2610 -#define STM32H7_PC6_FUNC_ANALOG 0x2611 - -#define STM32H7_PC7_FUNC_GPIO 0x2700 -#define STM32H7_PC7_FUNC_TRGIO 0x2701 -#define STM32H7_PC7_FUNC_HRTIM_CHA2 0x2702 -#define STM32H7_PC7_FUNC_TIM3_CH2 0x2703 -#define STM32H7_PC7_FUNC_TIM8_CH2 0x2704 -#define STM32H7_PC7_FUNC_DFSDM_DATIN3 0x2705 -#define STM32H7_PC7_FUNC_I2S3_MCK 0x2707 -#define STM32H7_PC7_FUNC_USART6_RX 0x2708 -#define STM32H7_PC7_FUNC_SDMMC1_D123DIR 0x2709 -#define STM32H7_PC7_FUNC_FMC_NE1 0x270a -#define STM32H7_PC7_FUNC_SDMMC2_D7 0x270b -#define STM32H7_PC7_FUNC_SWPMI_TX 0x270c -#define STM32H7_PC7_FUNC_SDMMC1_D7 0x270d -#define STM32H7_PC7_FUNC_DCMI_D1 0x270e -#define STM32H7_PC7_FUNC_LCD_G6 0x270f -#define STM32H7_PC7_FUNC_EVENTOUT 0x2710 -#define STM32H7_PC7_FUNC_ANALOG 0x2711 - -#define STM32H7_PC8_FUNC_GPIO 0x2800 -#define STM32H7_PC8_FUNC_TRACED1 0x2801 -#define STM32H7_PC8_FUNC_HRTIM_CHB1 0x2802 -#define STM32H7_PC8_FUNC_TIM3_CH3 0x2803 -#define STM32H7_PC8_FUNC_TIM8_CH3 0x2804 -#define STM32H7_PC8_FUNC_USART6_CK 0x2808 -#define STM32H7_PC8_FUNC_UART5_RTS 0x2809 -#define STM32H7_PC8_FUNC_FMC_NE2_FMC_NCE 0x280a -#define STM32H7_PC8_FUNC_SWPMI_RX 0x280c -#define STM32H7_PC8_FUNC_SDMMC1_D0 0x280d -#define STM32H7_PC8_FUNC_DCMI_D2 0x280e -#define STM32H7_PC8_FUNC_EVENTOUT 0x2810 -#define STM32H7_PC8_FUNC_ANALOG 0x2811 - -#define STM32H7_PC9_FUNC_GPIO 0x2900 -#define STM32H7_PC9_FUNC_MCO2 0x2901 -#define STM32H7_PC9_FUNC_TIM3_CH4 0x2903 -#define STM32H7_PC9_FUNC_TIM8_CH4 0x2904 -#define STM32H7_PC9_FUNC_I2C3_SDA 0x2905 -#define STM32H7_PC9_FUNC_I2S_CKIN 0x2906 -#define STM32H7_PC9_FUNC_UART5_CTS 0x2909 -#define STM32H7_PC9_FUNC_QUADSPI_BK1_IO0 0x290a -#define STM32H7_PC9_FUNC_LCD_G3 0x290b -#define STM32H7_PC9_FUNC_SWPMI_SUSPEND 0x290c -#define STM32H7_PC9_FUNC_SDMMC1_D1 0x290d -#define STM32H7_PC9_FUNC_DCMI_D3 0x290e -#define STM32H7_PC9_FUNC_LCD_B2 0x290f -#define STM32H7_PC9_FUNC_EVENTOUT 0x2910 -#define STM32H7_PC9_FUNC_ANALOG 0x2911 - -#define STM32H7_PC10_FUNC_GPIO 0x2a00 -#define STM32H7_PC10_FUNC_HRTIM_EEV1 0x2a03 -#define STM32H7_PC10_FUNC_DFSDM_CKIN5 0x2a04 -#define STM32H7_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 -#define STM32H7_PC10_FUNC_USART3_TX 0x2a08 -#define STM32H7_PC10_FUNC_UART4_TX 0x2a09 -#define STM32H7_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a -#define STM32H7_PC10_FUNC_SDMMC1_D2 0x2a0d -#define STM32H7_PC10_FUNC_DCMI_D8 0x2a0e -#define STM32H7_PC10_FUNC_LCD_R2 0x2a0f -#define STM32H7_PC10_FUNC_EVENTOUT 0x2a10 -#define STM32H7_PC10_FUNC_ANALOG 0x2a11 - -#define STM32H7_PC11_FUNC_GPIO 0x2b00 -#define STM32H7_PC11_FUNC_HRTIM_FLT2 0x2b03 -#define STM32H7_PC11_FUNC_DFSDM_DATIN5 0x2b04 -#define STM32H7_PC11_FUNC_SPI3_MISO_I2S3_SDI 0x2b07 -#define STM32H7_PC11_FUNC_USART3_RX 0x2b08 -#define STM32H7_PC11_FUNC_UART4_RX 0x2b09 -#define STM32H7_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a -#define STM32H7_PC11_FUNC_SDMMC1_D3 0x2b0d -#define STM32H7_PC11_FUNC_DCMI_D4 0x2b0e -#define STM32H7_PC11_FUNC_EVENTOUT 0x2b10 -#define STM32H7_PC11_FUNC_ANALOG 0x2b11 - -#define STM32H7_PC12_FUNC_GPIO 0x2c00 -#define STM32H7_PC12_FUNC_TRACED3 0x2c01 -#define STM32H7_PC12_FUNC_HRTIM_EEV2 0x2c03 -#define STM32H7_PC12_FUNC_SPI3_MOSI_I2S3_SDO 0x2c07 -#define STM32H7_PC12_FUNC_USART3_CK 0x2c08 -#define STM32H7_PC12_FUNC_UART5_TX 0x2c09 -#define STM32H7_PC12_FUNC_SDMMC1_CK 0x2c0d -#define STM32H7_PC12_FUNC_DCMI_D9 0x2c0e -#define STM32H7_PC12_FUNC_EVENTOUT 0x2c10 -#define STM32H7_PC12_FUNC_ANALOG 0x2c11 - -#define STM32H7_PC13_FUNC_GPIO 0x2d00 -#define STM32H7_PC13_FUNC_EVENTOUT 0x2d10 -#define STM32H7_PC13_FUNC_ANALOG 0x2d11 - -#define STM32H7_PC14_FUNC_GPIO 0x2e00 -#define STM32H7_PC14_FUNC_EVENTOUT 0x2e10 -#define STM32H7_PC14_FUNC_ANALOG 0x2e11 - -#define STM32H7_PC15_FUNC_GPIO 0x2f00 -#define STM32H7_PC15_FUNC_EVENTOUT 0x2f10 -#define STM32H7_PC15_FUNC_ANALOG 0x2f11 - -#define STM32H7_PD0_FUNC_GPIO 0x3000 -#define STM32H7_PD0_FUNC_DFSDM_CKIN6 0x3004 -#define STM32H7_PD0_FUNC_SAI3_SCK_A 0x3007 -#define STM32H7_PD0_FUNC_UART4_RX 0x3009 -#define STM32H7_PD0_FUNC_CAN1_RX 0x300a -#define STM32H7_PD0_FUNC_FMC_D2_FMC_DA2 0x300d -#define STM32H7_PD0_FUNC_EVENTOUT 0x3010 -#define STM32H7_PD0_FUNC_ANALOG 0x3011 - -#define STM32H7_PD1_FUNC_GPIO 0x3100 -#define STM32H7_PD1_FUNC_DFSDM_DATIN6 0x3104 -#define STM32H7_PD1_FUNC_SAI3_SD_A 0x3107 -#define STM32H7_PD1_FUNC_UART4_TX 0x3109 -#define STM32H7_PD1_FUNC_CAN1_TX 0x310a -#define STM32H7_PD1_FUNC_FMC_D3_FMC_DA3 0x310d -#define STM32H7_PD1_FUNC_EVENTOUT 0x3110 -#define STM32H7_PD1_FUNC_ANALOG 0x3111 - -#define STM32H7_PD2_FUNC_GPIO 0x3200 -#define STM32H7_PD2_FUNC_TRACED2 0x3201 -#define STM32H7_PD2_FUNC_TIM3_ETR 0x3203 -#define STM32H7_PD2_FUNC_UART5_RX 0x3209 -#define STM32H7_PD2_FUNC_SDMMC1_CMD 0x320d -#define STM32H7_PD2_FUNC_DCMI_D11 0x320e -#define STM32H7_PD2_FUNC_EVENTOUT 0x3210 -#define STM32H7_PD2_FUNC_ANALOG 0x3211 - -#define STM32H7_PD3_FUNC_GPIO 0x3300 -#define STM32H7_PD3_FUNC_DFSDM_CKOUT 0x3304 -#define STM32H7_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 -#define STM32H7_PD3_FUNC_USART2_CTS_NSS 0x3308 -#define STM32H7_PD3_FUNC_FMC_CLK 0x330d -#define STM32H7_PD3_FUNC_DCMI_D5 0x330e -#define STM32H7_PD3_FUNC_LCD_G7 0x330f -#define STM32H7_PD3_FUNC_EVENTOUT 0x3310 -#define STM32H7_PD3_FUNC_ANALOG 0x3311 - -#define STM32H7_PD4_FUNC_GPIO 0x3400 -#define STM32H7_PD4_FUNC_HRTIM_FLT3 0x3403 -#define STM32H7_PD4_FUNC_SAI3_FS_A 0x3407 -#define STM32H7_PD4_FUNC_USART2_RTS 0x3408 -#define STM32H7_PD4_FUNC_CAN1_RXFD 0x340a -#define STM32H7_PD4_FUNC_FMC_NOE 0x340d -#define STM32H7_PD4_FUNC_EVENTOUT 0x3410 -#define STM32H7_PD4_FUNC_ANALOG 0x3411 - -#define STM32H7_PD5_FUNC_GPIO 0x3500 -#define STM32H7_PD5_FUNC_HRTIM_EEV3 0x3503 -#define STM32H7_PD5_FUNC_USART2_TX 0x3508 -#define STM32H7_PD5_FUNC_CAN1_TXFD 0x350a -#define STM32H7_PD5_FUNC_FMC_NWE 0x350d -#define STM32H7_PD5_FUNC_EVENTOUT 0x3510 -#define STM32H7_PD5_FUNC_ANALOG 0x3511 - -#define STM32H7_PD6_FUNC_GPIO 0x3600 -#define STM32H7_PD6_FUNC_SAI1_D1 0x3603 -#define STM32H7_PD6_FUNC_DFSDM_CKIN4 0x3604 -#define STM32H7_PD6_FUNC_DFSDM_DATIN1 0x3605 -#define STM32H7_PD6_FUNC_SPI3_MOSI_I2S3_SDO 0x3606 -#define STM32H7_PD6_FUNC_SAI1_SD_A 0x3607 -#define STM32H7_PD6_FUNC_USART2_RX 0x3608 -#define STM32H7_PD6_FUNC_SAI4_SD_A 0x3609 -#define STM32H7_PD6_FUNC_CAN2_RXFD 0x360a -#define STM32H7_PD6_FUNC_SAI4_D1 0x360b -#define STM32H7_PD6_FUNC_SDMMC2_CK 0x360c -#define STM32H7_PD6_FUNC_FMC_NWAIT 0x360d -#define STM32H7_PD6_FUNC_DCMI_D10 0x360e -#define STM32H7_PD6_FUNC_LCD_B2 0x360f -#define STM32H7_PD6_FUNC_EVENTOUT 0x3610 -#define STM32H7_PD6_FUNC_ANALOG 0x3611 - -#define STM32H7_PD7_FUNC_GPIO 0x3700 -#define STM32H7_PD7_FUNC_DFSDM_DATIN4 0x3704 -#define STM32H7_PD7_FUNC_SPI1_MOSI_I2S1_SDO 0x3706 -#define STM32H7_PD7_FUNC_DFSDM_CKIN1 0x3707 -#define STM32H7_PD7_FUNC_USART2_CK 0x3708 -#define STM32H7_PD7_FUNC_SPDIFRX_IN0 0x370a -#define STM32H7_PD7_FUNC_SDMMC2_CMD 0x370c -#define STM32H7_PD7_FUNC_FMC_NE1 0x370d -#define STM32H7_PD7_FUNC_EVENTOUT 0x3710 -#define STM32H7_PD7_FUNC_ANALOG 0x3711 - -#define STM32H7_PD8_FUNC_GPIO 0x3800 -#define STM32H7_PD8_FUNC_DFSDM_CKIN3 0x3804 -#define STM32H7_PD8_FUNC_SAI3_SCK_B 0x3807 -#define STM32H7_PD8_FUNC_USART3_TX 0x3808 -#define STM32H7_PD8_FUNC_SPDIFRX_IN1 0x380a -#define STM32H7_PD8_FUNC_FMC_D13_FMC_DA13 0x380d -#define STM32H7_PD8_FUNC_EVENTOUT 0x3810 -#define STM32H7_PD8_FUNC_ANALOG 0x3811 - -#define STM32H7_PD9_FUNC_GPIO 0x3900 -#define STM32H7_PD9_FUNC_DFSDM_DATIN3 0x3904 -#define STM32H7_PD9_FUNC_SAI3_SD_B 0x3907 -#define STM32H7_PD9_FUNC_USART3_RX 0x3908 -#define STM32H7_PD9_FUNC_CAN2_RXFD 0x390a -#define STM32H7_PD9_FUNC_FMC_D14_FMC_DA14 0x390d -#define STM32H7_PD9_FUNC_EVENTOUT 0x3910 -#define STM32H7_PD9_FUNC_ANALOG 0x3911 - -#define STM32H7_PD10_FUNC_GPIO 0x3a00 -#define STM32H7_PD10_FUNC_DFSDM_CKOUT 0x3a04 -#define STM32H7_PD10_FUNC_SAI3_FS_B 0x3a07 -#define STM32H7_PD10_FUNC_USART3_CK 0x3a08 -#define STM32H7_PD10_FUNC_CAN2_TXFD 0x3a0a -#define STM32H7_PD10_FUNC_FMC_D15_FMC_DA15 0x3a0d -#define STM32H7_PD10_FUNC_LCD_B3 0x3a0f -#define STM32H7_PD10_FUNC_EVENTOUT 0x3a10 -#define STM32H7_PD10_FUNC_ANALOG 0x3a11 - -#define STM32H7_PD11_FUNC_GPIO 0x3b00 -#define STM32H7_PD11_FUNC_LPTIM2_IN2 0x3b04 -#define STM32H7_PD11_FUNC_I2C4_SMBA 0x3b05 -#define STM32H7_PD11_FUNC_USART3_CTS_NSS 0x3b08 -#define STM32H7_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a -#define STM32H7_PD11_FUNC_SAI2_SD_A 0x3b0b -#define STM32H7_PD11_FUNC_FMC_A16 0x3b0d -#define STM32H7_PD11_FUNC_EVENTOUT 0x3b10 -#define STM32H7_PD11_FUNC_ANALOG 0x3b11 - -#define STM32H7_PD12_FUNC_GPIO 0x3c00 -#define STM32H7_PD12_FUNC_LPTIM1_IN1 0x3c02 -#define STM32H7_PD12_FUNC_TIM4_CH1 0x3c03 -#define STM32H7_PD12_FUNC_LPTIM2_IN1 0x3c04 -#define STM32H7_PD12_FUNC_I2C4_SCL 0x3c05 -#define STM32H7_PD12_FUNC_USART3_RTS 0x3c08 -#define STM32H7_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a -#define STM32H7_PD12_FUNC_SAI2_FS_A 0x3c0b -#define STM32H7_PD12_FUNC_FMC_A17 0x3c0d -#define STM32H7_PD12_FUNC_EVENTOUT 0x3c10 -#define STM32H7_PD12_FUNC_ANALOG 0x3c11 - -#define STM32H7_PD13_FUNC_GPIO 0x3d00 -#define STM32H7_PD13_FUNC_LPTIM1_OUT 0x3d02 -#define STM32H7_PD13_FUNC_TIM4_CH2 0x3d03 -#define STM32H7_PD13_FUNC_I2C4_SDA 0x3d05 -#define STM32H7_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a -#define STM32H7_PD13_FUNC_SAI2_SCK_A 0x3d0b -#define STM32H7_PD13_FUNC_FMC_A18 0x3d0d -#define STM32H7_PD13_FUNC_EVENTOUT 0x3d10 -#define STM32H7_PD13_FUNC_ANALOG 0x3d11 - -#define STM32H7_PD14_FUNC_GPIO 0x3e00 -#define STM32H7_PD14_FUNC_TIM4_CH3 0x3e03 -#define STM32H7_PD14_FUNC_SAI3_MCLK_B 0x3e07 -#define STM32H7_PD14_FUNC_UART8_CTS 0x3e09 -#define STM32H7_PD14_FUNC_FMC_D0_FMC_DA0 0x3e0d -#define STM32H7_PD14_FUNC_EVENTOUT 0x3e10 -#define STM32H7_PD14_FUNC_ANALOG 0x3e11 - -#define STM32H7_PD15_FUNC_GPIO 0x3f00 -#define STM32H7_PD15_FUNC_TIM4_CH4 0x3f03 -#define STM32H7_PD15_FUNC_SAI3_MCLK_A 0x3f07 -#define STM32H7_PD15_FUNC_UART8_RTS 0x3f09 -#define STM32H7_PD15_FUNC_FMC_D1_FMC_DA1 0x3f0d -#define STM32H7_PD15_FUNC_EVENTOUT 0x3f10 -#define STM32H7_PD15_FUNC_ANALOG 0x3f11 - -#define STM32H7_PE0_FUNC_GPIO 0x4000 -#define STM32H7_PE0_FUNC_LPTIM1_ETR 0x4002 -#define STM32H7_PE0_FUNC_TIM4_ETR 0x4003 -#define STM32H7_PE0_FUNC_HRTIM_SCIN 0x4004 -#define STM32H7_PE0_FUNC_LPTIM2_ETR 0x4005 -#define STM32H7_PE0_FUNC_UART8_RX 0x4009 -#define STM32H7_PE0_FUNC_CAN1_RXFD 0x400a -#define STM32H7_PE0_FUNC_SAI2_MCK_A 0x400b -#define STM32H7_PE0_FUNC_FMC_NBL0 0x400d -#define STM32H7_PE0_FUNC_DCMI_D2 0x400e -#define STM32H7_PE0_FUNC_EVENTOUT 0x4010 -#define STM32H7_PE0_FUNC_ANALOG 0x4011 - -#define STM32H7_PE1_FUNC_GPIO 0x4100 -#define STM32H7_PE1_FUNC_LPTIM1_IN2 0x4102 -#define STM32H7_PE1_FUNC_HRTIM_SCOUT 0x4104 -#define STM32H7_PE1_FUNC_UART8_TX 0x4109 -#define STM32H7_PE1_FUNC_CAN1_TXFD 0x410a -#define STM32H7_PE1_FUNC_FMC_NBL1 0x410d -#define STM32H7_PE1_FUNC_DCMI_D3 0x410e -#define STM32H7_PE1_FUNC_EVENTOUT 0x4110 -#define STM32H7_PE1_FUNC_ANALOG 0x4111 - -#define STM32H7_PE2_FUNC_GPIO 0x4200 -#define STM32H7_PE2_FUNC_TRACECLK 0x4201 -#define STM32H7_PE2_FUNC_SAI1_CK1 0x4203 -#define STM32H7_PE2_FUNC_SPI4_SCK 0x4206 -#define STM32H7_PE2_FUNC_SAI1_MCLK_A 0x4207 -#define STM32H7_PE2_FUNC_SAI4_MCLK_A 0x4209 -#define STM32H7_PE2_FUNC_QUADSPI_BK1_IO2 0x420a -#define STM32H7_PE2_FUNC_SAI4_CK1 0x420b -#define STM32H7_PE2_FUNC_ETH_MII_TXD3 0x420c -#define STM32H7_PE2_FUNC_FMC_A23 0x420d -#define STM32H7_PE2_FUNC_EVENTOUT 0x4210 -#define STM32H7_PE2_FUNC_ANALOG 0x4211 - -#define STM32H7_PE3_FUNC_GPIO 0x4300 -#define STM32H7_PE3_FUNC_TRACED0 0x4301 -#define STM32H7_PE3_FUNC_TIM15_BKIN 0x4305 -#define STM32H7_PE3_FUNC_SAI1_SD_B 0x4307 -#define STM32H7_PE3_FUNC_SAI4_SD_B 0x4309 -#define STM32H7_PE3_FUNC_FMC_A19 0x430d -#define STM32H7_PE3_FUNC_EVENTOUT 0x4310 -#define STM32H7_PE3_FUNC_ANALOG 0x4311 - -#define STM32H7_PE4_FUNC_GPIO 0x4400 -#define STM32H7_PE4_FUNC_TRACED1 0x4401 -#define STM32H7_PE4_FUNC_SAI1_D2 0x4403 -#define STM32H7_PE4_FUNC_DFSDM_DATIN3 0x4404 -#define STM32H7_PE4_FUNC_TIM15_CH1N 0x4405 -#define STM32H7_PE4_FUNC_SPI4_NSS 0x4406 -#define STM32H7_PE4_FUNC_SAI1_FS_A 0x4407 -#define STM32H7_PE4_FUNC_SAI4_FS_A 0x4409 -#define STM32H7_PE4_FUNC_SAI4_D2 0x440b -#define STM32H7_PE4_FUNC_FMC_A20 0x440d -#define STM32H7_PE4_FUNC_DCMI_D4 0x440e -#define STM32H7_PE4_FUNC_LCD_B0 0x440f -#define STM32H7_PE4_FUNC_EVENTOUT 0x4410 -#define STM32H7_PE4_FUNC_ANALOG 0x4411 - -#define STM32H7_PE5_FUNC_GPIO 0x4500 -#define STM32H7_PE5_FUNC_TRACED2 0x4501 -#define STM32H7_PE5_FUNC_SAI1_CK2 0x4503 -#define STM32H7_PE5_FUNC_DFSDM_CKIN3 0x4504 -#define STM32H7_PE5_FUNC_TIM15_CH1 0x4505 -#define STM32H7_PE5_FUNC_SPI4_MISO 0x4506 -#define STM32H7_PE5_FUNC_SAI1_SCK_A 0x4507 -#define STM32H7_PE5_FUNC_SAI4_SCK_A 0x4509 -#define STM32H7_PE5_FUNC_SAI4_CK2 0x450b -#define STM32H7_PE5_FUNC_FMC_A21 0x450d -#define STM32H7_PE5_FUNC_DCMI_D6 0x450e -#define STM32H7_PE5_FUNC_LCD_G0 0x450f -#define STM32H7_PE5_FUNC_EVENTOUT 0x4510 -#define STM32H7_PE5_FUNC_ANALOG 0x4511 - -#define STM32H7_PE6_FUNC_GPIO 0x4600 -#define STM32H7_PE6_FUNC_TRACED3 0x4601 -#define STM32H7_PE6_FUNC_TIM1_BKIN2 0x4602 -#define STM32H7_PE6_FUNC_SAI1_D1 0x4603 -#define STM32H7_PE6_FUNC_TIM15_CH2 0x4605 -#define STM32H7_PE6_FUNC_SPI4_MOSI 0x4606 -#define STM32H7_PE6_FUNC_SAI1_SD_A 0x4607 -#define STM32H7_PE6_FUNC_SAI4_SD_A 0x4609 -#define STM32H7_PE6_FUNC_SAI4_D1 0x460a -#define STM32H7_PE6_FUNC_SAI2_MCK_B 0x460b -#define STM32H7_PE6_FUNC_TIM1_BKIN2_COMP12 0x460c -#define STM32H7_PE6_FUNC_FMC_A22 0x460d -#define STM32H7_PE6_FUNC_DCMI_D7 0x460e -#define STM32H7_PE6_FUNC_LCD_G1 0x460f -#define STM32H7_PE6_FUNC_EVENTOUT 0x4610 -#define STM32H7_PE6_FUNC_ANALOG 0x4611 - -#define STM32H7_PE7_FUNC_GPIO 0x4700 -#define STM32H7_PE7_FUNC_TIM1_ETR 0x4702 -#define STM32H7_PE7_FUNC_DFSDM_DATIN2 0x4704 -#define STM32H7_PE7_FUNC_UART7_RX 0x4708 -#define STM32H7_PE7_FUNC_QUADSPI_BK2_IO0 0x470b -#define STM32H7_PE7_FUNC_FMC_D4_FMC_DA4 0x470d -#define STM32H7_PE7_FUNC_EVENTOUT 0x4710 -#define STM32H7_PE7_FUNC_ANALOG 0x4711 - -#define STM32H7_PE8_FUNC_GPIO 0x4800 -#define STM32H7_PE8_FUNC_TIM1_CH1N 0x4802 -#define STM32H7_PE8_FUNC_DFSDM_CKIN2 0x4804 -#define STM32H7_PE8_FUNC_UART7_TX 0x4808 -#define STM32H7_PE8_FUNC_QUADSPI_BK2_IO1 0x480b -#define STM32H7_PE8_FUNC_FMC_D5_FMC_DA5 0x480d -#define STM32H7_PE8_FUNC_COMP_2_OUT 0x480e -#define STM32H7_PE8_FUNC_EVENTOUT 0x4810 -#define STM32H7_PE8_FUNC_ANALOG 0x4811 - -#define STM32H7_PE9_FUNC_GPIO 0x4900 -#define STM32H7_PE9_FUNC_TIM1_CH1 0x4902 -#define STM32H7_PE9_FUNC_DFSDM_CKOUT 0x4904 -#define STM32H7_PE9_FUNC_UART7_RTS 0x4908 -#define STM32H7_PE9_FUNC_QUADSPI_BK2_IO2 0x490b -#define STM32H7_PE9_FUNC_FMC_D6_FMC_DA6 0x490d -#define STM32H7_PE9_FUNC_EVENTOUT 0x4910 -#define STM32H7_PE9_FUNC_ANALOG 0x4911 - -#define STM32H7_PE10_FUNC_GPIO 0x4a00 -#define STM32H7_PE10_FUNC_TIM1_CH2N 0x4a02 -#define STM32H7_PE10_FUNC_DFSDM_DATIN4 0x4a04 -#define STM32H7_PE10_FUNC_UART7_CTS 0x4a08 -#define STM32H7_PE10_FUNC_QUADSPI_BK2_IO3 0x4a0b -#define STM32H7_PE10_FUNC_FMC_D7_FMC_DA7 0x4a0d -#define STM32H7_PE10_FUNC_EVENTOUT 0x4a10 -#define STM32H7_PE10_FUNC_ANALOG 0x4a11 - -#define STM32H7_PE11_FUNC_GPIO 0x4b00 -#define STM32H7_PE11_FUNC_TIM1_CH2 0x4b02 -#define STM32H7_PE11_FUNC_DFSDM_CKIN4 0x4b04 -#define STM32H7_PE11_FUNC_SPI4_NSS 0x4b06 -#define STM32H7_PE11_FUNC_SAI2_SD_B 0x4b0b -#define STM32H7_PE11_FUNC_FMC_D8_FMC_DA8 0x4b0d -#define STM32H7_PE11_FUNC_LCD_G3 0x4b0f -#define STM32H7_PE11_FUNC_EVENTOUT 0x4b10 -#define STM32H7_PE11_FUNC_ANALOG 0x4b11 - -#define STM32H7_PE12_FUNC_GPIO 0x4c00 -#define STM32H7_PE12_FUNC_TIM1_CH3N 0x4c02 -#define STM32H7_PE12_FUNC_DFSDM_DATIN5 0x4c04 -#define STM32H7_PE12_FUNC_SPI4_SCK 0x4c06 -#define STM32H7_PE12_FUNC_SAI2_SCK_B 0x4c0b -#define STM32H7_PE12_FUNC_FMC_D9_FMC_DA9 0x4c0d -#define STM32H7_PE12_FUNC_COMP_1_OUT 0x4c0e -#define STM32H7_PE12_FUNC_LCD_B4 0x4c0f -#define STM32H7_PE12_FUNC_EVENTOUT 0x4c10 -#define STM32H7_PE12_FUNC_ANALOG 0x4c11 - -#define STM32H7_PE13_FUNC_GPIO 0x4d00 -#define STM32H7_PE13_FUNC_TIM1_CH3 0x4d02 -#define STM32H7_PE13_FUNC_DFSDM_CKIN5 0x4d04 -#define STM32H7_PE13_FUNC_SPI4_MISO 0x4d06 -#define STM32H7_PE13_FUNC_SAI2_FS_B 0x4d0b -#define STM32H7_PE13_FUNC_FMC_D10_FMC_DA10 0x4d0d -#define STM32H7_PE13_FUNC_COMP_2_OUT 0x4d0e -#define STM32H7_PE13_FUNC_LCD_DE 0x4d0f -#define STM32H7_PE13_FUNC_EVENTOUT 0x4d10 -#define STM32H7_PE13_FUNC_ANALOG 0x4d11 - -#define STM32H7_PE14_FUNC_GPIO 0x4e00 -#define STM32H7_PE14_FUNC_TIM1_CH4 0x4e02 -#define STM32H7_PE14_FUNC_SPI4_MOSI 0x4e06 -#define STM32H7_PE14_FUNC_SAI2_MCK_B 0x4e0b -#define STM32H7_PE14_FUNC_FMC_D11_FMC_DA11 0x4e0d -#define STM32H7_PE14_FUNC_LCD_CLK 0x4e0f -#define STM32H7_PE14_FUNC_EVENTOUT 0x4e10 -#define STM32H7_PE14_FUNC_ANALOG 0x4e11 - -#define STM32H7_PE15_FUNC_GPIO 0x4f00 -#define STM32H7_PE15_FUNC_TIM1_BKIN 0x4f02 -#define STM32H7_PE15_FUNC_HDMI__TIM1_BKIN 0x4f06 -#define STM32H7_PE15_FUNC_FMC_D12_FMC_DA12 0x4f0d -#define STM32H7_PE15_FUNC_TIM1_BKIN_COMP12 0x4f0e -#define STM32H7_PE15_FUNC_LCD_R7 0x4f0f -#define STM32H7_PE15_FUNC_EVENTOUT 0x4f10 -#define STM32H7_PE15_FUNC_ANALOG 0x4f11 - -#define STM32H7_PF0_FUNC_GPIO 0x5000 -#define STM32H7_PF0_FUNC_I2C2_SDA 0x5005 -#define STM32H7_PF0_FUNC_FMC_A0 0x500d -#define STM32H7_PF0_FUNC_EVENTOUT 0x5010 -#define STM32H7_PF0_FUNC_ANALOG 0x5011 - -#define STM32H7_PF1_FUNC_GPIO 0x5100 -#define STM32H7_PF1_FUNC_I2C2_SCL 0x5105 -#define STM32H7_PF1_FUNC_FMC_A1 0x510d -#define STM32H7_PF1_FUNC_EVENTOUT 0x5110 -#define STM32H7_PF1_FUNC_ANALOG 0x5111 - -#define STM32H7_PF2_FUNC_GPIO 0x5200 -#define STM32H7_PF2_FUNC_I2C2_SMBA 0x5205 -#define STM32H7_PF2_FUNC_FMC_A2 0x520d -#define STM32H7_PF2_FUNC_EVENTOUT 0x5210 -#define STM32H7_PF2_FUNC_ANALOG 0x5211 - -#define STM32H7_PF3_FUNC_GPIO 0x5300 -#define STM32H7_PF3_FUNC_FMC_A3 0x530d -#define STM32H7_PF3_FUNC_EVENTOUT 0x5310 -#define STM32H7_PF3_FUNC_ANALOG 0x5311 - -#define STM32H7_PF4_FUNC_GPIO 0x5400 -#define STM32H7_PF4_FUNC_FMC_A4 0x540d -#define STM32H7_PF4_FUNC_EVENTOUT 0x5410 -#define STM32H7_PF4_FUNC_ANALOG 0x5411 - -#define STM32H7_PF5_FUNC_GPIO 0x5500 -#define STM32H7_PF5_FUNC_FMC_A5 0x550d -#define STM32H7_PF5_FUNC_EVENTOUT 0x5510 -#define STM32H7_PF5_FUNC_ANALOG 0x5511 - -#define STM32H7_PF6_FUNC_GPIO 0x5600 -#define STM32H7_PF6_FUNC_TIM16_CH1 0x5602 -#define STM32H7_PF6_FUNC_SPI5_NSS 0x5606 -#define STM32H7_PF6_FUNC_SAI1_SD_B 0x5607 -#define STM32H7_PF6_FUNC_UART7_RX 0x5608 -#define STM32H7_PF6_FUNC_SAI4_SD_B 0x5609 -#define STM32H7_PF6_FUNC_QUADSPI_BK1_IO3 0x560a -#define STM32H7_PF6_FUNC_EVENTOUT 0x5610 -#define STM32H7_PF6_FUNC_ANALOG 0x5611 - -#define STM32H7_PF7_FUNC_GPIO 0x5700 -#define STM32H7_PF7_FUNC_TIM17_CH1 0x5702 -#define STM32H7_PF7_FUNC_SPI5_SCK 0x5706 -#define STM32H7_PF7_FUNC_SAI1_MCLK_B 0x5707 -#define STM32H7_PF7_FUNC_UART7_TX 0x5708 -#define STM32H7_PF7_FUNC_SAI4_MCLK_B 0x5709 -#define STM32H7_PF7_FUNC_QUADSPI_BK1_IO2 0x570a -#define STM32H7_PF7_FUNC_EVENTOUT 0x5710 -#define STM32H7_PF7_FUNC_ANALOG 0x5711 - -#define STM32H7_PF8_FUNC_GPIO 0x5800 -#define STM32H7_PF8_FUNC_TIM16_CH1N 0x5802 -#define STM32H7_PF8_FUNC_SPI5_MISO 0x5806 -#define STM32H7_PF8_FUNC_SAI1_SCK_B 0x5807 -#define STM32H7_PF8_FUNC_UART7_RTS 0x5808 -#define STM32H7_PF8_FUNC_SAI4_SCK_B 0x5809 -#define STM32H7_PF8_FUNC_TIM13_CH1 0x580a -#define STM32H7_PF8_FUNC_QUADSPI_BK1_IO0 0x580b -#define STM32H7_PF8_FUNC_EVENTOUT 0x5810 -#define STM32H7_PF8_FUNC_ANALOG 0x5811 - -#define STM32H7_PF9_FUNC_GPIO 0x5900 -#define STM32H7_PF9_FUNC_TIM17_CH1N 0x5902 -#define STM32H7_PF9_FUNC_SPI5_MOSI 0x5906 -#define STM32H7_PF9_FUNC_SAI1_FS_B 0x5907 -#define STM32H7_PF9_FUNC_UART7_CTS 0x5908 -#define STM32H7_PF9_FUNC_SAI4_FS_B 0x5909 -#define STM32H7_PF9_FUNC_TIM14_CH1 0x590a -#define STM32H7_PF9_FUNC_QUADSPI_BK1_IO1 0x590b -#define STM32H7_PF9_FUNC_EVENTOUT 0x5910 -#define STM32H7_PF9_FUNC_ANALOG 0x5911 - -#define STM32H7_PF10_FUNC_GPIO 0x5a00 -#define STM32H7_PF10_FUNC_TIM16_BKIN 0x5a02 -#define STM32H7_PF10_FUNC_SAI1_D3 0x5a03 -#define STM32H7_PF10_FUNC_QUADSPI_CLK 0x5a0a -#define STM32H7_PF10_FUNC_SAI4_D3 0x5a0b -#define STM32H7_PF10_FUNC_DCMI_D11 0x5a0e -#define STM32H7_PF10_FUNC_LCD_DE 0x5a0f -#define STM32H7_PF10_FUNC_EVENTOUT 0x5a10 -#define STM32H7_PF10_FUNC_ANALOG 0x5a11 - -#define STM32H7_PF11_FUNC_GPIO 0x5b00 -#define STM32H7_PF11_FUNC_SPI5_MOSI 0x5b06 -#define STM32H7_PF11_FUNC_SAI2_SD_B 0x5b0b -#define STM32H7_PF11_FUNC_FMC_SDNRAS 0x5b0d -#define STM32H7_PF11_FUNC_DCMI_D12 0x5b0e -#define STM32H7_PF11_FUNC_EVENTOUT 0x5b10 -#define STM32H7_PF11_FUNC_ANALOG 0x5b11 - -#define STM32H7_PF12_FUNC_GPIO 0x5c00 -#define STM32H7_PF12_FUNC_FMC_A6 0x5c0d -#define STM32H7_PF12_FUNC_EVENTOUT 0x5c10 -#define STM32H7_PF12_FUNC_ANALOG 0x5c11 - -#define STM32H7_PF13_FUNC_GPIO 0x5d00 -#define STM32H7_PF13_FUNC_DFSDM_DATIN6 0x5d04 -#define STM32H7_PF13_FUNC_I2C4_SMBA 0x5d05 -#define STM32H7_PF13_FUNC_FMC_A7 0x5d0d -#define STM32H7_PF13_FUNC_EVENTOUT 0x5d10 -#define STM32H7_PF13_FUNC_ANALOG 0x5d11 - -#define STM32H7_PF14_FUNC_GPIO 0x5e00 -#define STM32H7_PF14_FUNC_DFSDM_CKIN6 0x5e04 -#define STM32H7_PF14_FUNC_I2C4_SCL 0x5e05 -#define STM32H7_PF14_FUNC_FMC_A8 0x5e0d -#define STM32H7_PF14_FUNC_EVENTOUT 0x5e10 -#define STM32H7_PF14_FUNC_ANALOG 0x5e11 - -#define STM32H7_PF15_FUNC_GPIO 0x5f00 -#define STM32H7_PF15_FUNC_I2C4_SDA 0x5f05 -#define STM32H7_PF15_FUNC_FMC_A9 0x5f0d -#define STM32H7_PF15_FUNC_EVENTOUT 0x5f10 -#define STM32H7_PF15_FUNC_ANALOG 0x5f11 - -#define STM32H7_PG0_FUNC_GPIO 0x6000 -#define STM32H7_PG0_FUNC_FMC_A10 0x600d -#define STM32H7_PG0_FUNC_EVENTOUT 0x6010 -#define STM32H7_PG0_FUNC_ANALOG 0x6011 - -#define STM32H7_PG1_FUNC_GPIO 0x6100 -#define STM32H7_PG1_FUNC_FMC_A11 0x610d -#define STM32H7_PG1_FUNC_EVENTOUT 0x6110 -#define STM32H7_PG1_FUNC_ANALOG 0x6111 - -#define STM32H7_PG2_FUNC_GPIO 0x6200 -#define STM32H7_PG2_FUNC_TIM8_BKIN 0x6204 -#define STM32H7_PG2_FUNC_TIM8_BKIN_COMP12 0x620c -#define STM32H7_PG2_FUNC_FMC_A12 0x620d -#define STM32H7_PG2_FUNC_EVENTOUT 0x6210 -#define STM32H7_PG2_FUNC_ANALOG 0x6211 - -#define STM32H7_PG3_FUNC_GPIO 0x6300 -#define STM32H7_PG3_FUNC_TIM8_BKIN2 0x6304 -#define STM32H7_PG3_FUNC_TIM8_BKIN2_COMP12 0x630c -#define STM32H7_PG3_FUNC_FMC_A13 0x630d -#define STM32H7_PG3_FUNC_EVENTOUT 0x6310 -#define STM32H7_PG3_FUNC_ANALOG 0x6311 - -#define STM32H7_PG4_FUNC_GPIO 0x6400 -#define STM32H7_PG4_FUNC_TIM1_BKIN2 0x6402 -#define STM32H7_PG4_FUNC_TIM1_BKIN2_COMP12 0x640c -#define STM32H7_PG4_FUNC_FMC_A14_FMC_BA0 0x640d -#define STM32H7_PG4_FUNC_EVENTOUT 0x6410 -#define STM32H7_PG4_FUNC_ANALOG 0x6411 - -#define STM32H7_PG5_FUNC_GPIO 0x6500 -#define STM32H7_PG5_FUNC_TIM1_ETR 0x6502 -#define STM32H7_PG5_FUNC_FMC_A15_FMC_BA1 0x650d -#define STM32H7_PG5_FUNC_EVENTOUT 0x6510 -#define STM32H7_PG5_FUNC_ANALOG 0x6511 - -#define STM32H7_PG6_FUNC_GPIO 0x6600 -#define STM32H7_PG6_FUNC_TIM17_BKIN 0x6602 -#define STM32H7_PG6_FUNC_HRTIM_CHE1 0x6603 -#define STM32H7_PG6_FUNC_QUADSPI_BK1_NCS 0x660b -#define STM32H7_PG6_FUNC_FMC_NE3 0x660d -#define STM32H7_PG6_FUNC_DCMI_D12 0x660e -#define STM32H7_PG6_FUNC_LCD_R7 0x660f -#define STM32H7_PG6_FUNC_EVENTOUT 0x6610 -#define STM32H7_PG6_FUNC_ANALOG 0x6611 - -#define STM32H7_PG7_FUNC_GPIO 0x6700 -#define STM32H7_PG7_FUNC_HRTIM_CHE2 0x6703 -#define STM32H7_PG7_FUNC_SAI1_MCLK_A 0x6707 -#define STM32H7_PG7_FUNC_USART6_CK 0x6708 -#define STM32H7_PG7_FUNC_FMC_INT 0x670d -#define STM32H7_PG7_FUNC_DCMI_D13 0x670e -#define STM32H7_PG7_FUNC_LCD_CLK 0x670f -#define STM32H7_PG7_FUNC_EVENTOUT 0x6710 -#define STM32H7_PG7_FUNC_ANALOG 0x6711 - -#define STM32H7_PG8_FUNC_GPIO 0x6800 -#define STM32H7_PG8_FUNC_TIM8_ETR 0x6804 -#define STM32H7_PG8_FUNC_SPI6_NSS 0x6806 -#define STM32H7_PG8_FUNC_USART6_RTS 0x6808 -#define STM32H7_PG8_FUNC_SPDIFRX_IN2 0x6809 -#define STM32H7_PG8_FUNC_ETH_PPS_OUT 0x680c -#define STM32H7_PG8_FUNC_FMC_SDCLK 0x680d -#define STM32H7_PG8_FUNC_LCD_G7 0x680f -#define STM32H7_PG8_FUNC_EVENTOUT 0x6810 -#define STM32H7_PG8_FUNC_ANALOG 0x6811 - -#define STM32H7_PG9_FUNC_GPIO 0x6900 -#define STM32H7_PG9_FUNC_SPI1_MISO_I2S1_SDI 0x6906 -#define STM32H7_PG9_FUNC_USART6_RX 0x6908 -#define STM32H7_PG9_FUNC_SPDIFRX_IN3 0x6909 -#define STM32H7_PG9_FUNC_QUADSPI_BK2_IO2 0x690a -#define STM32H7_PG9_FUNC_SAI2_FS_B 0x690b -#define STM32H7_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d -#define STM32H7_PG9_FUNC_DCMI_VSYNC 0x690e -#define STM32H7_PG9_FUNC_EVENTOUT 0x6910 -#define STM32H7_PG9_FUNC_ANALOG 0x6911 - -#define STM32H7_PG10_FUNC_GPIO 0x6a00 -#define STM32H7_PG10_FUNC_HRTIM_FLT5 0x6a03 -#define STM32H7_PG10_FUNC_SPI1_NSS_I2S1_WS 0x6a06 -#define STM32H7_PG10_FUNC_LCD_G3 0x6a0a -#define STM32H7_PG10_FUNC_SAI2_SD_B 0x6a0b -#define STM32H7_PG10_FUNC_FMC_NE3 0x6a0d -#define STM32H7_PG10_FUNC_DCMI_D2 0x6a0e -#define STM32H7_PG10_FUNC_LCD_B2 0x6a0f -#define STM32H7_PG10_FUNC_EVENTOUT 0x6a10 -#define STM32H7_PG10_FUNC_ANALOG 0x6a11 - -#define STM32H7_PG11_FUNC_GPIO 0x6b00 -#define STM32H7_PG11_FUNC_HRTIM_EEV4 0x6b03 -#define STM32H7_PG11_FUNC_SPI1_SCK_I2S1_CK 0x6b06 -#define STM32H7_PG11_FUNC_SPDIFRX_IN0 0x6b09 -#define STM32H7_PG11_FUNC_SDMMC2_D2 0x6b0b -#define STM32H7_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c -#define STM32H7_PG11_FUNC_DCMI_D3 0x6b0e -#define STM32H7_PG11_FUNC_LCD_B3 0x6b0f -#define STM32H7_PG11_FUNC_EVENTOUT 0x6b10 -#define STM32H7_PG11_FUNC_ANALOG 0x6b11 - -#define STM32H7_PG12_FUNC_GPIO 0x6c00 -#define STM32H7_PG12_FUNC_LPTIM1_IN1 0x6c02 -#define STM32H7_PG12_FUNC_HRTIM_EEV5 0x6c03 -#define STM32H7_PG12_FUNC_SPI6_MISO 0x6c06 -#define STM32H7_PG12_FUNC_USART6_RTS 0x6c08 -#define STM32H7_PG12_FUNC_SPDIFRX_IN1 0x6c09 -#define STM32H7_PG12_FUNC_LCD_B4 0x6c0a -#define STM32H7_PG12_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6c0c -#define STM32H7_PG12_FUNC_FMC_NE4 0x6c0d -#define STM32H7_PG12_FUNC_LCD_B1 0x6c0f -#define STM32H7_PG12_FUNC_EVENTOUT 0x6c10 -#define STM32H7_PG12_FUNC_ANALOG 0x6c11 - -#define STM32H7_PG13_FUNC_GPIO 0x6d00 -#define STM32H7_PG13_FUNC_TRACED0 0x6d01 -#define STM32H7_PG13_FUNC_LPTIM1_OUT 0x6d02 -#define STM32H7_PG13_FUNC_HRTIM_EEV10 0x6d03 -#define STM32H7_PG13_FUNC_SPI6_SCK 0x6d06 -#define STM32H7_PG13_FUNC_USART6_CTS_NSS 0x6d08 -#define STM32H7_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c -#define STM32H7_PG13_FUNC_FMC_A24 0x6d0d -#define STM32H7_PG13_FUNC_LCD_R0 0x6d0f -#define STM32H7_PG13_FUNC_EVENTOUT 0x6d10 -#define STM32H7_PG13_FUNC_ANALOG 0x6d11 - -#define STM32H7_PG14_FUNC_GPIO 0x6e00 -#define STM32H7_PG14_FUNC_TRACED1 0x6e01 -#define STM32H7_PG14_FUNC_LPTIM1_ETR 0x6e02 -#define STM32H7_PG14_FUNC_SPI6_MOSI 0x6e06 -#define STM32H7_PG14_FUNC_USART6_TX 0x6e08 -#define STM32H7_PG14_FUNC_QUADSPI_BK2_IO3 0x6e0a -#define STM32H7_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c -#define STM32H7_PG14_FUNC_FMC_A25 0x6e0d -#define STM32H7_PG14_FUNC_LCD_B0 0x6e0f -#define STM32H7_PG14_FUNC_EVENTOUT 0x6e10 -#define STM32H7_PG14_FUNC_ANALOG 0x6e11 - -#define STM32H7_PG15_FUNC_GPIO 0x6f00 -#define STM32H7_PG15_FUNC_USART6_CTS_NSS 0x6f08 -#define STM32H7_PG15_FUNC_FMC_SDNCAS 0x6f0d -#define STM32H7_PG15_FUNC_DCMI_D13 0x6f0e -#define STM32H7_PG15_FUNC_EVENTOUT 0x6f10 -#define STM32H7_PG15_FUNC_ANALOG 0x6f11 - -#define STM32H7_PH0_FUNC_GPIO 0x7000 -#define STM32H7_PH0_FUNC_EVENTOUT 0x7010 -#define STM32H7_PH0_FUNC_ANALOG 0x7011 - -#define STM32H7_PH1_FUNC_GPIO 0x7100 -#define STM32H7_PH1_FUNC_EVENTOUT 0x7110 -#define STM32H7_PH1_FUNC_ANALOG 0x7111 - -#define STM32H7_PH2_FUNC_GPIO 0x7200 -#define STM32H7_PH2_FUNC_LPTIM1_IN2 0x7202 -#define STM32H7_PH2_FUNC_QUADSPI_BK2_IO0 0x720a -#define STM32H7_PH2_FUNC_SAI2_SCK_B 0x720b -#define STM32H7_PH2_FUNC_ETH_MII_CRS 0x720c -#define STM32H7_PH2_FUNC_FMC_SDCKE0 0x720d -#define STM32H7_PH2_FUNC_LCD_R0 0x720f -#define STM32H7_PH2_FUNC_EVENTOUT 0x7210 -#define STM32H7_PH2_FUNC_ANALOG 0x7211 - -#define STM32H7_PH3_FUNC_GPIO 0x7300 -#define STM32H7_PH3_FUNC_QUADSPI_BK2_IO1 0x730a -#define STM32H7_PH3_FUNC_SAI2_MCK_B 0x730b -#define STM32H7_PH3_FUNC_ETH_MII_COL 0x730c -#define STM32H7_PH3_FUNC_FMC_SDNE0 0x730d -#define STM32H7_PH3_FUNC_LCD_R1 0x730f -#define STM32H7_PH3_FUNC_EVENTOUT 0x7310 -#define STM32H7_PH3_FUNC_ANALOG 0x7311 - -#define STM32H7_PH4_FUNC_GPIO 0x7400 -#define STM32H7_PH4_FUNC_I2C2_SCL 0x7405 -#define STM32H7_PH4_FUNC_LCD_G5 0x740a -#define STM32H7_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b -#define STM32H7_PH4_FUNC_LCD_G4 0x740f -#define STM32H7_PH4_FUNC_EVENTOUT 0x7410 -#define STM32H7_PH4_FUNC_ANALOG 0x7411 - -#define STM32H7_PH5_FUNC_GPIO 0x7500 -#define STM32H7_PH5_FUNC_I2C2_SDA 0x7505 -#define STM32H7_PH5_FUNC_SPI5_NSS 0x7506 -#define STM32H7_PH5_FUNC_FMC_SDNWE 0x750d -#define STM32H7_PH5_FUNC_EVENTOUT 0x7510 -#define STM32H7_PH5_FUNC_ANALOG 0x7511 - -#define STM32H7_PH6_FUNC_GPIO 0x7600 -#define STM32H7_PH6_FUNC_I2C2_SMBA 0x7605 -#define STM32H7_PH6_FUNC_SPI5_SCK 0x7606 -#define STM32H7_PH6_FUNC_ETH_MII_RXD2 0x760c -#define STM32H7_PH6_FUNC_FMC_SDNE1 0x760d -#define STM32H7_PH6_FUNC_DCMI_D8 0x760e -#define STM32H7_PH6_FUNC_EVENTOUT 0x7610 -#define STM32H7_PH6_FUNC_ANALOG 0x7611 - -#define STM32H7_PH7_FUNC_GPIO 0x7700 -#define STM32H7_PH7_FUNC_I2C3_SCL 0x7705 -#define STM32H7_PH7_FUNC_SPI5_MISO 0x7706 -#define STM32H7_PH7_FUNC_ETH_MII_RXD3 0x770c -#define STM32H7_PH7_FUNC_FMC_SDCKE1 0x770d -#define STM32H7_PH7_FUNC_DCMI_D9 0x770e -#define STM32H7_PH7_FUNC_EVENTOUT 0x7710 -#define STM32H7_PH7_FUNC_ANALOG 0x7711 - -#define STM32H7_PH8_FUNC_GPIO 0x7800 -#define STM32H7_PH8_FUNC_TIM5_ETR 0x7803 -#define STM32H7_PH8_FUNC_I2C3_SDA 0x7805 -#define STM32H7_PH8_FUNC_FMC_D16 0x780d -#define STM32H7_PH8_FUNC_DCMI_HSYNC 0x780e -#define STM32H7_PH8_FUNC_LCD_R2 0x780f -#define STM32H7_PH8_FUNC_EVENTOUT 0x7810 -#define STM32H7_PH8_FUNC_ANALOG 0x7811 - -#define STM32H7_PH9_FUNC_GPIO 0x7900 -#define STM32H7_PH9_FUNC_I2C3_SMBA 0x7905 -#define STM32H7_PH9_FUNC_FMC_D17 0x790d -#define STM32H7_PH9_FUNC_DCMI_D0 0x790e -#define STM32H7_PH9_FUNC_LCD_R3 0x790f -#define STM32H7_PH9_FUNC_EVENTOUT 0x7910 -#define STM32H7_PH9_FUNC_ANALOG 0x7911 - -#define STM32H7_PH10_FUNC_GPIO 0x7a00 -#define STM32H7_PH10_FUNC_TIM5_CH1 0x7a03 -#define STM32H7_PH10_FUNC_I2C4_SMBA 0x7a05 -#define STM32H7_PH10_FUNC_FMC_D18 0x7a0d -#define STM32H7_PH10_FUNC_DCMI_D1 0x7a0e -#define STM32H7_PH10_FUNC_LCD_R4 0x7a0f -#define STM32H7_PH10_FUNC_EVENTOUT 0x7a10 -#define STM32H7_PH10_FUNC_ANALOG 0x7a11 - -#define STM32H7_PH11_FUNC_GPIO 0x7b00 -#define STM32H7_PH11_FUNC_TIM5_CH2 0x7b03 -#define STM32H7_PH11_FUNC_I2C4_SCL 0x7b05 -#define STM32H7_PH11_FUNC_FMC_D19 0x7b0d -#define STM32H7_PH11_FUNC_DCMI_D2 0x7b0e -#define STM32H7_PH11_FUNC_LCD_R5 0x7b0f -#define STM32H7_PH11_FUNC_EVENTOUT 0x7b10 -#define STM32H7_PH11_FUNC_ANALOG 0x7b11 - -#define STM32H7_PH12_FUNC_GPIO 0x7c00 -#define STM32H7_PH12_FUNC_TIM5_CH3 0x7c03 -#define STM32H7_PH12_FUNC_I2C4_SDA 0x7c05 -#define STM32H7_PH12_FUNC_FMC_D20 0x7c0d -#define STM32H7_PH12_FUNC_DCMI_D3 0x7c0e -#define STM32H7_PH12_FUNC_LCD_R6 0x7c0f -#define STM32H7_PH12_FUNC_EVENTOUT 0x7c10 -#define STM32H7_PH12_FUNC_ANALOG 0x7c11 - -#define STM32H7_PH13_FUNC_GPIO 0x7d00 -#define STM32H7_PH13_FUNC_TIM8_CH1N 0x7d04 -#define STM32H7_PH13_FUNC_UART4_TX 0x7d09 -#define STM32H7_PH13_FUNC_CAN1_TX 0x7d0a -#define STM32H7_PH13_FUNC_FMC_D21 0x7d0d -#define STM32H7_PH13_FUNC_LCD_G2 0x7d0f -#define STM32H7_PH13_FUNC_EVENTOUT 0x7d10 -#define STM32H7_PH13_FUNC_ANALOG 0x7d11 - -#define STM32H7_PH14_FUNC_GPIO 0x7e00 -#define STM32H7_PH14_FUNC_TIM8_CH2N 0x7e04 -#define STM32H7_PH14_FUNC_UART4_RX 0x7e09 -#define STM32H7_PH14_FUNC_CAN1_RX 0x7e0a -#define STM32H7_PH14_FUNC_FMC_D22 0x7e0d -#define STM32H7_PH14_FUNC_DCMI_D4 0x7e0e -#define STM32H7_PH14_FUNC_LCD_G3 0x7e0f -#define STM32H7_PH14_FUNC_EVENTOUT 0x7e10 -#define STM32H7_PH14_FUNC_ANALOG 0x7e11 - -#define STM32H7_PH15_FUNC_GPIO 0x7f00 -#define STM32H7_PH15_FUNC_TIM8_CH3N 0x7f04 -#define STM32H7_PH15_FUNC_CAN1_TXFD 0x7f0a -#define STM32H7_PH15_FUNC_FMC_D23 0x7f0d -#define STM32H7_PH15_FUNC_DCMI_D11 0x7f0e -#define STM32H7_PH15_FUNC_LCD_G4 0x7f0f -#define STM32H7_PH15_FUNC_EVENTOUT 0x7f10 -#define STM32H7_PH15_FUNC_ANALOG 0x7f11 - -#define STM32H7_PI0_FUNC_GPIO 0x8000 -#define STM32H7_PI0_FUNC_TIM5_CH4 0x8003 -#define STM32H7_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 -#define STM32H7_PI0_FUNC_CAN1_RXFD 0x800a -#define STM32H7_PI0_FUNC_FMC_D24 0x800d -#define STM32H7_PI0_FUNC_DCMI_D13 0x800e -#define STM32H7_PI0_FUNC_LCD_G5 0x800f -#define STM32H7_PI0_FUNC_EVENTOUT 0x8010 -#define STM32H7_PI0_FUNC_ANALOG 0x8011 - -#define STM32H7_PI1_FUNC_GPIO 0x8100 -#define STM32H7_PI1_FUNC_TIM8_BKIN2 0x8104 -#define STM32H7_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 -#define STM32H7_PI1_FUNC_TIM8_BKIN2_COMP12 0x810c -#define STM32H7_PI1_FUNC_FMC_D25 0x810d -#define STM32H7_PI1_FUNC_DCMI_D8 0x810e -#define STM32H7_PI1_FUNC_LCD_G6 0x810f -#define STM32H7_PI1_FUNC_EVENTOUT 0x8110 -#define STM32H7_PI1_FUNC_ANALOG 0x8111 - -#define STM32H7_PI2_FUNC_GPIO 0x8200 -#define STM32H7_PI2_FUNC_TIM8_CH4 0x8204 -#define STM32H7_PI2_FUNC_SPI2_MISO_I2S2_SDI 0x8206 -#define STM32H7_PI2_FUNC_FMC_D26 0x820d -#define STM32H7_PI2_FUNC_DCMI_D9 0x820e -#define STM32H7_PI2_FUNC_LCD_G7 0x820f -#define STM32H7_PI2_FUNC_EVENTOUT 0x8210 -#define STM32H7_PI2_FUNC_ANALOG 0x8211 - -#define STM32H7_PI3_FUNC_GPIO 0x8300 -#define STM32H7_PI3_FUNC_TIM8_ETR 0x8304 -#define STM32H7_PI3_FUNC_SPI2_MOSI_I2S2_SDO 0x8306 -#define STM32H7_PI3_FUNC_FMC_D27 0x830d -#define STM32H7_PI3_FUNC_DCMI_D10 0x830e -#define STM32H7_PI3_FUNC_EVENTOUT 0x8310 -#define STM32H7_PI3_FUNC_ANALOG 0x8311 - -#define STM32H7_PI4_FUNC_GPIO 0x8400 -#define STM32H7_PI4_FUNC_TIM8_BKIN 0x8404 -#define STM32H7_PI4_FUNC_SAI2_MCK_A 0x840b -#define STM32H7_PI4_FUNC_TIM8_BKIN_COMP12 0x840c -#define STM32H7_PI4_FUNC_FMC_NBL2 0x840d -#define STM32H7_PI4_FUNC_DCMI_D5 0x840e -#define STM32H7_PI4_FUNC_LCD_B4 0x840f -#define STM32H7_PI4_FUNC_EVENTOUT 0x8410 -#define STM32H7_PI4_FUNC_ANALOG 0x8411 - -#define STM32H7_PI5_FUNC_GPIO 0x8500 -#define STM32H7_PI5_FUNC_TIM8_CH1 0x8504 -#define STM32H7_PI5_FUNC_SAI2_SCK_A 0x850b -#define STM32H7_PI5_FUNC_FMC_NBL3 0x850d -#define STM32H7_PI5_FUNC_DCMI_VSYNC 0x850e -#define STM32H7_PI5_FUNC_LCD_B5 0x850f -#define STM32H7_PI5_FUNC_EVENTOUT 0x8510 -#define STM32H7_PI5_FUNC_ANALOG 0x8511 - -#define STM32H7_PI6_FUNC_GPIO 0x8600 -#define STM32H7_PI6_FUNC_TIM8_CH2 0x8604 -#define STM32H7_PI6_FUNC_SAI2_SD_A 0x860b -#define STM32H7_PI6_FUNC_FMC_D28 0x860d -#define STM32H7_PI6_FUNC_DCMI_D6 0x860e -#define STM32H7_PI6_FUNC_LCD_B6 0x860f -#define STM32H7_PI6_FUNC_EVENTOUT 0x8610 -#define STM32H7_PI6_FUNC_ANALOG 0x8611 - -#define STM32H7_PI7_FUNC_GPIO 0x8700 -#define STM32H7_PI7_FUNC_TIM8_CH3 0x8704 -#define STM32H7_PI7_FUNC_SAI2_FS_A 0x870b -#define STM32H7_PI7_FUNC_FMC_D29 0x870d -#define STM32H7_PI7_FUNC_DCMI_D7 0x870e -#define STM32H7_PI7_FUNC_LCD_B7 0x870f -#define STM32H7_PI7_FUNC_EVENTOUT 0x8710 -#define STM32H7_PI7_FUNC_ANALOG 0x8711 - -#define STM32H7_PI8_FUNC_GPIO 0x8800 -#define STM32H7_PI8_FUNC_EVENTOUT 0x8810 -#define STM32H7_PI8_FUNC_ANALOG 0x8811 - -#define STM32H7_PI9_FUNC_GPIO 0x8900 -#define STM32H7_PI9_FUNC_UART4_RX 0x8909 -#define STM32H7_PI9_FUNC_CAN1_RX 0x890a -#define STM32H7_PI9_FUNC_FMC_D30 0x890d -#define STM32H7_PI9_FUNC_LCD_VSYNC 0x890f -#define STM32H7_PI9_FUNC_EVENTOUT 0x8910 -#define STM32H7_PI9_FUNC_ANALOG 0x8911 - -#define STM32H7_PI10_FUNC_GPIO 0x8a00 -#define STM32H7_PI10_FUNC_CAN1_RXFD 0x8a0a -#define STM32H7_PI10_FUNC_ETH_MII_RX_ER 0x8a0c -#define STM32H7_PI10_FUNC_FMC_D31 0x8a0d -#define STM32H7_PI10_FUNC_LCD_HSYNC 0x8a0f -#define STM32H7_PI10_FUNC_EVENTOUT 0x8a10 -#define STM32H7_PI10_FUNC_ANALOG 0x8a11 - -#define STM32H7_PI11_FUNC_GPIO 0x8b00 -#define STM32H7_PI11_FUNC_LCD_G6 0x8b0a -#define STM32H7_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b -#define STM32H7_PI11_FUNC_EVENTOUT 0x8b10 -#define STM32H7_PI11_FUNC_ANALOG 0x8b11 - -#define STM32H7_PI12_FUNC_GPIO 0x8c00 -#define STM32H7_PI12_FUNC_ETH_TX_ER 0x8c0c -#define STM32H7_PI12_FUNC_LCD_HSYNC 0x8c0f -#define STM32H7_PI12_FUNC_EVENTOUT 0x8c10 -#define STM32H7_PI12_FUNC_ANALOG 0x8c11 - -#define STM32H7_PI13_FUNC_GPIO 0x8d00 -#define STM32H7_PI13_FUNC_LCD_VSYNC 0x8d0f -#define STM32H7_PI13_FUNC_EVENTOUT 0x8d10 -#define STM32H7_PI13_FUNC_ANALOG 0x8d11 - -#define STM32H7_PI14_FUNC_GPIO 0x8e00 -#define STM32H7_PI14_FUNC_LCD_CLK 0x8e0f -#define STM32H7_PI14_FUNC_EVENTOUT 0x8e10 -#define STM32H7_PI14_FUNC_ANALOG 0x8e11 - -#define STM32H7_PI15_FUNC_GPIO 0x8f00 -#define STM32H7_PI15_FUNC_LCD_G2 0x8f0a -#define STM32H7_PI15_FUNC_LCD_R0 0x8f0f -#define STM32H7_PI15_FUNC_EVENTOUT 0x8f10 -#define STM32H7_PI15_FUNC_ANALOG 0x8f11 - -#define STM32H7_PJ0_FUNC_GPIO 0x9000 -#define STM32H7_PJ0_FUNC_LCD_R7 0x900a -#define STM32H7_PJ0_FUNC_LCD_R1 0x900f -#define STM32H7_PJ0_FUNC_EVENTOUT 0x9010 -#define STM32H7_PJ0_FUNC_ANALOG 0x9011 - -#define STM32H7_PJ1_FUNC_GPIO 0x9100 -#define STM32H7_PJ1_FUNC_LCD_R2 0x910f -#define STM32H7_PJ1_FUNC_EVENTOUT 0x9110 -#define STM32H7_PJ1_FUNC_ANALOG 0x9111 - -#define STM32H7_PJ2_FUNC_GPIO 0x9200 -#define STM32H7_PJ2_FUNC_DSI_TE 0x920e -#define STM32H7_PJ2_FUNC_LCD_R3 0x920f -#define STM32H7_PJ2_FUNC_EVENTOUT 0x9210 -#define STM32H7_PJ2_FUNC_ANALOG 0x9211 - -#define STM32H7_PJ3_FUNC_GPIO 0x9300 -#define STM32H7_PJ3_FUNC_LCD_R4 0x930f -#define STM32H7_PJ3_FUNC_EVENTOUT 0x9310 -#define STM32H7_PJ3_FUNC_ANALOG 0x9311 - -#define STM32H7_PJ4_FUNC_GPIO 0x9400 -#define STM32H7_PJ4_FUNC_LCD_R5 0x940f -#define STM32H7_PJ4_FUNC_EVENTOUT 0x9410 -#define STM32H7_PJ4_FUNC_ANALOG 0x9411 - -#define STM32H7_PJ5_FUNC_GPIO 0x9500 -#define STM32H7_PJ5_FUNC_LCD_R6 0x950f -#define STM32H7_PJ5_FUNC_EVENTOUT 0x9510 -#define STM32H7_PJ5_FUNC_ANALOG 0x9511 - -#define STM32H7_PJ6_FUNC_GPIO 0x9600 -#define STM32H7_PJ6_FUNC_TIM8_CH2 0x9604 -#define STM32H7_PJ6_FUNC_LCD_R7 0x960f -#define STM32H7_PJ6_FUNC_EVENTOUT 0x9610 -#define STM32H7_PJ6_FUNC_ANALOG 0x9611 - -#define STM32H7_PJ7_FUNC_GPIO 0x9700 -#define STM32H7_PJ7_FUNC_TRGIN 0x9701 -#define STM32H7_PJ7_FUNC_TIM8_CH2N 0x9704 -#define STM32H7_PJ7_FUNC_LCD_G0 0x970f -#define STM32H7_PJ7_FUNC_EVENTOUT 0x9710 -#define STM32H7_PJ7_FUNC_ANALOG 0x9711 - -#define STM32H7_PJ8_FUNC_GPIO 0x9800 -#define STM32H7_PJ8_FUNC_TIM1_CH3N 0x9802 -#define STM32H7_PJ8_FUNC_TIM8_CH1 0x9804 -#define STM32H7_PJ8_FUNC_UART8_TX 0x9809 -#define STM32H7_PJ8_FUNC_LCD_G1 0x980f -#define STM32H7_PJ8_FUNC_EVENTOUT 0x9810 -#define STM32H7_PJ8_FUNC_ANALOG 0x9811 - -#define STM32H7_PJ9_FUNC_GPIO 0x9900 -#define STM32H7_PJ9_FUNC_TIM1_CH3 0x9902 -#define STM32H7_PJ9_FUNC_TIM8_CH1N 0x9904 -#define STM32H7_PJ9_FUNC_UART8_RX 0x9909 -#define STM32H7_PJ9_FUNC_LCD_G2 0x990f -#define STM32H7_PJ9_FUNC_EVENTOUT 0x9910 -#define STM32H7_PJ9_FUNC_ANALOG 0x9911 - -#define STM32H7_PJ10_FUNC_GPIO 0x9a00 -#define STM32H7_PJ10_FUNC_TIM1_CH2N 0x9a02 -#define STM32H7_PJ10_FUNC_TIM8_CH2 0x9a04 -#define STM32H7_PJ10_FUNC_SPI5_MOSI 0x9a06 -#define STM32H7_PJ10_FUNC_LCD_G3 0x9a0f -#define STM32H7_PJ10_FUNC_EVENTOUT 0x9a10 -#define STM32H7_PJ10_FUNC_ANALOG 0x9a11 - -#define STM32H7_PJ11_FUNC_GPIO 0x9b00 -#define STM32H7_PJ11_FUNC_TIM1_CH2 0x9b02 -#define STM32H7_PJ11_FUNC_TIM8_CH2N 0x9b04 -#define STM32H7_PJ11_FUNC_SPI5_MISO 0x9b06 -#define STM32H7_PJ11_FUNC_LCD_G4 0x9b0f -#define STM32H7_PJ11_FUNC_EVENTOUT 0x9b10 -#define STM32H7_PJ11_FUNC_ANALOG 0x9b11 - -#define STM32H7_PJ12_FUNC_GPIO 0x9c00 -#define STM32H7_PJ12_FUNC_TRGOUT 0x9c01 -#define STM32H7_PJ12_FUNC_LCD_G3 0x9c0a -#define STM32H7_PJ12_FUNC_LCD_B0 0x9c0f -#define STM32H7_PJ12_FUNC_EVENTOUT 0x9c10 -#define STM32H7_PJ12_FUNC_ANALOG 0x9c11 - -#define STM32H7_PJ13_FUNC_GPIO 0x9d00 -#define STM32H7_PJ13_FUNC_LCD_B4 0x9d0a -#define STM32H7_PJ13_FUNC_LCD_B1 0x9d0f -#define STM32H7_PJ13_FUNC_EVENTOUT 0x9d10 -#define STM32H7_PJ13_FUNC_ANALOG 0x9d11 - -#define STM32H7_PJ14_FUNC_GPIO 0x9e00 -#define STM32H7_PJ14_FUNC_LCD_B2 0x9e0f -#define STM32H7_PJ14_FUNC_EVENTOUT 0x9e10 -#define STM32H7_PJ14_FUNC_ANALOG 0x9e11 - -#define STM32H7_PJ15_FUNC_GPIO 0x9f00 -#define STM32H7_PJ15_FUNC_LCD_B3 0x9f0f -#define STM32H7_PJ15_FUNC_EVENTOUT 0x9f10 -#define STM32H7_PJ15_FUNC_ANALOG 0x9f11 - -#define STM32H7_PK0_FUNC_GPIO 0xa000 -#define STM32H7_PK0_FUNC_TIM1_CH1N 0xa002 -#define STM32H7_PK0_FUNC_TIM8_CH3 0xa004 -#define STM32H7_PK0_FUNC_SPI5_SCK 0xa006 -#define STM32H7_PK0_FUNC_LCD_G5 0xa00f -#define STM32H7_PK0_FUNC_EVENTOUT 0xa010 -#define STM32H7_PK0_FUNC_ANALOG 0xa011 - -#define STM32H7_PK1_FUNC_GPIO 0xa100 -#define STM32H7_PK1_FUNC_TIM1_CH1 0xa102 -#define STM32H7_PK1_FUNC_TIM8_CH3N 0xa104 -#define STM32H7_PK1_FUNC_SPI5_NSS 0xa106 -#define STM32H7_PK1_FUNC_LCD_G6 0xa10f -#define STM32H7_PK1_FUNC_EVENTOUT 0xa110 -#define STM32H7_PK1_FUNC_ANALOG 0xa111 - -#define STM32H7_PK2_FUNC_GPIO 0xa200 -#define STM32H7_PK2_FUNC_TIM1_BKIN 0xa202 -#define STM32H7_PK2_FUNC_TIM8_BKIN 0xa204 -#define STM32H7_PK2_FUNC_TIM8_BKIN_COMP12 0xa20b -#define STM32H7_PK2_FUNC_TIM1_BKIN_COMP12 0xa20c -#define STM32H7_PK2_FUNC_LCD_G7 0xa20f -#define STM32H7_PK2_FUNC_EVENTOUT 0xa210 -#define STM32H7_PK2_FUNC_ANALOG 0xa211 - -#define STM32H7_PK3_FUNC_GPIO 0xa300 -#define STM32H7_PK3_FUNC_LCD_B4 0xa30f -#define STM32H7_PK3_FUNC_EVENTOUT 0xa310 -#define STM32H7_PK3_FUNC_ANALOG 0xa311 - -#define STM32H7_PK4_FUNC_GPIO 0xa400 -#define STM32H7_PK4_FUNC_LCD_B5 0xa40f -#define STM32H7_PK4_FUNC_EVENTOUT 0xa410 -#define STM32H7_PK4_FUNC_ANALOG 0xa411 - -#define STM32H7_PK5_FUNC_GPIO 0xa500 -#define STM32H7_PK5_FUNC_LCD_B6 0xa50f -#define STM32H7_PK5_FUNC_EVENTOUT 0xa510 -#define STM32H7_PK5_FUNC_ANALOG 0xa511 - -#define STM32H7_PK6_FUNC_GPIO 0xa600 -#define STM32H7_PK6_FUNC_LCD_B7 0xa60f -#define STM32H7_PK6_FUNC_EVENTOUT 0xa610 -#define STM32H7_PK6_FUNC_ANALOG 0xa611 - -#define STM32H7_PK7_FUNC_GPIO 0xa700 -#define STM32H7_PK7_FUNC_LCD_DE 0xa70f -#define STM32H7_PK7_FUNC_EVENTOUT 0xa710 -#define STM32H7_PK7_FUNC_ANALOG 0xa711 - -#endif /* _DT_BINDINGS_STM32H7_PINFUNC_H */ diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h new file mode 100644 index 000000000000..bf54779d1625 --- /dev/null +++ b/include/dt-bindings/power/r8a77970-sysc.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77970_PD_CA53_CPU0 5 +#define R8A77970_PD_CA53_CPU1 6 +#define R8A77970_PD_CR7 13 +#define R8A77970_PD_CA53_SCU 21 +#define R8A77970_PD_A2IR0 23 +#define R8A77970_PD_A3IR 24 +#define R8A77970_PD_A2IR1 27 +#define R8A77970_PD_A2IR2 28 +#define R8A77970_PD_A2IR3 29 +#define R8A77970_PD_A2SC0 30 +#define R8A77970_PD_A2SC1 31 + +/* Always-on power area */ +#define R8A77970_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */ diff --git a/include/dt-bindings/thermal/tegra186-bpmp-thermal.h b/include/dt-bindings/thermal/tegra186-bpmp-thermal.h new file mode 100644 index 000000000000..a96b8fa31aab --- /dev/null +++ b/include/dt-bindings/thermal/tegra186-bpmp-thermal.h @@ -0,0 +1,14 @@ +/* + * This header provides constants for binding nvidia,tegra186-bpmp-thermal. + */ + +#ifndef _DT_BINDINGS_THERMAL_TEGRA186_BPMP_THERMAL_H +#define _DT_BINDINGS_THERMAL_TEGRA186_BPMP_THERMAL_H + +#define TEGRA186_BPMP_THERMAL_ZONE_CPU 2 +#define TEGRA186_BPMP_THERMAL_ZONE_GPU 3 +#define TEGRA186_BPMP_THERMAL_ZONE_AUX 4 +#define TEGRA186_BPMP_THERMAL_ZONE_PLLX 5 +#define TEGRA186_BPMP_THERMAL_ZONE_AO 6 + +#endif |