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authorLars-Peter Clausen <lars@metafoo.de>2017-09-05 10:16:37 +0200
committerVinod Koul <vinod.koul@intel.com>2017-09-17 18:58:18 +0530
commit63ab76dbbdb8657e24645b7311ec3911a41039b5 (patch)
treed84c51cfddbda2a638dc2d1dbef19f0671ff76b4
parent2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e (diff)
dmaengine: axi-dmac: Only use hardware cyclic mode for single segment transfers
In hardware cyclic mode the submitted segment is repeated. This means hardware cyclic mode can only be used if the transfer has a single segment. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r--drivers/dma/dma-axi-dmac.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c
index 7f0b9aa15867..eb289aa187dd 100644
--- a/drivers/dma/dma-axi-dmac.c
+++ b/drivers/dma/dma-axi-dmac.c
@@ -220,9 +220,11 @@ static void axi_dmac_start_transfer(struct axi_dmac_chan *chan)
/*
* If the hardware supports cyclic transfers and there is no callback to
- * call, enable hw cyclic mode to avoid unnecessary interrupts.
+ * call and only a single segment, enable hw cyclic mode to avoid
+ * unnecessary interrupts.
*/
- if (chan->hw_cyclic && desc->cyclic && !desc->vdesc.tx.callback)
+ if (chan->hw_cyclic && desc->cyclic && !desc->vdesc.tx.callback &&
+ desc->num_sgs == 1)
flags |= AXI_DMAC_FLAG_CYCLIC;
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, sg->x_len - 1);