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authorHans Verkuil <hverkuil-cisco@xs4all.nl>2019-12-02 12:46:17 +0100
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>2019-12-13 09:23:09 +0100
commit7b575b6d8de03ca6b6ab85fa1dd53d2ce921a4a0 (patch)
tree82e9db1a2c412872c86deb931155fad0ccd34f8c
parent3d15c7643ba78b71c5c8fae25d7d9af52442882a (diff)
media: vidioc-g-dv-timings.rst: fix wrong porch
It is the vfrontporch of field 1 that is one half-line longer, not the backporch. The order of the vertical signals in an interlaced system is: Field 1: vsync vbackporch active video of field 1 vfrontporch + 0.5 Field 2: il_vsync il_vbackporch - 0.5 active video of field 2 il_vfrontporch Interlaced systems that use HALF_LINE set the il_ fields as follows: il_vfrontporch = vfrontporch il_vsync = vsync il_vbackporch = vbackporch + 1 So the total vertical blanking for field 1 is: vsync + vbackporch + vfrontporch + 0.5 and for field 2: vsync + vbackporch + 1 + vfrontporch - 0.5 == vsync + vbackporch + vfrontporch + 0.5 So each field has the same number of half-lines. Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
-rw-r--r--Documentation/media/uapi/v4l/vidioc-g-dv-timings.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/media/uapi/v4l/vidioc-g-dv-timings.rst b/Documentation/media/uapi/v4l/vidioc-g-dv-timings.rst
index 5712bd48e687..5c675cbac4cf 100644
--- a/Documentation/media/uapi/v4l/vidioc-g-dv-timings.rst
+++ b/Documentation/media/uapi/v4l/vidioc-g-dv-timings.rst
@@ -279,7 +279,7 @@ EBUSY
then it will set this flag to signal this to the application.
* - ``V4L2_DV_FL_HALF_LINE``
- Specific to interlaced formats: if set, then the vertical
- backporch of field 1 (aka the odd field) is really one half-line
+ frontporch of field 1 (aka the odd field) is really one half-line
longer and the vertical backporch of field 2 (aka the even field)
is really one half-line shorter, so each field has exactly the
same number of half-lines. Whether half-lines can be detected or