From 6387b75284aa7b78c2e947934fb874444ab427e9 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Wed, 25 Mar 2015 19:57:32 -0300 Subject: [media] omap3isp: Calculate vpclk_div for CSI-2 The video port clock is l3_ick divided by vpclk_div. This clock must be high enough for the external pixel rate. The video port requires two clock cycles to process a pixel. Signed-off-by: Sakari Ailus Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- include/media/omap3isp.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include/media') diff --git a/include/media/omap3isp.h b/include/media/omap3isp.h index 39e0748b0d31..0f0c08b48829 100644 --- a/include/media/omap3isp.h +++ b/include/media/omap3isp.h @@ -129,11 +129,9 @@ struct isp_ccp2_cfg { /** * struct isp_csi2_cfg - CSI2 interface configuration * @crc: Enable the cyclic redundancy check - * @vpclk_div: Video port output clock control */ struct isp_csi2_cfg { unsigned crc:1; - unsigned vpclk_div:2; struct isp_csiphy_lanes_cfg lanecfg; }; -- cgit v1.2.3