From adf4b00ebf4e183f36d88d5a5a591c532fb0abe9 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 19 Mar 2014 12:18:02 +0000 Subject: ARM: l2c: spear13xx: remove cache size override The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King --- arch/arm/mach-spear/spear13xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-spear') diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c index dcb300443b66..c9897ea38980 100644 --- a/arch/arm/mach-spear/spear13xx.c +++ b/arch/arm/mach-spear/spear13xx.c @@ -46,7 +46,7 @@ void __init spear13xx_l2x0_init(void) */ writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); - l2x0_init(VA_L2CC_BASE, 0x30a60001, 0xfe00ffff); + l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff); } /* -- cgit v1.2.3