| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2015-04-02 | perf/x86/intel: Limit to half counters when the HT workaround is enabled, to ... | Stephane Eranian | 1 | -2/+20 |
| 2015-04-02 | perf/x86/intel: Fix intel_get_event_constraints() for dynamic constraints | Stephane Eranian | 1 | -5/+10 |
| 2015-04-02 | perf/x86/intel: Enforce HT bug workaround for SNB/IVB/HSW | Maria Dimakopoulou | 1 | -9/+44 |
| 2015-04-02 | perf/x86/intel: Implement cross-HT corruption bug workaround | Maria Dimakopoulou | 1 | -1/+306 |
| 2015-04-02 | perf/x86/intel: Add cross-HT counter exclusion infrastructure | Maria Dimakopoulou | 1 | -5/+66 |
| 2015-04-02 | perf/x86: Add 'index' param to get_event_constraint() callback | Stephane Eranian | 1 | -5/+10 |
| 2015-04-02 | perf/x86: Vectorize cpuc->kfree_on_online | Stephane Eranian | 1 | -1/+3 |
| 2015-04-02 | perf/x86: Rename x86_pmu::er_flags to 'flags' | Stephane Eranian | 1 | -12/+12 |
| 2015-04-02 | Merge branch 'perf/urgent' into perf/core, before applying dependent patches | Ingo Molnar | 1 | -5/+5 |
| 2015-04-02 | perf/x86/intel/bts: Add BTS PMU driver | Alexander Shishkin | 1 | -1/+5 |
| 2015-04-02 | perf/x86/intel/pt: Add Intel PT PMU driver | Alexander Shishkin | 1 | -0/+8 |
| 2015-04-02 | perf/x86: Mark Intel PT and LBR/BTS as mutually exclusive | Alexander Shishkin | 1 | -0/+11 |
| 2015-04-02 | perf/x86/intel: Fix Haswell CYCLE_ACTIVITY.* counter constraints | Andi Kleen | 1 | -3/+3 |
| 2015-04-02 | perf/x86/intel: Filter branches for PEBS event | Kan Liang | 1 | -2/+2 |
| 2015-03-27 | perf/x86/intel: Add INST_RETIRED.ALL workarounds | Andi Kleen | 1 | -0/+27 |
| 2015-03-27 | perf/x86/intel: Add Broadwell core support | Andi Kleen | 1 | -0/+47 |
| 2015-03-27 | perf/x86/intel: Add new cache events table for Haswell | Andi Kleen | 1 | -2/+192 |
| 2015-02-18 | perf: Simplify the branch stack check | Yan, Zheng | 1 | -17/+3 |
| 2015-02-18 | perf/x86/intel: Add basic Haswell LBR call stack support | Yan, Zheng | 1 | -1/+1 |
| 2015-02-18 | perf/x86/intel: Use context switch callback to flush LBR stack | Yan, Zheng | 1 | -13/+1 |
| 2015-01-28 | perf/x86/intel: Add model number for Airmont | Kan Liang | 1 | -0/+1 |
| 2014-10-29 | perf/x86/intel: Revert incomplete and undocumented Broadwell client support | Ingo Molnar | 1 | -171/+2 |
| 2014-10-15 | Merge branch 'for-3.18-consistent-ops' of git://git.kernel.org/pub/scm/linux/... | Linus Torvalds | 1 | -9/+9 |
| 2014-09-24 | perf/x86/intel: Use Broadwell cache event list for Haswell | Andi Kleen | 1 | -2/+2 |
| 2014-09-24 | perf/x86: Add INST_RETIRED.ALL workarounds | Andi Kleen | 1 | -0/+19 |
| 2014-09-24 | perf/x86/intel: Add Broadwell core support | Andi Kleen | 1 | -0/+150 |
| 2014-09-24 | perf/x86/intel: Document all Haswell models | Andi Kleen | 1 | -4/+4 |
| 2014-09-24 | perf/x86/intel: Remove incorrect model number from Haswell perf | Andi Kleen | 1 | -1/+0 |
| 2014-08-26 | x86: Replace __get_cpu_var uses | Christoph Lameter | 1 | -9/+9 |
| 2014-08-13 | perf/x86: Use extended offcore mask on Haswell | Andi Kleen | 1 | -1/+1 |
| 2014-08-13 | perf/x86/intel: Update Intel models | Peter Zijlstra | 1 | -25/+26 |
| 2014-07-16 | perf/x86/intel: Protect LBR and extra_regs against KVM lying | Kan Liang | 1 | -1/+65 |
| 2014-07-16 | perf/x86/intel: Use proper dTLB-load-misses event on IvyBridge | Vince Weaver | 1 | -0/+3 |
| 2014-07-02 | perf/x86/intel: ignore CondChgd bit to avoid false NMI handling | HATAYAMA Daisuke | 1 | -0/+9 |
| 2014-05-07 | perf/x86/intel: Fix Silvermont's event constraints | Yan, Zheng | 1 | -1/+0 |
| 2014-02-21 | perf/x86: Correctly use FEATURE_PDCM | Peter Zijlstra | 1 | -4/+1 |
| 2014-02-21 | perf, nmi: Fix unknown NMI warning | Markus Metzger | 1 | -4/+2 |
| 2013-10-04 | perf/x86: Suppress duplicated abort LBR records | Andi Kleen | 1 | -0/+1 |
| 2013-10-04 | Merge branch 'perf/urgent' into perf/core | Ingo Molnar | 1 | -0/+1 |
| 2013-09-23 | perf/x86/intel: Add model number for Avoton Silvermont | Yan, Zheng | 1 | -0/+1 |
| 2013-09-12 | perf/x86/intel: Clean up EVENT_ATTR_STR() muck | Ingo Molnar | 1 | -18/+17 |
| 2013-09-12 | perf/x86/intel: Clean up checkpoint-interrupt bits | Peter Zijlstra | 1 | -9/+13 |
| 2013-09-12 | perf/x86/intel: Add Haswell TSX event aliases | Andi Kleen | 1 | -0/+27 |
| 2013-09-12 | perf/x86/intel: Avoid checkpointed counters causing excessive TSX aborts | Andi Kleen | 1 | -0/+37 |
| 2013-09-12 | perf/x86/intel: Fix Silvermont offcore masks | Peter Zijlstra | 1 | -2/+2 |
| 2013-09-12 | perf/x86: Add constraint for IVB CYCLE_ACTIVITY:CYCLES_LDM_PENDING | Stephane Eranian | 1 | -0/+1 |
| 2013-09-02 | perf/x86: Add Silvermont (22nm Atom) support | Yan, Zheng | 1 | -0/+158 |
| 2013-09-02 | perf/x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X | Yan, Zheng | 1 | -9/+13 |
| 2013-08-12 | perf/x86: Add Haswell ULT model number used in Macbook Air and other systems | Andi Kleen | 1 | -0/+1 |
| 2013-06-26 | perf/x86: Fix shared register mutual exclusion enforcement | Stephane Eranian | 1 | -2/+0 |
