From fbb8bb8370f6fdaaaccf85201f4ee2a665aae42d Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:11 -0800 Subject: ARM: dts: Configure omap4 rng to probe with ti-sysc Add RNG interconnect data for omap4 similar to what dra7 has. The clock is OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET at offset address 0x01c0, which matches what dra7 also has with DRA7_L4SEC_CLKCTRL_INDEX(0x1c0). Note that we need to also add the related l4_secure clock entries. I've only added RNG, the others can be added as they get tested. They are probably very similar to what we already have for dra7 in dra7_l4sec_clkctrl_regs[]. With the clock tagged CLKF_SOC_NONSEC, clock is set disabled for secure devices and clk_get() will fail. Additionally we disable the RNG target module on droid4 to avoid introducing new boot time warnings. Cc: devicetree@vger.kernel.org Cc: Rob Herring Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts/omap4-l4.dtsi') diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index 83f803be8ee2..e8fa3f389f25 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -2002,12 +2002,26 @@ }; }; - target-module@90000 { /* 0x48090000, ap 57 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; + rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x91fe0 0x4>, + <0x91fe4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + ; + /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ + clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x90000 0x2000>; + + rng: rng@0 { + compatible = "ti,omap4-rng"; + reg = <0x0 0x2000>; + interrupts = ; + }; }; target-module@96000 { /* 0x48096000, ap 37 26.0 */ -- cgit v1.2.3