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2018-11-29drm/i915/dp: Add DSC params and DSC config to intel_crtc_stateManasi Navare2-0/+10
Basic DSC parameters and DSC configuration data needs to be computed for each of the requested mode during atomic check. This is required since for certain modes, valid DSC parameters and config data might not be computed in which case compression cannot be enabled for that mode. For that reason we need to add these params and config structure to the intel_crtc_state so that if valid this state information can directly be used while enabling DSC in atomic commit. v2: * Rebase on drm-tip (Manasi) Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-1-manasi.d.navare@intel.com
2018-11-29drm/i915: Decouple SKL stride units from intel_fb_stride_alignment()Ville Syrjälä1-11/+17
In the future framebuffer stride alignment requirements won't exactly match the units in which skl+ plane stride is specified. So extract the code for the skl+ stuff into a separate helper. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180925193714.25280-3-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2018-11-29drm/i915: Make sure fb gtt offsets stay within 32bitsVille Syrjälä2-5/+24
Let's try to make sure the fb offset computations never hit an integer overflow by making sure the entire fb stays below 32bits. framebuffer_check() in the core already does the same check, but as it doesn't know about tiling some things can slip through. Repeat the check in the driver with tiling taken into account. v2: Use add_overflows() after massaging it to work for me (Chris) v3: Call it add_overflow_t() to match min_t() & co. (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181023160201.9840-1-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2018-11-28drm/i915: Pass the plane to icl_program_input_csc_coeff()Ville Syrjälä1-8/+6
On icl+ the plane state that gets passed to update_slave() is not the plane state of the plane we're programming. With NV12 the plane state would be coming from the master (UV) plane whereas the plane we're programming is the slave (Y) plane. For that reason we need to explicitly pass around the slave plane (or we'd have to otherwise deduce it by checking whether we were called via .update_plane() or .update_slave()). In the case of icl_program_input_csc_coeff() it's actually OK to assume that we are always the master plane because the input CSC only exists on HDR planes which can never be a slave plane. But for consistency let's pass in the plane explicitly anyway. While at it drop the "_coeff" from the function name since it's kinda redundant, and this makes the name a bit shorter :) Cc: Uma Shankar <uma.shankar@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114210729.16185-14-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
2018-11-28drm/i915: Rename the confusing 'plane_id' to 'color_plane'Ville Syrjälä1-4/+4
A variable whose name is 'plane_id' is expected to be of the enum plane_id type. In this case we have a raw int, which turns out to refer to the plane of the framebuffer. Rename the variable to 'color_plane' in line with the trend started earlier. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114210729.16185-13-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2018-11-28drm/i915: Commit skl+ planes in an order that avoids ddb overlapsVille Syrjälä3-18/+93
skl+ can go belly up if there are overlapping ddb allocations between planes. If we could absolutely guarantee that we can perform the atomic update within a single frame we shouldn't have to worry about this. But we can't rely on that so let's steal the ddb overlap check trick from skl_update_crtcs() and apply it to the plane updates. Since each step of the sequence is free from ddb overlaps we don't have to worry about a vblank sneaking up on us in the middle of the sequence. The partial state that gets latched by the hardware will be safe. And unlike skl_update_crtcs() we don't have to intoduce any extra vblank waits on account of only having to worry about a single pipe. v2: Fix typo in commit msg (Matt) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114210729.16185-12-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2018-11-28drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+Ville Syrjälä7-207/+260
On SKL+ the plane WM/BUF_CFG registers are a proper part of each plane's register set. That means accessing them will cancel any pending plane update, and we would need a PLANE_SURF register write to arm the wm/ddb change as well. To avoid all the problems with that let's just move the wm/ddb programming into the plane update/disable hooks. Now all plane registers get written in one (hopefully atomic) operation. To make that feasible we'll move the plane ddb tracking into the crtc state. Watermarks were already tracked there. v2: Rebase due to input CSC v3: Split out a bunch of junk (Matt) v4: Add skl_wm_add_affected_planes() to deal with cursor special case and non-zero wm register reset value v5: Drop the unrelated for_each_intel_plane_mask() fix (Matt) Remove the redundant ddb memset() (Matt) Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #v3 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181127165900.31298-1-ville.syrjala@linux.intel.com
2018-11-28drm/i915: Don't pass dev_priv around so muchVille Syrjälä1-14/+13
Simplify the calling convention of the skl+ watermark functions by not passing around dev_priv needlessly. The callees have what they need to dig it out anyway. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114210729.16185-10-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2018-11-28drm/i915: Clean up skl+ vs. icl+ watermark computationVille Syrjälä1-77/+92
Make a cleaner split between the skl+ and icl+ ways of computing watermarks. This way skl_build_pipe_wm() doesn't have to know any of the gritty details of icl+ master/slave planes. We can also simplify a bunch of the lower level code by pulling the plane visibility checks a bit higher up. v2: WARN_ON(!visible) for the icl+ master plane case (Matt) Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181127165726.31122-1-ville.syrjala@linux.intel.com
2018-11-28drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()Ville Syrjälä1-9/+7
We have to pass both level 0 watermark struct and the transition watermark struct to skl_compute_transition_wm(). Make life less confusing by just passing the entire plane watermark struct that contains both aforementioned structures. Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114210729.16185-8-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2018-11-28drm/i915: Remove some useless zeroing on skl+ wm calculationsVille Syrjälä1-12/+4
We memset(0) the entire watermark struct the start, so there's no need to clear things later on. v2: Rebase due to some stale w/a removal Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114210729.16185-7-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2018-11-28drm/i915: Fix latency==0 handling for level 0 watermark on skl+Ville Syrjälä1-2/+4
If the level 0 latency is 0 we can't do anything. Return an error rather than success. While this can't happen due to WaWmMemoryReadLatency, it can happen if the user clears out the level 0 latency via debugfs. v2: Clarify how how we can end here with zero level 0 latency (Matt) Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114210729.16185-6-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2018-11-28drm/i915: Pass the new crtc_state to ->disable_plane()Ville Syrjälä5-21/+42
We're going to need access to the new crtc state in ->disable_plane() for SKL+ wm/ddb programming and pre-skl pipe gamma/csc control. Pass the crtc state down. We'll also try to make intel_crtc_disable_planes() do the right thing as much as it's possible. The fact that we don't have a separate crtc state for the disabled state when we're going to re-enable the crtc later means we might end up poking at a few extra planes in there. But that's harmless. I suppose one might argue that we wouldn't have to care about proper ddb/wm/csc/gamma if the pipe is going to permanently disable anyway, but the state checker probably cares so we should try our best to make sure everything is programmed correctly even in that case. v2: Fix the commit message a bit (Matt) Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114210729.16185-5-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2018-11-28drm/i915: Introduce crtc_state->update_planes bitmaskVille Syrjälä4-5/+12
Keep track which planes need updating during the commit. For now we set the bit for any plane that was or will be visible (including icl+ nv12 slave planes). In the future I'll have need to update invisible planes as well, for skl plane ddbs and for pre-skl pipe gamma/csc control (which lives in the primary plane control register). v2: Pimp the commit message to mention icl+ nv12 slave planes (Matt) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181127163742.30215-1-ville.syrjala@linux.intel.com
2018-11-28drm/i915: Move single buffered plane register writes to the endVille Syrjälä1-2/+2
The plane color correction registers are single buffered. So ideally we would write them at the start of vblank just after the double buffered plane registers have been latched. Since we have no convenient way to do that for now let's at least move the single buffered register writes to happen after the double buffered registers have been written. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114210729.16185-3-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2018-11-28drm/i915: Reorganize plane register writes to make them more atomicVille Syrjälä2-62/+86
Some observations about the plane registers: - the control register will self-arm if the plane is not already enabled, thus we want to write it as close to (or ideally after) the surface register - tileoff/linoff/offset/aux_offset are self-arming as well so we want them close to the surface register as well - color keying registers we maybe self arming before SKL. Not 100% sure but we can try to keep them near to the surface register as well - chv pipe b csc register are double buffered but self arming so moving them down a bit - the rest should be mostly armed by the surface register so we can safely write them first, and to just for some consistency let's try to follow keep them in order based on the register offset None of this will have any effect of course unless the vblank evasion fails (which it still does sometimes). Another potential future benefit might be pulling the non-self armings registers outside the vblank evasion since they won't latch until the arming register has been written. This would make the critical section a bit lighter and thus less likely to exceed the deadline. v2: Rebase due to input CSC v3: Swap LINOFF/TILEOFF and KEYMSK/KEYMAX to actually follow the last rule above (Matt) Add a bit more rationale to the commit message (Matt) Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114210729.16185-2-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2018-11-28drm/i915: Mark up early pre-production KabylakesChris Wilson3-17/+1
Mark A0 as the one and only pre-production variant of Kabylake and remove its couple of workarounds, consigning them to the annals of history. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181128135325.10641-1-chris@chris-wilson.co.uk
2018-11-27drm/dsc: Add helpers for DSC picture parameter set infoframesManasi Navare2-1/+229
According to Display Stream compression spec 1.2, the picture parameter set metadata is sent from source to sink device using the DP Secondary data packet. An infoframe is formed for the PPS SDP header and PPS SDP payload bytes. This patch adds helpers to fill the PPS SDP header and PPS SDP payload according to the DSC 1.2 specification. v7: * Use BUILD_BUG_ON() to protect changing struct size (Ville) * Remove typecaseting (Ville) * Include byteorder.h in drm_dsc.c (Ville) * Correct kernel doc spacing (Anusha) v6: * Use proper sequence points for breaking down the assignments (Chris Wilson) * Use SPDX identifier v5: Do not use bitfields for DRM structs (Jani N) v4: * Use DSC constants for params that dont change across configurations v3: * Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst (Daniel Vetter) v2: * Add EXPORT_SYMBOL for the drm functions (Manasi) Cc: dri-devel@lists.freedesktop.org Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Sean Paul <seanpaul@chromium.org> (For merging through drm-intel) Link: https://patchwork.freedesktop.org/patch/msgid/20181127214125.17658-5-manasi.d.navare@intel.com
2018-11-27drm/dsc: Modify DRM helper to return complete DSC color depth capabilitiesManasi Navare1-6/+8
DSC DPCD color depth register advertises its color depth capabilities by setting each of the bits that corresponding to a specific color depth. This patch defines those specific color depths and adds a helper to return an array of color depth capabilities. v2: * Simplify the logic (Ville) Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Acked-by: Sean Paul <seanpaul@chromium.org> (For merging through drm-intel) Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181127214125.17658-1-manasi.d.navare@intel.com
2018-11-27drm/i915: Skip engine serialisation for no-op seqno resetChris Wilson1-0/+3
If the engine's seqno is already at our target seqno (most likely it hasn't been used since the last reset), we can skip serialising the engine and leave it as is. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181126095610.20962-1-chris@chris-wilson.co.uk
2018-11-26drm/i915/ringbuffer: 2-step restartChris Wilson1-2/+9
We may be simply restarting too fast for the culmudgeonly gen3/gen4 as we still see missing interrupts following a reset. So let's try restarting a little slower, first wake up the ring empty and then tell it about the work it has to perform. References: https://bugs.freedesktop.org/show_bug.cgi?id=108735 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181126122821.4537-1-chris@chris-wilson.co.uk
2018-11-23drm/i915: Cache the error stringChris Wilson4-175/+243
Currently, we convert the error state into a string every time we read from sysfs (and sysfs reads in page size (4KiB) chunks). We do try to window the string and only capture the portion that is being read, but that means that we must always convert up to the window to find the start. For a very large error state bordering on EXEC_OBJECT_CAPTURE abuse, this is noticeable as it degrades to O(N^2)! As we do not have a convenient hook for sysfs open(), and we would like to keep the lazy conversion into a string, do the conversion of the whole string on the first read and keep the string until the error state is freed. v2: Don't double advance simple_read_from_buffer v3: Due to extreme pain of lack of vrealloc, use a scatterlist v4: Keep the forward iterator loosely cached v5: Stylistic improvements to reduce patch size Reported-by: Jason Ekstrand <jason@jlekstrand.net> Testcase: igt/gem_exec_capture/many* Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181123132325.26541-1-chris@chris-wilson.co.uk
2018-11-22drm/i915/hsw: Drop the stereo 3D enabled check in psr_compute_config()José Roberto de Souza1-7/+0
We should not access hardware while computing config also we don't support stereo 3D so this test was never true. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181121225441.18785-6-jose.souza@intel.com
2018-11-22drm/i915: Keep PSR disabled after a driver reload after a PSR errorJosé Roberto de Souza1-0/+18
If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR will still keep the error set even after the reset done in the irq_preinstall and irq_uninstall hooks. And enabling in this situation cause the screen to freeze in the first time that PSR HW tries to activate so lets keep PSR disabled to avoid any rendering problems. v5: rebased: using edp_psr_shift() v4: Moved handling from intel_psr_compute_config() to intel_psr_init() to avoid hardware access during compute(Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> squash Link: https://patchwork.freedesktop.org/patch/msgid/20181121225441.18785-5-jose.souza@intel.com
2018-11-22drm/i915: Disable PSR when a PSR aux error happenJosé Roberto de Souza2-4/+38
While PSR is active hardware will do aux transactions by it self to wakeup sink to receive a new frame when necessary. If that transaction is not acked by sink, hardware will trigger this interruption. So let's disable PSR as it is a hint that there is problem with this sink. The removed FIXME was asking to manually train the link but we don't need to do that as by spec sink should do a short pulse when it is out of sync with source, we just need to make sure it is awaken and the SDP header with PSR inactive set it will trigger the short pulse with a error set in the link status. v3: added workarround to fix scheduled work starvation cause by to frequent PSR error interruption v4: only setting irq_aux_error as we don't care in clear it and not using dev_priv->irq_lock as consequence. v5: rebased: using edp_psr_shift() Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181121225441.18785-4-jose.souza@intel.com
2018-11-22drm/i915: Do not enable PSR in the next modeset after a errorJosé Roberto de Souza2-1/+10
When we detect a error and disable PSR, it is kept disabled until the next modeset but as the sink already show signs that it do not properly work with PSR lets disabled it for good to avoid any additional flickering. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181121225441.18785-3-jose.souza@intel.com
2018-11-22drm/i915: Check PSR errors instead of retrain while PSR is enabledJosé Roberto de Souza3-0/+27
When a PSR error happens sink sets the PSR error register and also set the link status to a error status. So in the short pulse handling it was returning earlier and doing a full detection and attempting to retrain but it fails as PSR HW is in change of the main-link. Just call intel_psr_short_pulse() before intel_dp_needs_link_retrain() is not the right fix as intel_dp_needs_link_retrain() would return true and trigger a full detection while PSR HW is still in change of main-link. Check for PSR active is also not safe as it could be inactive due a frontbuffer invalidate and still doing the PSR exit sequence. v3: added comment in intel_dp_needs_link_retrain() Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181121225441.18785-2-jose.souza@intel.com
2018-11-22drm/i915: Avoid a full port detection in the first eDP short pulseJosé Roberto de Souza1-18/+26
Some eDP panels do not set a valid sink count value and even for the ones that sets is should always be one for eDP, that is why it is not cached in intel_edp_init_dpcd(). But intel_dp_short_pulse() compares the old count with the read one if there is a mistmatch a full port detection will be executed, what was happening in the first short pulse interruption of eDP panels that sets sink count. Instead of just skip the compasison for eDP panels, lets not read the sink count at all for eDP. v2: the previous version of this patch it was caching the sink count in intel_edp_init_dpcd() but I was pointed out by Ville a patch that handled a case of a eDP panel that do not set sink count and as sink count is not used to eDP certification was choosed to just not read it at all. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181121225441.18785-1-jose.souza@intel.com
2018-11-22drm/i915: Synchronize hpd work in i915_hpd_storm_ctl_show()Lyude Paul1-0/+7
While trying to add a chamelium test for short HPD IRQs, I ran into issues where a hotplug storm would be triggered, but the point at which it would be reported by the kernel would be after igt actually finished checking i915_hpd_storm_ctl's status. So, fix this by simply synchronizing our IRQ work, dig_port_work, and hotplug_work before printing out the HPD storm status in i915_hpd_storm_ctl_show(). Signed-off-by: Lyude Paul <lyude@redhat.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20181121003718.17704-1-lyude@redhat.com
2018-11-22drm/i915: Eliminate the horrendous format check codeVille Syrjälä1-97/+8
Replace the messy framebuffer format/modifier validation code with a single call to drm_any_plane_has_format(). The code was extremely annoying to maintain as you had to have a lot of platform checks for different formats. The new code requires zero maintenance. v2: Nuke the modifier checks as well since the core does that too now v3: Call drm_any_plane_has_format() from the driver code v4: Rebase Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181029183453.28541-2-ville.syrjala@linux.intel.com Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
2018-11-22drm/i915: Update DRIVER_DATE to 20181122Jani Nikula1-1/+1
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2018-11-22drm/i915: Update DRIVER_DATE to 20181122Jani Nikula1-2/+2
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2018-11-22drm/i915: avoid rebuilding i915_gpu_error.o on version string updatesHans Holmberg1-2/+2
There is no need to rebuild i915_gpu_error.o when the version string changes as the version is available in init_utsname()->release. Signed-off-by: Hans Holmberg <hans.holmberg@cnexlabs.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181121095423.20760-1-hans.ml.holmberg@owltronix.com
2018-11-21drm/i915: Show waiter's status on engine dumpChris Wilson1-2/+4
When showing the list of waiters, include the task's status so that we can tell if they have been woken up and are waiting for the CPU, or if they are still waiting to be woken. v2: task_state_to_char() Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181121151653.24595-1-chris@chris-wilson.co.uk
2018-11-21drm/i915: Add rotation readout for plane initial configVille Syrjälä2-0/+32
If we need to force a full plane update before userspace/fbdev have given us a proper plane state we should try to maintain the current plane state as much as possible (apart from the parts of the state we're trying to fix up with the plane update). To that end add basic readout for the plane rotation and maintain it during the initial fb takeover. Cc: Hans de Goede <hdegoede@redhat.com> Fixes: 516a49cc1946 ("drm/i915: Fix assert_plane() warning on bootup with external display") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181120135450.3634-2-ville.syrjala@linux.intel.com Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2018-11-21drm/i915: Force a LUT update in intel_initial_commit()Ville Syrjälä1-0/+8
If we force a plane update to fix up our half populated plane state we'll also force on the pipe gamma for the plane (since we always enable pipe gamma currently). If the BIOS hasn't programmed a sensible LUT into the hardware this will cause the image to become corrupted. Typical symptoms are a purple/yellow/etc. flash when the driver loads. To avoid this let's program something sensible into the LUT when we do the plane update. In the future I plan to add proper plane gamma enable readout so this is just a temporary measure. Cc: Hans de Goede <hdegoede@redhat.com> Fixes: 516a49cc1946 ("drm/i915: Fix assert_plane() warning on bootup with external display") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181120135450.3634-1-ville.syrjala@linux.intel.com Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-11-21drm/i915: Make CHICKEN_TRANS reg not depend on enum valueImre Deak3-17/+52
Depending on the transcoder enum values to translate from transcoder to the corresponding CHICKEN_TRANS register can easily break if we add a new transcoder. Add an explicit mapping instead, by using helpers to look up the register instance either by transcoder or port (since unconveniently the registers have both port and transcoder specific bits). While at it also check for the correctness of GEN, port, transcoder. I wasn't sure if psr2_enabled can only be set for GEN9+, but that seems to be the case indeed (see setting of sink_psr2_support in intel_psr_init_dpcd()). v2 (Ville): - Make gen9_chicken_trans_reg() internal to intel_psr.c. - s/trans/cpu_transcoder/ Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181119180021.370-1-imre.deak@intel.com
2018-11-21drm/i915: Add code comment on assumption of pipe==transcoderImre Deak1-3/+19
Add a comment to the pipe and transcoder enum definitions about our assumption in the code about enum values for pipes and transcoders with a 1:1 transcoder -> pipe mapping. v2: - Clarify more what are the assumptions about the enum values. (Ville) v3: (Lucas) - s/->/ -> / so it looks less like pointer dereferencing. - Use pipe enums as initializers in the transcoder enum definition. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2) Link: https://patchwork.freedesktop.org/patch/msgid/20181120092325.21249-3-imre.deak@intel.com
2018-11-21drm/i915: Make EDP PSR flags not depend on enum valuesImre Deak2-21/+44
Depending on the transcoder enum values to translate from transcoder to EDP PSR flags can easily break if we add a new transcoder. So remove the dependency by using an explicit mapping. While at it also add a WARN for unexpected trancoders. v2: - Simplify things by defining flag shift values instead of indices. - s/trans/cpu_transcoder/ (Ville) v3: - Define flags to look like separate bits instead of the values of the same bitfield. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181120092325.21249-2-imre.deak@intel.com
2018-11-21drm/i915: Make pipe/transcoder offsets not depend on enum valuesImre Deak1-14/+38
Depending on the transcoder enum values to translate from transcoder to pipe/transcoder register addresses can easily break if we add a new transcoder. So remove the dependency by using named initializers. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181120092325.21249-1-imre.deak@intel.com
2018-11-21drm/i915: fix spelling mistake "reserverd" -> "reserved"Alexandre Belloni1-1/+1
Fix a spelling mistake in a comment. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181120151415.32419-1-alexandre.belloni@bootlin.com
2018-11-20drm/i915: Downgrade unknown CSR firmware warningsLucas De Marchi1-3/+0
Like it was done in commit 9e180d9991dc ("drm/i915: Downgrade unknown firmware warnings") for huc and guc: downgrade CSR firmware warnings. If we have released no firmware yet for a platform, stop scaring the consumer and merely note its expected absence. By simply removing the warning and early return we hit the condition with the appropriate message. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181117004234.23437-2-lucas.demarchi@intel.com
2018-11-20drm/i915: allow to load DMC firmware on next genLucas De Marchi1-1/+6
Before commit d8a5b7d79fb7 ("drm/i915/csr: keep max firmware size together with firmare name and version") it was possible to load the firmware for testing purposes via parameter. Let's use the size of the last known platform to recover that behavior. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181117004234.23437-1-lucas.demarchi@intel.com
2018-11-20drm/i915/ilk: Fix warning when reading emon_status with no outputJosé Roberto de Souza1-0/+4
When there is no output no one will hold a runtime_pm reference causing a warning when trying to read emom_status in debugfs. [22.756480] ------------[ cut here ]------------ [22.756489] RPM wakelock ref not held during HW access [22.756578] WARNING: CPU: 0 PID: 1058 at drivers/gpu/drm/i915/intel_drv.h:2104 gen5_read32+0x16b/0x1a0 [i915] [22.756580] Modules linked in: snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic i915 coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel snd_hda_intel snd_hda_codec snd_hwdep snd_hda_core e1000e snd_pcm mei_me prime_numbers mei lpc_ich [22.756595] CPU: 0 PID: 1058 Comm: debugfs_test Not tainted 4.20.0-rc1-CI-Trybot_3219+ #1 [22.756597] Hardware name: Hewlett-Packard HP Compaq 8100 Elite SFF PC/304Ah, BIOS 786H1 v01.13 07/14/2011 [22.756634] RIP: 0010:gen5_read32+0x16b/0x1a0 [i915] [22.756637] Code: a4 ea e0 0f 0b e9 d2 fe ff ff 80 3d a5 71 19 00 00 0f 85 d3 fe ff ff 48 c7 c7 48 d0 2d a0 c6 05 91 71 19 00 01 e8 35 a4 ea e0 <0f> 0b e9 b9 fe ff ff e8 69 c6 f2 e0 85 c0 75 92 48 c7 c2 78 d0 2d [22.756639] RSP: 0018:ffffc90000f1fd38 EFLAGS: 00010282 [22.756642] RAX: 0000000000000000 RBX: ffff8801f7ab0000 RCX: 0000000000000006 [22.756643] RDX: 0000000000000006 RSI: ffffffff8212886a RDI: ffffffff820d6d57 [22.756645] RBP: 0000000000011020 R08: 0000000043e3d1a8 R09: 0000000000000000 [22.756647] R10: ffffc90000f1fd80 R11: 0000000000000000 R12: 0000000000000001 [22.756649] R13: ffff8801f7ab0068 R14: 0000000000000001 R15: ffff88020d53d188 [22.756651] FS: 00007f2878849980(0000) GS:ffff880213a00000(0000) knlGS:0000000000000000 [22.756653] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [22.756655] CR2: 00005638deedf028 CR3: 0000000203292001 CR4: 00000000000206f0 [22.756657] Call Trace: [22.756689] i915_mch_val+0x1b/0x60 [i915] [22.756721] i915_emon_status+0x45/0xd0 [i915] [22.756730] seq_read+0xdb/0x3c0 [22.756736] ? lockdep_hardirqs_off+0x94/0xd0 [22.756740] ? __slab_free+0x24e/0x510 [22.756746] full_proxy_read+0x52/0x90 [22.756752] __vfs_read+0x31/0x170 [22.756759] ? do_sys_open+0x13b/0x240 [22.756763] ? rcu_read_lock_sched_held+0x6f/0x80 [22.756766] vfs_read+0x9e/0x140 [22.756770] ksys_read+0x50/0xc0 [22.756775] do_syscall_64+0x55/0x190 [22.756781] entry_SYSCALL_64_after_hwframe+0x49/0xbe [22.756783] RIP: 0033:0x7f28781dc34e [22.756786] Code: 00 00 00 00 48 8b 15 71 8c 20 00 f7 d8 64 89 02 48 c7 c0 ff ff ff ff c3 0f 1f 40 00 8b 05 ba d0 20 00 85 c0 75 16 31 c0 0f 05 <48> 3d 00 f0 ff ff 77 5a f3 c3 0f 1f 84 00 00 00 00 00 41 54 55 49 [22.756787] RSP: 002b:00007ffd33fa0d08 EFLAGS: 00000246 ORIG_RAX: 0000000000000000 [22.756790] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f28781dc34e [22.756792] RDX: 0000000000000200 RSI: 00007ffd33fa0d50 RDI: 0000000000000008 [22.756794] RBP: 00007ffd33fa0f60 R08: 0000000000000000 R09: 0000000000000020 [22.756796] R10: 0000000000000000 R11: 0000000000000246 R12: 00005638de45c2c0 [22.756797] R13: 00007ffd33fa14b0 R14: 0000000000000000 R15: 0000000000000000 [22.756806] irq event stamp: 47950 [22.756811] hardirqs last enabled at (47949): [<ffffffff810fba74>] vprintk_emit+0x124/0x320 [22.756813] hardirqs last disabled at (47950): [<ffffffff810019b0>] trace_hardirqs_off_thunk+0x1a/0x1c [22.756816] softirqs last enabled at (47518): [<ffffffff81c0033a>] __do_softirq+0x33a/0x4b9 [22.756820] softirqs last disabled at (47479): [<ffffffff8108df29>] irq_exit+0xa9/0xc0 [22.756858] WARNING: CPU: 0 PID: 1058 at drivers/gpu/drm/i915/intel_drv.h:2104 gen5_read32+0x16b/0x1a0 [i915] [22.756860] ---[ end trace bf56fa7d6a3cbf7a ] Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181119230101.32460-1-jose.souza@intel.com
2018-11-20drm/i915/selftests: Hold task reference to reset workerChris Wilson1-0/+3
As the worker may exit by itself, we need to hold a task reference to it in the parent. References: https://bugs.freedesktop.org/show_bug.cgi?id=108735 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181120120601.24083-1-chris@chris-wilson.co.uk
2018-11-20Merge drm/drm-next into drm-intel-next-queuedJani Nikula401-9102/+12174
Pull in v4.20-rc3 via drm-next. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2018-11-20drm/i915/fixed: cosmetic cleanupJani Nikula1-36/+41
Clean up fixed point temp variable initialization, use the more conventional tmp name for temp variables, add empty lines before return. No functional changes. Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181116120729.7580-5-jani.nikula@intel.com
2018-11-20drm/i915/fixed: simplify is_fixed16_zero()Jani Nikula1-3/+1
Simply return the condition. No functional changes. Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181116120729.7580-4-jani.nikula@intel.com
2018-11-20drm/i915/fixed: simplify FP_16_16_MAX definitionJani Nikula1-5/+1
No need to use a compound statement enclosed in parenthesis where a C99 compound literal will do. No functional changes. Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181116120729.7580-3-jani.nikula@intel.com
2018-11-20drm/i915/fixed: prefer kernel types over stdint typesJani Nikula1-32/+29
While at it, conform to kernel spacing (i.e. no space) after cast. No functional changes. Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181116120729.7580-2-jani.nikula@intel.com
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-16 09:30:18 +0000