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2024-03-13Merge branches 'clk-renesas', 'clk-cleanup', 'clk-hisilicon', 'clk-mediatek' ↵Stephen Boyd15-28/+89
and 'clk-bulk' into clk-next - Add a devm_clk_bulk_get_all_enable() API to get and enable all clks for a device - Fix some static checker errors in the hisilicon clk driver * clk-renesas: (25 commits) clk: renesas: r8a779h0: Add RPC-IF clock clk: renesas: r8a779h0: Add SYS-DMAC clocks clk: renesas: r8a779h0: Add SDHI clock clk: renesas: r8a779h0: Add EtherAVB clocks clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux clk: renesas: r8a779f0: Correct PFC/GPIO parent clock clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks clk: renesas: r8a779h0: Add I2C clocks clk: renesas: r8a779h0: Add watchdog clock clk: renesas: r8a779h0: Add PFC/GPIO clocks clk: renesas: r8a779g0: Fix PCIe clock name clk: renesas: cpg-mssr: Add support for R-Car V4M clk: renesas: rcar-gen4: Add support for FRQCRC1 clk: renesas: r9a07g043: Add clock and reset entries for CRU clk: renesas: r9a08g045: Add clock and reset support for watchdog dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support dt-bindings: power: Add r8a779h0 SYSC power domain definitions dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support ... * clk-cleanup: clk: zynq: Prevent null pointer dereference caused by kmalloc failure clk: fractional-divider: Use bit operations consistently clk: fractional-divider: Move mask calculations out of lock clk: ti: dpll3xxx: use correct function names in kernel-doc clk: clocking-wizard: Remove redundant initialization of pointer div_addr clk: keystone: sci-clk: match func name comment to actual clk: cdce925: Remove redundant assignment to variable 'rate' MAINTAINERS: drop Sekhar Nori * clk-hisilicon: clk: hisilicon: Use devm_kcalloc() instead of devm_kzalloc() clk: hisilicon: hi3559a: Fix an erroneous devm_kfree() clk: hisilicon: hi3519: Release the correct number of gates in hi3519_clk_unregister() * clk-mediatek: clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in clk_mt8173_apmixed_probe() clk: mediatek: add infracfg reset controller for mt7988 dt-bindings: reset: mediatek: add MT7988 infracfg reset IDs dt-bindings: clock: mediatek: convert SSUSBSYS to the json-schema clock dt-bindings: clock: mediatek: convert PCIESYS to the json-schema clock dt-bindings: clock: mediatek: convert hifsys to the json-schema clock clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical clk: mediatek: mt8183: Correct parent of CLK_INFRA_SSPM_32K_SELF clk: mediatek: mt7622-apmixedsys: Fix an error handling path in clk_mt8135_apmixed_probe() clk: mediatek: mt8135: Fix an error handling path in clk_mt8135_apmixed_probe() * clk-bulk: clk: Provide managed helper to get and enable bulk clocks
2024-03-08clk: zynq: Prevent null pointer dereference caused by kmalloc failureDuoming Zhou1-5/+3
The kmalloc() in zynq_clk_setup() will return null if the physical memory has run out. As a result, if we use snprintf() to write data to the null address, the null pointer dereference bug will happen. This patch uses a stack variable to replace the kmalloc(). Fixes: 0ee52b157b8e ("clk: zynq: Add clock controller driver") Suggested-by: Michal Simek <michal.simek@amd.com> Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Duoming Zhou <duoming@zju.edu.cn> Link: https://lore.kernel.org/r/20240301084437.16084-1-duoming@zju.edu.cn Acked-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-03-08clk: fractional-divider: Use bit operations consistentlyAndy Shevchenko1-4/+4
Use BIT() where makes sense. This alings usage of bit operations in the same pieces of code. Moreover, strictly speaking by the letter of the C standard, left shift of 1 by 31 bits is UB (undefined behaviour), switching to BIT() addresses that as well. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240303120732.240355-1-andy.shevchenko@gmail.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-03-08clk: fractional-divider: Move mask calculations out of lockAndy Shevchenko1-3/+3
There is no need to calculate masks under the lock taken. Move them out of it. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240303121410.240761-1-andy.shevchenko@gmail.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-28clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in ↵Markus Elfring1-2/+3
clk_mt8173_apmixed_probe() Add a label so that a bit of exception handling can be better reused at the end of this function implementation. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Link: https://lore.kernel.org/r/6a64e7b3-b1ce-46c4-9c85-89f731aee592@web.de Reviewed-by: AngeloGiaocchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-28clk: ti: dpll3xxx: use correct function names in kernel-docRandy Dunlap1-2/+2
Use function names that match the implementation in kernel-doc comments to avoid kernel-doc warnings: dpll3xxx.c:938: warning: expecting prototype for omap3_non_core_dpll_save_context(). Prototype was for omap3_noncore_dpll_save_context() instead dpll3xxx.c:967: warning: expecting prototype for omap3_core_dpll_restore_context(). Prototype was for omap3_noncore_dpll_restore_context() instead Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Tero Kristo <kristo@kernel.org> Cc: linux-omap@vger.kernel.org Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Link: https://lore.kernel.org/r/20240115054739.4988-1-rdunlap@infradead.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-28clk: clocking-wizard: Remove redundant initialization of pointer div_addrColin Ian King1-1/+1
The pointer div_addr is being assigned a value that is never used, it is being re-assigned a different value near the end of the function where it is being read in the next statement. The initialization is redundant and can be removed. Cleans up clang scan build warning: drivers/clk/xilinx/clk-xlnx-clock-wizard.c:501:16: warning: Value stored to 'div_addr' during its initialization is never read [deadcode.DeadStores] Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20240223134347.3908301-1-colin.i.king@gmail.com Reviewed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21clk: keystone: sci-clk: match func name comment to actualRandy Dunlap1-1/+1
Correct the function name in the kernel-doc comment to match the actual function name to avoid a kernel-doc warning: drivers/clk/keystone/sci-clk.c:287: warning: expecting prototype for _sci_clk_get(). Prototype was for _sci_clk_build() instead Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Nishanth Menon <nm@ti.com> Cc: Tero Kristo <kristo@kernel.org> Cc: Santosh Shilimkar <ssantosh@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Link: https://lore.kernel.org/r/20240115001255.4124-1-rdunlap@infradead.org Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21clk: cdce925: Remove redundant assignment to variable 'rate'Colin Ian King1-1/+0
The variable 'rate' being assigned a value that is never read, the assignment is redundant and can be removed. Cleans up clang scan build warning: drivers/clk/clk-cdce925.c:104:3: warning: Value stored to 'rate' is never read [deadcode.DeadStores] Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20240216140132.2108665-1-colin.i.king@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21clk: Provide managed helper to get and enable bulk clocksShradha Todi1-0/+40
Provide a managed devm_clk_bulk* wrapper to get and enable all bulk clocks in order to simplify drivers that keeps all clocks enabled for the time of driver operation. Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Shradha Todi <shradha.t@samsung.com> Link: https://lore.kernel.org/r/20240220084046.23786-2-shradha.t@samsung.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21clk: mediatek: add infracfg reset controller for mt7988Frank Wunderlich1-0/+23
Infracfg can also operate as reset controller, add support for it. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240201182409.39878-3-linux@fw-web.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as criticalDaniel Golle1-2/+3
Without the SGM_REG_SEL clock enabled the cpu freezes if trying to access registers used by MT7981 clock drivers itself. Mark SGM_REG_SEL as critical to make sure it is always enabled to prevent freezes on boot even if the Ethernet driver which prepares and enables the clock is not loaded or probed at a later point. Fixes: 813c3b53b55b ("clk: mediatek: add MT7981 clock support") Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/fc157139e6b7f8dfb6430ac7191ba754027705e8.1708221995.git.daniel@makrotopia.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21clk: mediatek: mt8183: Correct parent of CLK_INFRA_SSPM_32K_SELFChen-Yu Tsai1-1/+1
CLK_INFRA_SSPM_32K_SELF has the "f_f26m_ck" clock assigned as its parent. This is inconsistent as the clock is part of a group that are all gates without dividers, and this makes the kernel think it runs at 26 MHz. After clarification from MediaTek engineers, the correct parent is actually the system 32 KHz clock. Fixes: 1eb8d61ac5c9 ("clk: mediatek: mt8183: Add back SSPM related clocks") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20240219105125.956278-1-wenst@chromium.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21clk: mediatek: mt7622-apmixedsys: Fix an error handling path in ↵Christophe JAILLET1-1/+0
clk_mt8135_apmixed_probe() 'clk_data' is allocated with mtk_devm_alloc_clk_data(). So calling mtk_free_clk_data() explicitly in the remove function would lead to a double-free. Remove the redundant call. Fixes: c50e2ea6507b ("clk: mediatek: mt7622-apmixedsys: Add .remove() callback for module build") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/2c553c2a5077757e4f7af0bb895acc43881cf62c.1704616152.git.christophe.jaillet@wanadoo.fr Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21clk: mediatek: mt8135: Fix an error handling path in clk_mt8135_apmixed_probe()Christophe JAILLET1-1/+3
If an error occurs after mtk_alloc_clk_data(), mtk_free_clk_data() should be called, as already done in the remove function. Fixes: 54b7026f011e ("clk: mediatek: mt8135-apmixedsys: Convert to platform_driver and module") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/6cd6af61e5a91598068227f1f68cfcfde1507453.1704615011.git.christophe.jaillet@wanadoo.fr Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21clk: hisilicon: Use devm_kcalloc() instead of devm_kzalloc()Erick Archer1-2/+1
As noted in the "Deprecated Interfaces, Language Features, Attributes, and Conventions" documentation [1], size calculations (especially multiplication) should not be performed in memory allocator (or similar) function arguments due to the risk of them overflowing. This could lead to values wrapping around and a smaller allocation being made than the caller was expecting. Using those allocations could lead to linear overflows of heap memory and other misbehaviors. So, use the purpose specific devm_kcalloc() function instead of the argument size * count in the devm_kzalloc() function. Link: https://www.kernel.org/doc/html/next/process/deprecated.html#open-coded-arithmetic-in-allocator-arguments [1] Link: https://github.com/KSPP/linux/issues/162 Signed-off-by: Erick Archer <erick.archer@gmx.com> Link: https://lore.kernel.org/r/20240121142946.2796-1-erick.archer@gmx.com Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21clk: hisilicon: hi3559a: Fix an erroneous devm_kfree()Christophe JAILLET1-1/+0
'p_clk' is an array allocated just before the for loop for all clk that need to be registered. It is incremented at each loop iteration. If a clk_register() call fails, 'p_clk' may point to something different from what should be freed. The best we can do, is to avoid this wrong release of memory. Fixes: 6c81966107dc ("clk: hisilicon: Add clock driver for hi3559A SoC") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/773fc8425c3b8f5b0ca7c1d89f15b65831a85ca9.1705850155.git.christophe.jaillet@wanadoo.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-21clk: hisilicon: hi3519: Release the correct number of gates in ↵Christophe JAILLET1-1/+1
hi3519_clk_unregister() The gates are stored in 'hi3519_gate_clks', not 'hi3519_mux_clks'. This is also in line with how hisi_clk_register_gate() is called in the probe. Fixes: 224b3b262c52 ("clk: hisilicon: hi3519: add driver remove path and fix some issues") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/c3f1877c9a0886fa35c949c8f0ef25547f284f18.1704912510.git.christophe.jaillet@wanadoo.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-20clk: renesas: r8a779h0: Add RPC-IF clockCong Dang1-0/+1
Add the module clock used by the SPI Multi I/O Bus Controller (RPC-IF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/07a72378ca64b44341af960f042a6efd41d10dc3.1708354355.git.geert+renesas@glider.be
2024-02-20clk: renesas: r8a779h0: Add SYS-DMAC clocksCong Dang1-0/+2
Add the module clocks used by the Direct Memory Access Controllers for System (SYS-DMAC) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/0285ef5d0c0c9d232e196559c9130ab46733d7f7.1707915706.git.geert+renesas@glider.be
2024-02-20clk: renesas: r8a779h0: Add SDHI clockCong Dang1-0/+1
Add the SDHI module clock, which is used by the SD Card/MMC Interface on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/3a604a6924043775c2ed0630b1c5c29be2d1a5b9.1707915642.git.geert+renesas@glider.be
2024-02-20clk: renesas: r8a779h0: Add EtherAVB clocksCong Dang1-0/+3
Add the module clocks used by the Ethernet AVB (EtherAVB-IF) blocks on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a5b4252d9822ded3fd523bc35417306cae2ec2bd.1707661303.git.geert+renesas@glider.be
2024-02-13clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variableClaudiu Beznea2-6/+6
Fix typo for sel_shdi variable. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240131102930.1841901-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-02-13clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 muxClaudiu Beznea2-2/+2
The status configuration for SD1 mux clock is SEL_SDHI1_STS. Fix it. Fixes: 16b86e5c03c5 ("clk: renesas: rzg2l: Refactor SD mux driver") Reported-by: Hien Huynh <hien.huynh.px@renesas.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240131102930.1841901-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-02-13clk: renesas: r8a779f0: Correct PFC/GPIO parent clockGeert Uytterhoeven1-1/+1
According to the R-Car S4 Series Hardware User’s Manual Rev.0.81, the parent clock of the Pin Function (PFC/GPIO) module clock is the CP clock. As this clock is not documented to exist on R-Car S4, use the CPEX clock instead. Fixes: 73421f2a48e6bd1d ("clk: renesas: r8a779f0: Add PFC clock") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f88ec4aede0eaf0107c8bb7b28ba719ac6cd418f.1706197415.git.geert+renesas@glider.be
2024-02-13clk: renesas: r8a779g0: Correct PFC/GPIO parent clocksGeert Uytterhoeven1-5/+6
According to the R-Car V4H Series Hardware User’s Manual Rev.1.00, the parent clock of the Pin Function (PFC/GPIO) module clocks is the CP clock. Fix this by adding the missing CP clock, and correcting the PFC parents. Fixes: f2afa78d5a0c0b0b ("dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions") Fixes: 36ff366033f0dde1 ("clk: renesas: r8a779g0: Add PFC/GPIO clocks") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/5401fccd204dc90b44f0013e7f53b9eff8df8214.1706197297.git.geert+renesas@glider.be
2024-02-06clk: renesas: r8a779h0: Add I2C clocksCong Dang1-0/+4
Add the module clocks used by the I2C Bus Interfaces on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/7a76dadbce24c81dd2bee68765a0b41beca2d565.1706790236.git.geert+renesas@glider.be
2024-02-06clk: renesas: r8a779h0: Add watchdog clockCong Dang1-0/+1
Add the module clock used by the RCLK Watchdog Timer on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f1dbf0f3f484015f2e629d78b746cf377d6f6746.1706790015.git.geert+renesas@glider.be
2024-02-06clk: renesas: r8a779h0: Add PFC/GPIO clocksCong Dang1-0/+3
Add the module clocks used by the Pin Function Controller (PFC) and General Purpose Input/Output (GPIO) blocks on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/a7d8f4111b87decb825db5ed310de8294f90b9f9.1706266196.git.geert+renesas@glider.be
2024-01-31clk: renesas: r8a779g0: Fix PCIe clock nameGeert Uytterhoeven1-1/+1
Fix a typo in the name of the module clock for the second PCIe channel. Fixes: 5ab16198b431ca48 ("clk: renesas: r8a779g0: Add PCIe clocks") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f582067564f357e2183d3db67b217084ecb51888.1706608032.git.geert+renesas@glider.be
2024-01-31clk: renesas: cpg-mssr: Add support for R-Car V4MCong Dang5-0/+254
Initial CPG support for the R-Car V4M (R8A779H0). Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be
2024-01-31clk: renesas: rcar-gen4: Add support for FRQCRC1Geert Uytterhoeven1-2/+8
R-Car V4H and V4M have a second Frequency Control Register C. Add support for this by treating bit field offsets beyond 31 as referring to the second register. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f64d5573a92a18505619ff0ff808d50cfc2bde55.1706194617.git.geert+renesas@glider.be
2024-01-31clk: renesas: r9a07g043: Add clock and reset entries for CRUBiju Das1-0/+31
Add CRU clock and reset entries to CPG driver. CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular sequence for the CRU block hence add these clocks to r9a07g043_no_pm_mod_clks[] array and pass it as part of CPG data for RZ/G2UL SoCs. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240123114415.290918-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-31clk: renesas: r9a08g045: Add clock and reset support for watchdogClaudiu Beznea1-0/+3
RZ/G3S has a watchdog module accessible by the Cortex-A core. Add clock and reset support for it. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240122111115.2861835-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-23clk: renesas: mstp: Remove obsolete clkdev registrationGeert Uytterhoeven1-13/+3
After the DT conversion of SH-Mobile and Armadillo-800-EVA display support, all devices are registered from DT, so we can remove the registration of clkdevs. Add the missing #include <linux/slab.h>, which was included implicitly through <linux/clkdev.h> before. Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e98a6e47ebecc44fa41de6d88b4ed20c6efbd177.1705931322.git.geert+renesas@glider.be
2024-01-23clk: renesas: cpg-mssr: Ignore all clocks assigned to non-Linux systemKuninori Morimoto1-7/+104
Some boards might use Linux and another OS at the same time. In such case, currently, during booting, Linux will stop necessary module clocks which are not used on the Linux side, but are used by another OS. To avoid such situation, renesas-cpg-mssr tries to find status = "reserved" devices (A), and adds CLK_IGNORE_UNUSED flag to its <&cgp CPG_MOD xxx> clock (B). Table 2.4: Values for status property https://github.com/devicetree-org/devicetree-specification/releases/download/v0.4/devicetree-specification-v0.4.pdf "reserved" Indicates that the device is operational, but should not be used. Typically this is used for devices that are controlled by another software component, such as platform firmware. ex) scif5: serial@e6f30000 { ... (B) clocks = <&cpg CPG_MOD 202>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; ... (A) status = "reserved"; }; Cc: Aymeric Aillet <aymeric.aillet@iot.bzh> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/878r4ygfap.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-19clk: qcom: gcc-x1e80100: Replace of_device.h with explicit includesStephen Rothwell1-1/+2
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. of_device.h isn't needed, but mod_devicetable.h and platform_device.h were implicitly included. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Link: https://lore.kernel.org/r/20231211160510.0aef871b@canb.auug.org.au [robh: Redo commit msg] Signed-off-by: Rob Herring <robh@kernel.org>
2024-01-12Merge tag 'clk-for-linus' of ↵Linus Torvalds71-637/+21379
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Only a couple new SoCs have support added this time, primarily for Qualcomm SM8650 based on the diffstat. Otherwise this is a collection of non-critical fixes and cleanups to various clk drivers and their DT bindings. Nothing is changed in the core clk framework this time, although there's a patch to fix a basic clk type initialization function. In general, this pile looks to be on the smaller side. New Drivers: - Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650 - Mediatek MT7988 SoC clocks Updates: - Update Zynqmp driver for Versal NET platforms - Add clk driver for Versal clocking wizard IP - Support for stm32mp25 clks - Add glitch free PLL setting support to si5351 clk driver - Add DSI clocks on Amlogic g12/sm1 - Add CSI and ISP clocks on Amlogic g12/sm1 - Document bindings for i.MX93 ANATOP clock driver - Free clk_node in i.MX SCU driver for resource with different owner - Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15 - Fix the name of the fvco in i.MX pll14xx by renaming it to fout - Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC - Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S - Check reset monitor registers on Renesas RZ/G2L-alike SoCs - Reuse reset functionality in the Renesas RZ/G2L clock driver - Global and RPMh clock support for the Qualcomm X1E80100 SoC - Support for the Stromer APCS PLL found in Qualcomm IPQ5018 - Add a new type of branch clock, with support for controlling separate memory control bits, to the Qualcomm clk driver - Use above new branch type in Qualcomm ECPRI clk driver for QDU1000 and QRU1000 - Add a number of missing clocks related to CSI2 on Qualcomm MSM8939 - Add support for the camera clock controller on Qualcomm SC8280XP - Correct PLL configuration in GPU and video clock controllers for Qualcomm SM8150 - Add runtime PM support and a few missing resets to Qualcomm SM8150 video clock controller - Fix configuration of various GCC GDSCs on Qualcomm SM8550 - Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver - Fix up GPU and display clock controllers PLL configuration settings on Qualcomm SM8550 - Cleanup variable init in Allwinner nkm module - Convert various DT bindings to YAML - A few kernel-doc fixes for Samsung SoC clock controllers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits) clk: mediatek: add drivers for MT7988 SoC clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 dt-bindings: clock: mediatek: add clock controllers of MT7988 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs dt-bindings: clock: mediatek: add MT7988 clock IDs clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: clk-mux: Support custom parent indices for muxes dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx clk: starfive: Add flags argument to JH71X0__MUX macro clk: imx: pll14xx: change naming of fvco to fout clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu() clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings ...
2024-01-11Merge tag 'soc-drivers-6.8' of ↵Linus Torvalds4-0/+2528
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "A new drivers/cache/ subsystem is added to contain drivers for abstracting cache flush methods on riscv and potentially others, as this is needed for handling non-coherent DMA but several SoCs require nonstandard hardware methods for it. op-tee gains support for asynchronous notification with FF-A, as well as support for a system thread for executing in secure world. The tee, reset, bus, memory and scmi subsystems have a couple of minor updates. Platform specific soc driver changes include: - Samsung Exynos gains driver support for Google GS101 (Tensor G1) across multiple subsystems - Qualcomm Snapdragon gains support for SM8650 and X1E along with added features for some other SoCs - Mediatek adds support for "Smart Voltage Scaling" on MT8186 and MT8195, and driver support for MT8188 along with some code refactoring. - Microchip Polarfire FPGA support for "Auto Update" of the FPGA bitstream - Apple M1 mailbox driver is rewritten into a SoC driver - minor updates on amlogic, mvebu, ti, zynq, imx, renesas and hisilicon" * tag 'soc-drivers-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (189 commits) memory: ti-emif-pm: Convert to platform remove callback returning void memory: ti-aemif: Convert to platform remove callback returning void memory: tegra210-emc: Convert to platform remove callback returning void memory: tegra186-emc: Convert to platform remove callback returning void memory: stm32-fmc2-ebi: Convert to platform remove callback returning void memory: exynos5422-dmc: Convert to platform remove callback returning void memory: renesas-rpc-if: Convert to platform remove callback returning void memory: omap-gpmc: Convert to platform remove callback returning void memory: mtk-smi: Convert to platform remove callback returning void memory: jz4780-nemc: Convert to platform remove callback returning void memory: fsl_ifc: Convert to platform remove callback returning void memory: fsl-corenet-cf: Convert to platform remove callback returning void memory: emif: Convert to platform remove callback returning void memory: brcmstb_memc: Convert to platform remove callback returning void memory: brcmstb_dpfe: Convert to platform remove callback returning void soc: qcom: llcc: Fix LLCC_TRP_ATTR2_CFGn offset firmware: qcom: qseecom: fix memory leaks in error paths dt-bindings: clock: google,gs101: rename CMU_TOP gate defines soc: qcom: llcc: Fix typo in kernel-doc dt-bindings: soc: qcom,aoss-qmp: document the X1E80100 Always-On Subsystem side channel ...
2024-01-09Merge branch 'clk-rs9' into clk-nextStephen Boyd1-17/+20
* clk-rs9: clk: rs9: Add support for 9FGV0841 clk: rs9: Replace model check with bitshift from chip data clk: rs9: Limit check to vendor ID in VID register dt-bindings: clk: rs9: Add 9FGV0841
2024-01-09Merge branches 'clk-zynq', 'clk-xilinx' and 'clk-stm' into clk-nextStephen Boyd13-292/+614
- Update Zynqmp driver for Versal NET platforms - Add clk driver for Versal clocking wizard IP * clk-zynq: drivers: clk: zynqmp: update divider round rate logic drivers: clk: zynqmp: calculate closest mux rate * clk-xilinx: clocking-wizard: Add support for versal clocking wizard dt-bindings: clock: xilinx: add versal compatible * clk-stm: dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform clk: stm32mp1: use stm32mp13 reset driver clk: stm32mp1: move stm32mp1 clock driver into stm32 directory
2024-01-09Merge branches 'clk-imx', 'clk-qcom', 'clk-amlogic' and 'clk-mediatek' into ↵Stephen Boyd37-106/+20433
clk-next * clk-imx: clk: imx: pll14xx: change naming of fvco to fout clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu() dt-bindings: clock: support i.MX93 ANATOP clock module * clk-qcom: (41 commits) clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings clk: qcom: gcc-sm8550: Mark RCGs shared where applicable clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag clk: qcom: camcc-sc8280xp: Prevent error pointer dereference clk: qcom: videocc-sm8150: Add runtime PM support clk: qcom: videocc-sm8150: Add missing PLL config property clk: qcom: videocc-sm8150: Update the videocc resets dt-bindings: clock: Update the videocc resets for sm8150 clk: qcom: rpmh: Add support for X1E80100 rpmh clocks clk: qcom: Add Global Clock controller (GCC) driver for X1E80100 dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for X1E80100 dt-bindings: clock: qcom: Add X1E80100 GCC clocks clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000 clk: qcom: branch: Add mem ops support for branch2 clocks ... * clk-amlogic: clk: meson: g12a: add CSI & ISP gates clocks clk: meson: g12a: add MIPI ISP clocks dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids * clk-mediatek: clk: mediatek: add drivers for MT7988 SoC clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 dt-bindings: clock: mediatek: add clock controllers of MT7988 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs dt-bindings: clock: mediatek: add MT7988 clock IDs clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: clk-mux: Support custom parent indices for muxes dt-bindings: clock: brcm,kona-ccu: convert to YAML dt-bindings: arm: mediatek: move ethsys controller & convert to DT schema dt-bindings: Remove alt_ref from versal
2024-01-09Merge branches 'clk-versa', 'clk-silabs', 'clk-samsung', 'clk-starfive' and ↵Stephen Boyd10-173/+221
'clk-sophgo' into clk-next - Add glitch free PLL setting support to si5351 clk driver * clk-versa: clk: versaclock3: Drop ret variable clk: versaclock3: Add missing space between ')' and '{' clk: versaclock3: Use u8 return type for get_parent() callback clk: versaclock3: Avoid unnecessary padding clk: versaclock3: Update vc3_get_div() to avoid divide by zero * clk-silabs: clk: si5351: allow PLLs to be adjusted without reset dt-bindings: clock: si5351: add PLL reset mode property dt-bindings: clock: si5351: convert to yaml * clk-samsung: clk: samsung: Improve kernel-doc comments clk: samsung: Fix kernel-doc comments * clk-starfive: clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx clk: starfive: Add flags argument to JH71X0__MUX macro * clk-sophgo: dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC
2024-01-09Merge branches 'clk-renesas', 'clk-rockchip', 'clk-allwinner' and ↵Stephen Boyd8-15/+20
'clk-cleanup' into clk-next * clk-renesas: clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1 clk: renesas: rzg2l: Check reset monitor registers clk: renesas: r9a08g045: Add IA55 pclk and its reset clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset() clk: renesas: r8a779g0: Add PCIe clocks clk: renesas: r8a779g0: Add EtherTSN clock * clk-rockchip: clk: rockchip: rk3568: Mark pclk_usb as critical clk: rockchip: rk3568: Add PLL rate for 126.4MHz clk: rockchip: rk3568: Add PLL rate for 115.2MHz * clk-allwinner: clk: sunxi-ng: nkm: remove redundant initialization of tmp_parent * clk-cleanup: clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw clk: si5341: fix an error code problem in si5341_output_clk_set_rate clk: microchip: mpfs-ccc: replace include of asm-generic/errno-base.h clk: rs9: Fix DIF OEn bit placement on 9FGV0241 clk: mmp: pxa168: Fix memory leak in pxa168_clk_init() clk: hi3620: Fix memory leak in hi3620_mmc_clk_init() clk: sp7021: fix return value check in sp7021_clk_probe()
2024-01-03clk: mediatek: add drivers for MT7988 SoCSam Shih7-0/+960
Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are typical MediaTek designs. Also add driver for XFIPLL clock generating the 156.25MHz clock for the XFI SerDes. It needs an undocumented software workaround and has an unknown internal design. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org [sboyd@kernel.org: Add module license to infracfg file] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03clk: mediatek: add pcw_chg_bit control for PLLs of MT7988Sam Shih2-2/+4
Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead of the previously hardcoded PCW_CHG_MASK macro if set. This will needed for clocks on the MT7988 SoC. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxesAngeloGioacchino Del Regno1-13/+14
The top_dp and top_edp muxes can be both parented to either TVDPLL1 or TVDPLL2, two identically specced PLLs for the specific purpose of giving out pixel clock: this becomes a problem when the MediaTek DisplayPort Interface (DPI) driver tries to set the pixel clock rate. In the usecase of two simultaneous outputs (using two controllers), it was seen that one of the displays would sometimes display garbled output (if any at all) and this was because: - top_edp was set to TVDPLL1, outputting X GHz - top_dp was set to TVDPLL2, outputting Y GHz - mtk_dpi calls clk_set_rate(top_edp, Z GHz) - top_dp is switched to TVDPLL1 - TVDPLL1 changes its rate, top_edp outputs the wrong rate. - eDP display is garbled To solve this issue, remove all TVDPLL1 parents from `top_dp` and all TVDPLL2 parents from `top_edp`, plus, necessarily switch both clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be able to use the right bit index for the new parents list. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20231103102533.69280-4-angelogioacchino.delregno@collabora.com Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Fei Shao <fshao@chromium.org> Reviewed-by: Fei Shao <fshao@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxesAngeloGioacchino Del Regno1-8/+19
The top_dp and top_edp muxes can be both parented to either TVDPLL1 or TVDPLL2, two identically specced PLLs for the specific purpose of giving out pixel clock: this becomes a problem when the MediaTek DisplayPort Interface (DPI) driver tries to set the pixel clock rate. In the usecase of two simultaneous outputs (using two controllers), it was seen that one of the displays would sometimes display garbled output (if any at all) and this was because: - top_edp was set to TVDPLL1, outputting X GHz - top_dp was set to TVDPLL2, outputting Y GHz - mtk_dpi calls clk_set_rate(top_edp, Z GHz) - top_dp is switched to TVDPLL1 - TVDPLL1 changes its rate, top_edp outputs the wrong rate. - eDP display is garbled To solve this issue, remove all TVDPLL1 parents from `top_dp` and all TVDPLL2 parents from `top_edp`, plus, necessarily switch both clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be able to use the right bit index for the new parents list. Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20231103102533.69280-3-angelogioacchino.delregno@collabora.com Reviewed-by: Fei Shao <fshao@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03clk: mediatek: clk-mux: Support custom parent indices for muxesAngeloGioacchino Del Regno2-4/+53
Add support for customized parent indices for MediaTek muxes: this is necessary for the case in which we want to exclude some clocks from a mux's parent clocks list, where the exclusions are not from the very bottom of the list but either in the middle or the beginning. Example: - MUX1 (all parents) - parent1; idx=0 - parent2; idx=1 - parent3; idx=2 - MUX1 (wanted parents) - parent1; idx=0 - parent3; idx=2 To achieve that add a `parent_index` array pointer to struct mtk_mux, then in .set_parent(), .get_parent() callbacks check if this array was populated and eventually get the index from that. Also, to avoid updating all clock drivers for all SoCs, rename the "main" macro to __GATE_CLR_SET_UPD_FLAGS (so, `__` was added) and add the new member to it; furthermore, GATE_CLK_SET_UPD_FLAGS has been reintroduced as being fully compatible with the older version. The new parent_index can be specified with the new `_INDEXED` variants of the MUX_GATE_CLR_SET_UPD_xxxx macros. Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20231103102533.69280-2-angelogioacchino.delregno@collabora.com Tested-by: Fei Shao <fshao@chromium.org> Reviewed-by: Fei Shao <fshao@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_txEmil Renner Berthing1-1/+1
This is needed by the dwmac-starfive ethernet driver to set the clock for 1000, 100 and 10 Mbps links properly. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Link: https://lore.kernel.org/r/20231219232442.2460166-3-cristian.ciocaltea@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 08:28:15 +0000