drm-tip - DRM current development and nightly trees

Age	Commit message (Expand)	Author	Files	Lines
2022-05-06	clk: renesas: Add RZ/V2M support using the rzg2l driver	Phil Edworthy	1	-0/+1
2022-05-05	clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg	Phil Edworthy	1	-2/+8
2022-05-05	clk: renesas: rzg2l: Make use of CLK_MON registers optional	Phil Edworthy	1	-0/+3
2022-05-05	clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers	Phil Edworthy	1	-4/+5
2022-05-05	clk: renesas: rzg2l: Add read only versions of the clk macros	Phil Edworthy	1	-0/+9
2022-05-05	clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro	Phil Edworthy	1	-7/+9
2022-05-05	clk: renesas: rzg2l: Add DSI divider clk support	Biju Das	1	-0/+11
2022-05-05	clk: renesas: rzg2l: Add PLL5_4 clk mux support	Biju Das	1	-0/+10
2022-05-05	clk: renesas: rzg2l: Add FOUTPOSTDIV clk support	Biju Das	1	-0/+23
2022-04-13	clk: renesas: Add support for RZ/G2UL SoC	Biju Das	1	-0/+1
2022-02-10	clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC	Biju Das	1	-0/+1
2021-12-08	clk: renesas: r9a07g044: Add mux and divider for G clock	Biju Das	1	-0/+4
2021-11-19	clk: renesas: rzg2l: Add CPG_PL1_DDIV macro	Biju Das	1	-0/+2
2021-11-15	clk: renesas: rzg2l: Add missing kerneldoc for resets	Geert Uytterhoeven	1	-0/+3
2021-10-08	clk: renesas: r9a07g044: Add SDHI clock and reset entries	Biju Das	1	-0/+4
2021-10-08	clk: renesas: rzg2l: Add SDHI clk mux support	Biju Das	1	-0/+12
2021-10-08	clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...	Lad Prabhakar	1	-0/+3
2021-09-24	clk: renesas: rzg2l: Add support to handle coupled clocks	Biju Das	1	-1/+10
2021-09-24	clk: renesas: r9a07g044: Add ethernet clock sources	Biju Das	1	-0/+3
2021-09-24	clk: renesas: rzg2l: Add support to handle MUX clocks	Biju Das	1	-0/+12
2021-07-19	clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]	Geert Uytterhoeven	1	-0/+155