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2020-10-13clk: pxa: Constify static struct clk_opsRikard Falkeborn1-4/+4
Constify a couple of static struct clk_ops that are not modified. Their only usage is inside the macros and their address is passed to clk_register_composite() which takes pointers to const struct clk_ops. This allows the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200922184715.1854-1-rikard.falkeborn@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-13clk: pxa: fix one of the pxa RTC clocksRobert Jarzmik1-0/+1
The pxa27x platforms have a single IP with 2 drivers, sa1100-rtc and rtc-pxa drivers. A previous patch fixed the sa1100-rtc case, but the pxa-rtc wasn't fixed. This patch completes the previous one. Fixes: 8b6d10345e16 ("clk: pxa: add missing pxa27x clocks for Irda and sa1100-rtc") Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Link: https://lkml.kernel.org/r/20191026194420.11918-1-robert.jarzmik@free.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 441Thomas Gleixner5-23/+5
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation version 2 of the license extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 315 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Armijn Hemel <armijn@tjaldur.nl> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190115.503150771@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd1-0/+1
Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-11-06clk: pxa: constify clk_ops structuresJulia Lawall1-2/+2
These clk_ops structures are only passed to a call to clk_register_composite where the corresponding parameters are const, so the clk_ops structure can be const as well. Identified and transformed using Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: pxa: export 32kHz PLLRobert Jarzmik3-8/+12
This clock is especially used by the RTC driver, so export it so that devicetree users can use it. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2017-12-28clk: pxa: unbreak lookup of CLK_POUTIgor Grinberg1-1/+5
Since switching to clk drivers, the CLK_POUT cannot be searched for by clk_get() API and thus it returns with ENOENT. Register it with the clk_lookup and thus unbreak the users of it. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-11-14clk: pxa: fix building on older compilersArnd Bergmann1-3/+1
gcc-4.4 got confused by the inline assembler statement: drivers/clk/pxa/clk-pxa.c: In function 'pxa2xx_core_turbo_switch': drivers/clk/pxa/clk-pxa.c:152: error: expected string literal before ')' token This removes the extraneous ':' to let all compilers parse the driver correctly. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-15Merge tag 'armsoc-soc' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Arnd Bergmann: "These are updates for platform specific code on 32-bit ARM machines, essentially anything that can not (yet) be expressed using DT files. Noteworthy changes include: - Added support for the TI DRA71x family of SoCs in mach-omap2, this is an new variant of the the DRA72x/DRA74x automotive infotainment chips we already supported for a while. - Added support for the ST STM32F746 SoC, the first Cortex-M7 based microcontroller we support, related to the smaller STM32F4 family. - Renesas adds support for r8a7743 and r8a7745 in mach-shmobile, see http://elinux.org/RZ-G - SMP is now supported on the OX820 platform - A lot of code in mach-omap2 gets removed as a follow-up to removing support for board files in the previous release - Davinci has some new work to improve USB support - For i.MX, the performance monitor now supports profiling the memory controller using 'perf'" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (95 commits) ARM: davinci: da830-evm: use gpio descriptor for mmc pins ARM: davinci: da850-evm: use gpio descriptor for mmc pins ARM: davinci: hawk: use gpio descriptor for mmc pins ARM: ARTPEC-6: add select MFD_SYSCON to MACH_ARTPEC6 ARM: davinci: da8xx: Fix ohci device name ARM: oxnas: Add OX820 config and makefile entry ARM: oxnas: Add OX820 SMP support ARM: davinci: PM: fix build when da850 not compiled in ARM: orion5x: remove legacy support of ls-chl ARM: integrator: drop EBI access use syscon ARM: BCM5301X: Add back handler ignoring external imprecise aborts ARM: davinci: PM: support da8xx DT platforms ARM: davinci: PM: cleanup: remove references to pdata ARM: davinci: PM: rework init, remove platform device ARM: Kconfig: Introduce MACH_STM32F746 flag ARM: mach-stm32: Add a new SOC - STM32F746 ARM: shmobile: document SK-RZG1E board ARM: shmobile: r8a7745: basic SoC support ARM: imx: mach-imx6ul: add imx6ull support ARM: zynq: Reserve correct amount of non-DMA RAM ...
2016-11-09clk: pxa: Use __iomem properly and staticize lock variableStephen Boyd2-5/+6
This function is passed an __iomem pointer but we use a u32 pointer instead which makes checkers like spare complain. Furthermore, "lock" is a pretty poor variable name for a string that will go into lockdep reports and the symbol isn't marked static. Cleanup all this. Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-09clk: pxa: fix pxa2xx_determine_rate returnArnd Bergmann1-11/+12
The new pxa2xx_determine_rate() function seems lacking in a few regards: - For an exact match or no match at all, the rate is uninitialized as reported by gcc -Wmaybe-unintialized: drivers/clk/pxa/clk-pxa.c: In function 'pxa2xx_determine_rate': drivers/clk/pxa/clk-pxa.c:243:5: error: 'rate' may be used uninitialized in this function - If we get a non-exact match, the req->rate output is never set to the actual rate but remains at the requested rate. - We should not attempt to print a rate if none could be found This rewrites the logic accordingly. Fixes: 9fe694295098 ("clk: pxa: transfer CPU clock setting from pxa2xx-cpufreq") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-08clk: pxa mark dummy helper as 'inline'Arnd Bergmann1-1/+1
The dummy_clk_set_parent function is marked as 'static' but is no longer referenced from the pxa25x clk driver after the last use of the RATE_RO_OPS() macro is gone from this file, causing a harmless build warning: In file included from drivers/clk/pxa/clk-pxa25x.c:24:0: drivers/clk/pxa/clk-pxa.h:146:12: error: 'dummy_clk_set_parent' defined but not used [-Werror=unused-function] This marks the functon as 'inline', which lets the compiler simply drop it when it gets referenced. Fixes: 9fe694295098 ("clk: pxa: transfer CPU clock setting from pxa2xx-cpufreq") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-04clk: pxa: transfer CPU clock setting from pxa2xx-cpufreqRobert Jarzmik4-27/+414
This is the initial stage to transfer the pxa25x and pxa27x CPU clocks handling from cpufreq to the clock API. More precisely, the clocks transferred are : - cpll : core pll, known also as the CPU core turbo frequency - core : core, known also as the CPU actual frequency, being either the CPU core turbo frequency or the CPU core run frequency This transfer is a prequel to shrink the code in pxa2xx-cpufreq.c, so that it can become, at least in devicetree builds, the casual cpufreq-dt driver. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: pxa: export core clocksRobert Jarzmik2-8/+14
pxaxxx_get_clk_frequency_khz() needs several clocks to be available through clk_get(), ie. the cpu clocks, system bus clock and memory clocks. Add the missing clkdev so that their rate can be acquired. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: pxa: b bit of clkcfg means fast busRobert Jarzmik1-2/+2
The meaning of this bit was inverted : - when set to 0, system bus clock is half of the CPU run clock - when set to 1, system bus clock is the CPU run clock Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: pxa: core pll is not affected by t bitRobert Jarzmik2-4/+2
The t bit of clkfcfg doesn't affect the core pll clock, but it makes core clock select between core pll clock and core run clock. As such remove it from the core pll rate reporting function, while it remains in clk_pxa27x_core_get_parent(). Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: pxa: remove unused variablesRobert Jarzmik1-5/+2
This is a cleanup patch to remove unused values not used in their respective functions. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-18clk: pxa25x: OSTIMER0 clocks from the main oscillatorRussell King - ARM Linux1-1/+1
The OSTIMER0 clock ticks at the main oscillator rate, not the 32kHz oscillator rate. Ensure that it is parented to the main oscillator. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2016-03-23Merge tag 'clk-for-linus' of ↵Linus Torvalds3-12/+10
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The clk changes for this release cycle are mostly dominated by new device support in terms of LoC, but there has been some cleanup in the core as well as the usual minor clk additions to various drivers. Core: - parent tracking has been simplified - CLK_IS_ROOT is now a no-op flag, cleaning up drivers has started - of_clk_init() doesn't consider disabled DT nodes anymore - clk_unregister() had an error path bug squashed - of_clk_get_parent_count() has been fixed to only return unsigned ints - HAVE_MACH_CLKDEV is removed now that the last arch user (ARM) is gone New Drivers: - NXP LPC18xx creg - QCOM IPQ4019 GCC - TI dm814x ADPLL - i.MX6QP Updates: - Cyngus audio clks found on Broadcom iProc devices - Non-critical fixes for BCM2385 PLLs - Samsung exynos5433 updates for clk id errors, HDMI support, suspend/resume simplifications - USB, CAN, LVDS, and FCP clks on shmobile devices - sunxi got support for more clks on new SoCs and went through a minor refactoring/rewrite to use a simpler factor clk construct - rockchip added some more clk ids and added suport for fraction dividers - QCOM GDSCs in msm8996 - A new devm helper to make adding custom actions simpler (acked by Greg)" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (197 commits) clk: bcm2835: fix check of error code returned by devm_ioremap_resource() clk: renesas: div6: use RENESAS for #define clk: renesas: Rename header file renesas.h clk: max77{686,802}: Remove CLK_IS_ROOT clk: versatile: Remove CLK_IS_ROOT clk: sunxi: Remove use of variable length array clk: fixed-rate: Remove CLK_IS_ROOT clk: qcom: Remove CLK_IS_ROOT doc: dt: add documentation for lpc1850-creg-clk driver clk: add lpc18xx creg clk driver clk: lpc32xx: fix compilation warning clk: xgene: Add missing parenthesis when clearing divider value clk: mb86s7x: Remove CLK_IS_ROOT clk: x86: Remove clkdev.h and clk.h includes clk: x86: Remove CLK_IS_ROOT clk: mvebu: Remove CLK_IS_ROOT clk: renesas: move drivers to renesas directory clk: si5{14,351,70}: Remove CLK_IS_ROOT clk: scpi: Remove CLK_IS_ROOT clk: s2mps11: Remove CLK_IS_ROOT ...
2016-03-02clk: pxa: Remove CLK_IS_ROOTStephen Boyd3-12/+10
This flag is a no-op now. Remove usage of the flag. Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01ARM: pxa: define clock registers as __iomemArnd Bergmann3-25/+24
We should not dereference registers as pointers, so use readl/writel instead for these registers. The clock registers are accessed in multiple files, so we have to change them all at once. I stumbled over these registers while looking at something unrelated. There are in fact other registers with the same problem, but I did not try to address those at this point. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2015-12-01ARM: pxa: make more mach/*.h files localArnd Bergmann1-1/+0
Lots of header files are never included outside of a mach-pxa directory and do not need to be made visible in include/mach, so let's just move them all down one level. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-08-31Merge tag 'clk-for-linus-4.3' of ↵Linus Torvalds3-3/+3
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Michael Turquette: "The clk framework changes for 4.3 are mostly updates to existing drivers and the addition of new clock drivers. Stephen Boyd has also done a lot of subsystem-wide driver clean-ups (thanks!). There are also fixes to the framework core and changes to better split clock provider drivers from clock consumer drivers" * tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits) clk: s5pv210: add missing call to samsung_clk_of_add_provider() clk: pistachio: correct critical clock list clk: pistachio: Fix PLL rate calculation in integer mode clk: pistachio: Fix override of clk-pll settings from boot loader clk: pistachio: Fix 32bit integer overflows clk: tegra: Fix some static checker problems clk: qcom: Fix MSM8916 prng clock enable bit clk: Add missing header for 'bool' definition to clk-conf.h drivers/clk: appropriate __init annotation for const data clk: rockchip: register pll mux before pll itself clk: add bindings for the Ux500 clocks clk/ARM: move Ux500 PRCC bases to the device tree clk: remove duplicated code with __clk_set_parent_after clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw) clk: Constify clk_hw argument to provider APIs clk: Hi6220: add stub clock driver dt-bindings: clk: Hi6220: Document stub clock driver dt-bindings: arm: Hi6220: add doc for SRAM controller clk: atlas7: fix pll missed divide NR in fraction mode clk: atlas7: fix bit field and its root clk for coresight_tpiu ...
2015-08-07clk: pxa: pxa3xx: fix CKEN register accessRobert Jarzmik1-1/+1
Clocks 0 to 31 are on CKENA, and not CKENB. The clock register names were inadequately inverted. As a consequence, all clock operations were happening on CKENB, because almost all but 2 clocks are on CKENA. As the clocks were activated by the bootloader in the former tests, it escaped the testing that the wrong clock gate was manipulated. The error was revealed by changing the pxa3xx-nand driver to a module, where upon unloading, the wrong clock was disabled in CKENB. Fixes: 9bbb8a338fb2 ("clk: pxa: add pxa3xx clock driver") Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28clk: pxa: fix core frequency reporting unitRobert Jarzmik3-3/+3
Legacy drivers which are not yet ported, such as cpufreq-pxa[23]xx, rely on pxaXXx_get_clk_frequency_khz() to find the CPU core frequency. This reporting was broken because the expected unit is kHz and not Hz. Fix the reporting for pxa25x, pxa27x and pxa3xx. Fixes: fe7710fae477 ("clk: add pxa25x clock drivers") Fixes: d40670dc6169 ("clk: add pxa27x clock drivers") Fixes: 9bbb8a338fb2 ("clk: pxa: add pxa3xx clock driver") Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-01Merge tag 'clk-for-linus-4.2' of ↵Linus Torvalds1-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clock framework updates from Michael Turquette: "The changes to the common clock framework for 4.2 are dominated by new drivers and updates to existing ones, as usual. There are some fixes to the framework itself and several cleanups for sparse warnings, etc" * tag 'clk-for-linus-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits) clk: stm32: Add clock driver for STM32F4[23]xxx devices dt-bindings: Document the STM32F4 clock bindings cpufreq: exynos: remove Exynos4210 specific cpufreq driver support ARM: Exynos: switch to using generic cpufreq driver for Exynos4210 clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock clk: samsung: add infrastructure to register cpu clocks clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock support doc: dt: add documentation for lpc1850-ccu clk driver clk: add lpc18xx ccu clk driver doc: dt: add documentation for lpc1850-cgu clk driver clk: add lpc18xx cgu clk driver clk: keystone: add support for post divider register for main pll clk: mvebu: flag the crypto clk as CLK_IGNORE_UNUSED clk: cygnus: remove Cygnus dummy clock binding clk: cygnus: add clock support for Broadcom Cygnus clk: Change bcm clocks build dependency clk: iproc: add initial common clock support clk: iproc: define Broadcom iProc clock binding MAINTAINERS: update email for Michael Turquette clk: meson: add some error handling in meson_clk_register_cpu() ...
2015-06-12clk: pxa: Fix const discarding warningStephen Boyd1-1/+1
A recent change to mark parent names as const missed this struct member so we get warnings like: drivers/clk/pxa/clk-pxa25x.c:122:2: warning: initialization discards 'const' qualifier from pointer target type Fix it. Reported-by: kbuild test robot <fengguang.wu@intel.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-04clk: make several parent names constUwe Kleine-König1-1/+1
Since commit 2893c379461a ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-12clk: pxa: add missing pxa27x clocks for Irda and sa1100-rtcRobert Jarzmik1-0/+29
Add 2 clocks which were erronously forgotten by the clock framework port, namely : - sa1100-rtc - irda for pxa2xx-ir:UARTCLK Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Michael Turquette <mturquette@linaro.org>
2015-05-12ARM: pxa: change clocks init sequenceRobert Jarzmik1-2/+1
Since pxa clocks were ported to the clock framework, an ordering issue appears between clocks and clocksource initialization. As a consequence, the pxa timer clock cannot be acquired in pxa_timer, and is disabled by clock framework because it is "unused". The ordering issue is that in the kernel boot sequence : start_kernel() ... time_init() -> pxa_timer() -> here the clocksource is initialized ... rest_init() kernel_init() initcalls -> here the clocks are initialized In the current sequence, the clocks are initialized way after pxa_timer, which cannot acquire the OSTIMER0 clock. To solve this issue, the clocks initialization is moved to pxa_timer(), so that clocks are initialized before clocksource for non device-tree. For device-tree, the standard arm time_init() will take care of the ordering. Reviewed-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2015-04-12clk: don't use __initconst for non-const arraysUwe Kleine-König1-1/+1
The statement static const char *name[]; defines a modifiable array of pointers to constant chars. That is *name[0] = 'f'; is forbidden, but name[0] = "f"; is not. So marking an array that is defined as above with __initconst is wrong. Either an additional const must be added such that the whole definition reads: static const char *const name[] __initconst; or where this is not possible __initdata must be used. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-04-10clk: pxa: pxa3xx: add missing os timer clockRobert Jarzmik1-0/+3
The pxa3xx scheduler relies on the pxa-timer, which requires a clock for its rate. As the clock handling will be taken over by the clock framework, add this missing clock. The miss was discovered by attempting to run a zylonite platform in a device-tree configuration, with the future patch to shift clocks handling to clock framework applied. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-18clk: Replace explicit clk assignment with __clk_hw_set_clkJavier Martinez Canillas1-1/+1
The change in the clk API to return a per-user clock instance, moved the clock state to struct clk_core so now the struct clk_hw .core field is used instead of .clk for most operations. So for hardware clocks that needs to share the same clock state, both the .core and .clk pointers have to be assigned but currently only the .clk is set. This leads to NULL pointer dereference when the operations try to access the hw clock .core. For example, the composite clock rate and mux components didn't have a .core set which leads to this error: Unable to handle kernel NULL pointer dereference at virtual address 00000034 pgd = c0004000 [00000034] *pgd=00000000 Internal error: Oops: 5 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.19.0-next-20150211-00002-g1fb7f0e1150d #423 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) task: ee480000 ti: ee488000 task.ti: ee488000 PC is at clk_mux_determine_rate_flags+0x14/0x19c LR is at __clk_mux_determine_rate+0x24/0x2c pc : [<c03a355c>] lr : [<c03a3734>] psr: a0000113 sp : ee489ce8 ip : ee489d84 fp : ee489d84 r10: 0000005c r9 : 00000001 r8 : 016e3600 r7 : 00000000 r6 : 00000000 r5 : ee442200 r4 : ee440c98 r3 : ffffffff r2 : 00000000 r1 : 016e3600 r0 : ee440c98 Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c5387d Table: 4000406a DAC: 00000015 Process swapper/0 (pid: 1, stack limit = 0xee488210) Stack: (0xee489ce8 to 0xee48a000) 9ce0: 00000000 ffffffff 60000113 ee440c98 ee442200 00000000 9d00: 016e3600 ffffffff 00000001 0000005c ee489d84 c03a3734 ee489d80 ee489d84 9d20: 00000000 c048b130 00000400 c03a5798 ee489d80 ee489d84 c0607f60 ffffffea 9d40: 00000001 00000001 ee489d5c c003f844 c06e3340 ee402680 ee440d0c ed935000 9d60: 016e3600 00000003 00000001 0000005c eded3700 c03a11a0 ee489d80 ee489d84 9d80: 016e3600 ee402680 c05b413a eddc9900 016e3600 c03a1228 00000000 ffffffff 9da0: ffffffff eddc9900 016e3600 c03a1c1c ffffffff 016e3600 ed8c6710 c03d6ce4 9dc0: eded3400 00000000 00000000 c03c797c 00000001 0000005c eded3700 eded3700 9de0: 000005e0 00000001 0000005c c03db8ac c06e7e54 c03c8f08 00000000 c06e7e64 9e00: c06b6e74 c06e7f64 000005e0 c06e7df8 c06e5100 00000000 c06e7e6c c06e7f54 9e20: 00000000 00000000 eebd9550 00000000 c06e7da0 c06e7e54 ee7b5010 c06e7da0 9e40: eddc9690 c06e7db4 c06b6e74 00000097 00000000 c03d4398 00000000 ee7b5010 9e60: eebd9550 c06e7da0 00000000 c03db824 ee7b5010 fffffffe c06e7db4 c0299c7c 9e80: ee7b5010 c072a05c 00000000 c0298858 ee7b5010 c06e7db4 ee7b5044 00000000 9ea0: eddc9580 c0298a04 c06e7db4 00000000 c0298978 c02971d4 ee405c78 ee732b40 9ec0: c06e7db4 eded3800 c06d6738 c0298044 c0608300 c06e7db4 00000000 c06e7db4 9ee0: 00000000 c06beb58 c06beb58 c0299024 00000000 c068dd00 00000000 c0008944 9f00: 00000038 c049013c ee462200 c0711920 ee480000 60000113 c06c2cb0 00000000 9f20: 00000000 c06c2cb0 60000113 00000000 ef7fcafc 00000000 c0640194 c00389ec 9f40: c05ec3a8 c063f824 00000006 00000006 c06c2c50 c0696444 00000006 c0696424 9f60: c06ee1c0 c066b588 c06b6e74 00000097 00000000 c066bd44 00000006 00000006 9f80: c066b588 c003d684 00000000 c0481938 00000000 00000000 00000000 00000000 9fa0: 00000000 c0481940 00000000 c000e680 00000000 00000000 00000000 00000000 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000 [<c03a355c>] (clk_mux_determine_rate_flags) from [<c03a3734>] (__clk_mux_determine_rate+0x24/0x2c) [<c03a3734>] (__clk_mux_determine_rate) from [<c03a5798>] (clk_composite_determine_rate+0xbc/0x238) [<c03a5798>] (clk_composite_determine_rate) from [<c03a11a0>] (clk_core_round_rate_nolock+0x5c/0x9c) [<c03a11a0>] (clk_core_round_rate_nolock) from [<c03a1228>] (__clk_round_rate+0x38/0x40) [<c03a1228>] (__clk_round_rate) from [<c03a1c1c>] (clk_round_rate+0x20/0x38) [<c03a1c1c>] (clk_round_rate) from [<c03d6ce4>] (max98090_dai_set_sysclk+0x34/0x118) [<c03d6ce4>] (max98090_dai_set_sysclk) from [<c03c797c>] (snd_soc_dai_set_sysclk+0x38/0x80) [<c03c797c>] (snd_soc_dai_set_sysclk) from [<c03db8ac>] (snow_late_probe+0x24/0x48) [<c03db8ac>] (snow_late_probe) from [<c03c8f08>] (snd_soc_register_card+0xf04/0x1070) [<c03c8f08>] (snd_soc_register_card) from [<c03d4398>] (devm_snd_soc_register_card+0x30/0x64) [<c03d4398>] (devm_snd_soc_register_card) from [<c03db824>] (snow_probe+0x68/0xcc) [<c03db824>] (snow_probe) from [<c0299c7c>] (platform_drv_probe+0x48/0x98) [<c0299c7c>] (platform_drv_probe) from [<c0298858>] (driver_probe_device+0x114/0x234) [<c0298858>] (driver_probe_device) from [<c0298a04>] (__driver_attach+0x8c/0x90) [<c0298a04>] (__driver_attach) from [<c02971d4>] (bus_for_each_dev+0x54/0x88) [<c02971d4>] (bus_for_each_dev) from [<c0298044>] (bus_add_driver+0xd8/0x1cc) [<c0298044>] (bus_add_driver) from [<c0299024>] (driver_register+0x78/0xf4) [<c0299024>] (driver_register) from [<c0008944>] (do_one_initcall+0x80/0x1d0) [<c0008944>] (do_one_initcall) from [<c066bd44>] (kernel_init_freeable+0x10c/0x1d8) [<c066bd44>] (kernel_init_freeable) from [<c0481940>] (kernel_init+0x8/0xe4) [<c0481940>] (kernel_init) from [<c000e680>] (ret_from_fork+0x14/0x34) Code: e24dd00c e5907000 e1a08001 e88d000c (e5970034) The changes were made using the following cocinelle semantic patch: @i@ @@ @depends on i@ identifier dst; @@ - dst->clk = hw->clk; + __clk_hw_set_clk(dst, hw); @depends on i@ identifier dst; @@ - dst->hw.clk = hw->clk; + __clk_hw_set_clk(&dst->hw, hw); Fixes: 035a61c314eb3 ("clk: Make clk API return per-user struct clk instances") Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27clk: pxa: add pxa3xx clock driverRobert Jarzmik2-0/+365
Move pxa25x clock drivers from arch/arm/mach-pxa to driver/clk. In the move : - convert to new clock framework legacy clocks - provide clocks as before for platform data based boards - provide clocks through devicetree with clk-pxa-dt Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-24Merge branch 'clk-fixes' into clk-nextMichael Turquette1-2/+2
2014-11-17clk: pxa: keep clocks initialization separated per variantRobert Jarzmik3-2/+9
Have each pxa variant (pxa25x, pxa27x, pxa3xx) have its own device-tree clock initializing function, to be able to register its own specific core clocks. Apply that change specifically to pxa27x. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17clk: pxa: declare init function and data __initRobert Jarzmik3-20/+32
As the clock descriptions are constant and only usefull at init time, mark them as such by : - spliting clock description (desc) and clock private data (dynamic) - mark __initdata clock descriptions This makes all the register and descriptions of the clocks to go after kernel init phase. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17clk: pxa: fix pxa27x CCCR bit usageRobert Jarzmik1-2/+2
Trivial fix to check the A bit of CCCR for memory frequency calculations, where the shift of the bit index was missing, triggering a wrong calculation of memory frequency. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17clk: add pxa25x clock driversRobert Jarzmik2-0/+274
Move pxa25x clock drivers from arch/arm/mach-pxa to driver/clk. In the move : - convert to new clock framework legacy clocks - provide clocks as before for platform data based boards - provide clocks through devicetree with clk-pxa-dt This is the preliminary step in the conversion. The remaining steps are : - pxa3xx - once PXA is fully converted to device tree, if that happens, clk-pxa2* and clk-pxa3* should only hold the core clocks which cannot be described in devicetree. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-09-30clk: add pxa27x clock driversRobert Jarzmik2-0/+371
Move pxa27x clock drivers from arch/arm/mach-pxa to driver/clk. In the move : - convert to new clock framework legacy clocks - provide clocks as before for platform data based boards - provide clocks through devicetree Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-30clk: add pxa clocks infrastructureRobert Jarzmik3-0/+205
Add a the common code used by all PXA variants. This is the first step in the transition from architecture defined clocks (in arch/arm/mach-pxa) towards clock framework. The goal is to have the same features (and not all the features) of the existing clocks, and enable the transition of PXA to device-tree. All PXA rely on a "CKEN" type clock, which : - has a gate (bit in CKEN register) - is generated from a PLL, generally divided - has an alternate low power clock Each variant will specialize the CKEN clock : - pxa25x have no low power clock - pxa27x in low power use always the 13 MHz ring oscillator - pxa3xx in low power have specific dividers for each clock The device-tree provides a list of CLK_* (ex: CLK_USB or CLK_I2C) to get a handle on the clock. While pxa-clock.h will describe all the clocks of all the variants, each variant will only use a subset of it. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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