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path: root/drivers/clk/clk-versaclock5.c
AgeCommit message (Expand)AuthorFilesLines
2023-01-18clk: vc5: Add support for 5P49V60Lars-Peter Clausen1-3/+22
2023-01-18clk: vc5: Use `clamp()` to restrict PLL rangeLars-Peter Clausen1-4/+1
2022-11-22clk: Remove a useless includeChristophe JAILLET1-1/+0
2022-10-08Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-58/+105
2022-10-04Merge branches 'clk-baikal', 'clk-broadcom', 'clk-vc5' and 'clk-versaclock' i...Stephen Boyd1-57/+104
2022-10-03clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975Matthias Fend1-0/+11
2022-09-30clk: vc5: Use regmap_{set,clear}_bits() where appropriateLars-Peter Clausen1-20/+15
2022-09-30clk: vc5: Check IO access resultsLars-Peter Clausen1-50/+91
2022-09-30clk: vc5: Fix 5P49V6901 outputs disabling when enabling FODSerge Semin1-1/+1
2022-08-22dt-bindings: clock: Move versaclock.h to dt-bindings/clockLukas Bulwahn1-1/+1
2022-08-16i2c: Make remove callback return voidUwe Kleine-König1-3/+1
2021-11-02clk: vc5: Use i2c .probe_newLuca Ceresoli1-2/+2
2021-08-28clk: vc5: Add properties for configuring SD/OE behaviorSean Anderson1-0/+24
2021-08-28clk: vc5: Use dev_err_probeSean Anderson1-10/+10
2021-06-08clk: vc5: fix output disabling when enabling a FODLuca Ceresoli1-3/+24
2021-02-11clk: vc5: Add support for optional load capacitanceAdam Ford1-0/+64
2020-12-19clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"Geert Uytterhoeven1-2/+2
2020-07-23clk: vc5: use a dedicated struct to describe the output driversLuca Ceresoli1-9/+15
2020-07-22clk: vc5: Add memory check to prevent oopsAdam Ford1-3/+5
2020-07-22clk: vc5: fix use of memory after it has been kfree'dColin Ian King1-32/+18
2020-06-22clk: vc5: Enable addition output configurations of the VersaclockAdam Ford1-0/+156
2020-06-22clk: vc5: Allow Versaclock driver to support multiple instancesAdam Ford1-47/+37
2020-05-30clk: vc5: Add support for IDT VersaClock 5P49V6965Adam Ford1-0/+11
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner1-10/+1
2019-01-09clk: vc5: Abort clock configuration without upstream clockMarek Vasut1-1/+3
2018-12-14clk: vc5: Add suspend/resume supportMarek Vasut1-0/+25
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V5925Vladimir Barinov1-0/+11
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V6901Marek Vasut1-0/+11
2017-07-17clk: vc5: Add support for the input frequency doublerMarek Vasut1-1/+77
2017-07-17clk: vc5: Split clock input mux and predividerMarek Vasut1-12/+34
2017-07-17clk: vc5: Configure the output buffer input mux on prepareMarek Vasut1-0/+19
2017-07-17clk: vc5: Do not warn about disabled output buffer input muxesMarek Vasut1-0/+3
2017-07-17clk: vc5: Fix trivial typoMarek Vasut1-1/+1
2017-07-17clk: vc5: Prevent division by zero on unconfigured outputsMarek Vasut1-0/+4
2017-04-19clk: vc5: Add support for IDT VersaClock 5P49V5935Alexey Firago1-2/+13
2017-04-19clk: vc5: Add structure to describe particular chip featuresAlexey Firago1-18/+47
2017-01-20clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933Marek Vasut1-0/+791