drm-tip - DRM current development and nightly trees

Age	Commit message (Collapse)	Author	Files	Lines
2015-03-24	arm64: pmu: add support for interrupt-affinity property	Will Deacon	1	-0/+1
	Historically, the PMU devicetree bindings have expected SPIs to be listed in order of logical CPU number. This is problematic for bootloaders, especially when the boot CPU (logical ID 0) isn't listed first in the devicetree. This patch adds a new optional property, interrupt-affinity, to the PMU node which allows the interrupt affinity to be described using a list of phandled to CPU nodes, with each entry in the list corresponding to the SPI at the same index in the interrupts property. Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-09-17	arm64: Performance counters support	Will Deacon	1	-0/+82
	This patch adds support for the AArch64 performance counters. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>