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2021-05-18ARM: dts: sun8i: r40: Add timer nodeJernej Skrabec1-0/+12
Allwinner R40 has a timer. Add a node for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210510163647.2731675-1-jernej.skrabec@gmail.com
2021-05-10ARM: dts: sun8i: r40: add pinmux settings for MMC3 and UARTs 2, 4, 5&7Ivan Uvarov1-0/+41
The Forlinx OKA40i-C devboard makes use of UARTs 0,2,3,4,5 and 7 of the R40 SoC, of which UART 0 is connected to an RS232 converter, UART 5 routed to an RS485 converter, and the rest broken out directly via labeled headers. The board also contains a micro-SD slot connected to SDC3. This patch adds settings to R40's pinmux node for MMC3 and those UARTs that were not already mapped, which would allow us to make use of all available UARTs and the micro-SD slot on this board in a further patch. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com> 1 file changed, 41 insertions(+) Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210407111428.3755684-3-i.uvarov@cognitivepilot.com
2021-05-10ARM: dts: sun8i: r40: add /omit-if-no-ref/ to pinmux nodes for UARTs 0&3Ivan Uvarov1-0/+3
This patch adds the /omit-if-no-ref/ keyword to the pio nodes for UART0 and UART3 pins of the R40 SoC, which would reduce the fdt size on boards which do not use these UARTs. Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com> 1 file changed, 3 insertions(+) Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210407111428.3755684-2-i.uvarov@cognitivepilot.com
2021-01-07ARM: dts: sun8i: r40: Add deinterlace nodeJernej Skrabec1-0/+19
R40 contains deinterlace core compatible to that in H3. One peculiarity is that RAM gate is shared with CSI1. User manual states it's separate but that's not true. Shared gate was verified with BSP Linux code check and with runtime tests (CPU crashed if CSI1 gate was not ungated). Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210106181901.1324075-3-jernej.skrabec@siol.net
2020-09-17ARM: dts: sun8i: r40: Add video engine nodeJernej Skrabec1-0/+11
Allwinner R40 SoC has a video engine. Add a node for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200825173523.1289379-6-jernej.skrabec@siol.net
2020-08-27ARM: dts: sun8i: r40: Add node for system controllerJernej Skrabec1-0/+23
Allwinner R40 has system controller and SRAM C1 region similar to that in A10. Add nodes for them. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200825173523.1289379-3-jernej.skrabec@siol.net
2020-08-27ARM: dts: sun8i: r40: Add IR nodesJernej Skrabec1-0/+36
Allwinner R40 has two IR cores, add nodes for them. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200825171358.1286902-3-jernej.skrabec@siol.net
2020-08-25ARM: dts: sun8i: r40: Add DMA nodeJernej Skrabec1-0/+12
Allwinner R40 SoC has DMA with 16 channels and 31 request sources. Add a node for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200825100030.1145356-3-jernej.skrabec@siol.net
2020-08-25ARM: dts: sun8i: r40: Add Mali nodeJernej Skrabec1-0/+22
R40 has Mali400 GP2 GPU. Add a node for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200824150434.951693-3-jernej.skrabec@siol.net
2020-04-03Merge tag 'arm-dt-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-1/+29
Pull ARM devicetree updates from Arnd Bergmann: "Most of the commits are for additional hardware support and minor fixes for existing machines for all the usual platforms: qcom, amlogic, at91, gemini, mediatek, ti, socfpga, i.mx, layerscape, uniphier, rockchip, exynos, ux500, mvebu, tegra, stm32, renesas, sunxi, broadcom, omap, and versatile. The conversion of binding files to machine-readable yaml format continues, along with fixes found during the validation. Andre Przywara takes over maintainership for the old Calxeda Highbank platform and provides a number of updates. The OMAP2+ platforms see a continued move from platform data into dts files, for many devices that relied on a mix of auxiliary data in addition to the DT description A moderate number of new SoCs and machines are added, here is a full list: - Two new Qualcomm SoCs with their evaluation boards: Snapdragon 865 (SM8250) is the current high-end phone chip, and IPQ6018 is a new WiFi-6 router chip. - Mediatek MT8516 application processor SoC for voice assistants, along with the "pumpkin" development board - NXP i.MX8M Plus SoC, a variant of the popular i.MX8M, along with an evaluation board. - Kontron "sl28" board family based on NXP LS1028A - Eleven variations of the new i.MX6 TechNexion Pico board, combining the "dwarf", "hobbit", "nymph" and "pi" baseboards with i.MX6/i.MX7 SoM carriers - Three additional variants of the Toradex Colibri board family, all based on versions of the NXP i.MX7. - The Pinebook Pro laptop based on Rockchip RK3399 - Samsung S7710 Galaxy Xcover 2, a 2013 vintage Android phone based on the ST-Ericsson u8500 platform - DH Electronics DHCOM SoM and PDK2 rev. 400 carrier based on STMicroelectronics stm32mp157 - Renesas M3ULCB starter kit for R-Car M3-W+ - Hoperun HiHope development board with Renesas RZ/G2M - Pine64 PineTab tablet and PinePhone phone, both based on Allwinner A64 - Linutronix Testbox v2 for the Lamobo R1 router, based on Allwinner A20 - PocketBook Touch Lux 3 ebook reader, based on Allwinner A13" * tag 'arm-dt-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (520 commits) ARM: dts: ux500: Fix missing node renames arm64: dts: Revert "specify console via command line" MAINTAINERS: Update Calxeda Highbank maintainership arm: dts: calxeda: Group port-phys and sgpio-gpio items arm: dts: calxeda: Fix interrupt grouping arm: dts: calxeda: Provide UART clock arm: dts: calxeda: Basic DT file fixes arm64: dts: specify console via command line ARM: dts: at91: sama5d27_wlsom1_ek: add USB device node ARM: dts: gemini: Add thermal zone to DIR-685 ARM: dts: gemini: Rename IDE nodes ARM: socfpga: arria10: Add ptp_ref clock to ethernet nodes arm64: dts: ti: k3-j721e-mcu: add scm node and phy-gmii-sel nodes arm64: dts: ti: k3-am65-mcu: add phy-gmii-sel node arm64: dts: ti: k3-am65-mcu: Add DMA entries for ADC arm64: dts: ti: k3-am65-main: Add DMA entries for main_spi0 arm64: dts: ti: k3-j721e-mcu-wakeup: Add DMA entries for ADC arm64: dts: ti: k3-am65: Add clocks to dwc3 nodes arm64: dts: meson-g12b-odroid-n2: add SPIFC controller node arm64: dts: khadas-vim3: add SPIFC controller node ...
2020-04-02Merge tag 'devicetree-for-5.7' of ↵Linus Torvalds1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: - Unit test for overlays with GPIO hogs - Improve dma-ranges parsing to handle dma-ranges with multiple entries - Update dtc to upstream version v1.6.0-2-g87a656ae5ff9 - Improve overlay error reporting - Device link support for power-domains and hwlocks bindings - Add vendor prefixes for Beacon, Topwise, ENE, Dell, SG Micro, Elida, PocketBook, Xiaomi, Linutronix, OzzMaker, Waveshare Electronics, and ITE Tech - Add deprecated Marvell vendor prefix 'mrvl' - A bunch of binding conversions to DT schema continues. Of note, the common serial and USB connector bindings are converted. - Add more Arm CPU compatibles - Drop Mark Rutland as DT maintainer :( * tag 'devicetree-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (106 commits) MAINTAINERS: drop an old reference to stm32 pwm timers doc MAINTAINERS: dt: update etnaviv file reference dt-bindings: usb: dwc2: fix bindings for amlogic, meson-gxbb-usb dt-bindings: uniphier-system-bus: fix warning in the example dt-bindings: display: meson-vpu: fix indentation of reg-names' "items" dt-bindings: iio: Fix adi, ltc2983 uint64-matrix schema constraints dt-bindings: power: Fix example for power-domain dt-bindings: arm: Add some constraints for PSCI nodes of: some unittest overlays not untracked of: gpio unittest kfree() wrong object dt-bindings: phy: convert phy-rockchip-inno-usb2 bindings to yaml dt-bindings: serial: sh-sci: Convert to json-schema dt-bindings: serial: Document serialN aliases dt-bindings: thermal: tsens: Set 'additionalProperties: false' dt-bindings: thermal: tsens: Fix nvmem-cell-names schema dt-bindings: vendor-prefixes: Add Beacon vendor prefix dt-bindings: vendor-prefixes: Add Topwise of: of_private.h: Replace zero-length array with flexible-array member docs: dt: fix a broken reference to input.yaml docs: dt: fix references to ap806-system-controller.txt ...
2020-03-19ARM: dts: sunxi: Fix dtc 'dma-ranges' warningsRob Herring1-0/+2
'#address-cells' and '#size-cells' are needed in the same node (for the child bus) as 'dma-ranges' in order to parse it. The kernel is more lax and will walk up the tree to get the properties from a parent node, but it's better to be explicit. dtc now does checks on 'dma-ranges' and is more strict: arch/arm/boot/dts/sun5i.dtsi:189.4-52: Warning (dma_ranges_format): \ /soc/dram-controller@1c01000:dma-ranges: "dma-ranges" property has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1) arch/arm/boot/dts/sun8i-r40.dtsi:742.4-52: Warning (dma_ranges_format): \ /soc/dram-controller@1c62000:dma-ranges: "dma-ranges" property has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1) arch/arm/boot/dts/sunxi-h3-h5.dtsi:563.4-52: Warning (dma_ranges_format): \ /soc/dram-controller@1c62000:dma-ranges: "dma-ranges" property has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1) Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
2020-03-12ARM: dts: sunxi: Fix DE2 clocks register rangeJernej Skrabec1-1/+1
As it can be seen from DE2 manual, clock range is 0x10000. Fix it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Fixes: 73f122c82775 ("ARM: dts: sun8i: a83t: Add display pipeline") Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline") Fixes: 21b299209330 ("ARM: sun8i: v3s: add device nodes for DE2 display pipeline") Fixes: d8c6f1f0295c ("ARM: sun8i: h3/h5: add DE2 CCU device node for H3") [wens@csie.org: added fixes tags] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-03-11ARM: dts: sun8i: r40: Move SPI device nodes based on address orderChen-Yu Tsai1-52/+52
When the SPI device nodes were added, they were added in the wrong location in the device tree file. The device nodes should be sorted by register address. Move the devices node to their correct positions within the file. Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes") Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-03-11ARM: dts: sun8i: r40: Fix register base address for SPI2 and SPI3Chen-Yu Tsai1-4/+4
When the SPI device nodes were added, SPI2 and SPI3 had incorrect register base addresses. Fix the base address for both of them. Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes") Reported-by: JuanEsf <juanesf91@gmail.com> Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-03-11ARM: dts: sun8i: r40: Move AHCI device node based on address orderChen-Yu Tsai1-11/+10
When the AHCI device node was added, it was added in the wrong location in the device tree file. The device nodes should be sorted by register address. Move the device node to before EHCI1, where it belongs. Fixes: 41c64d3318aa ("ARM: dts: sun8i: r40: add sata node") Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-02-10ARM: dts: sun8i-r40: Add thermal sensor and thermal zonesYangtao Li1-0/+28
There are two sensors, sensor0 for CPU, sensor1 for GPU. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-06ARM: dts: sunxi: Use macros for references to CCU clocksChen-Yu Tsai1-1/+1
A few clocks from the CCU were exported later, and references to them in the device tree were using raw numbers. Now that the DT binding header changes are in as well, switch to the macros for more clarity. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-06ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxesAndre Przywara1-0/+82
The Allwinner R40 SoC contains four SPI controllers, using the newer sun6i design (but at the legacy addresses). The controller seems to be fully compatible to the A64 one, so no driver changes are necessary. The first three controllers can be used on two sets of pins, but SPI3 is only routed to one set on Port A. Only the pin groups for SPI0 on PortC and SPI1 on PortI are added here, because those seem to be the only one exposed on the Bananapi boards. Tested by connecting a SPI flash to a Bananapi M2 Berry SPI0 and SPI1 header pins. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-06ARM: dts: sun8i: r40: Add device node for CSI0Chen-Yu Tsai1-0/+36
The CSI0 and CSI1 blocks are the same as found on the A20. However only CSI0 is supported upstream right now. Add a device node for CSI0 using the A20 compatible as a fallback, and the standard pinctrl options. Also add the MBUS interconnect. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-03ARM: dts: sun8i: r40: Use tcon top clock index macrosJagan Teki1-2/+3
tcon_tv0, tcon_tv1 nodes have a clock names of tcon-ch0, tcon-ch1 which are referring tcon_top clocks via index numbers like 0, 1 with CLK_TCON_TV0 and CLK_TCON_TV1 respectively. Use the macro in place of index numbers, for more code readability. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-03ARM: dts: sun8i: R40: Add PMU nodeAndre Przywara1-4/+13
The ARM Cortex-A7 cores used in the Allwinner R40 SoC have their usual Performance Monitoring Unit (PMU), which allows perf to use hardware events. The SoC integrator just needs to connect each per-core interrupt line to the GIC. The R40 manual does not really mention those IRQ lines, but experimentation in U-Boot shows that interrupts 152-155 are connected to the four cores (similar to the A20). Tested on a Bananapi M2 Berry, with perf and taskset to confirm the association between cores and interrupts. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-03ARM: dts: sun8i: R40: Upgrade GICC reg size to 8KAndre Przywara1-1/+1
The GIC used in the R40 SoC is an ARM GIC-400 with virtualization support, so let's advertise the full 8K region of the GICC MMIO frame to enable KVM's usage of the GIC (as we do already for all other SoCs). Tested by running KVM on a Bananapi M2 Berry. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-16ARM: dts: sun8i: r40: Add I2C pinmux optionsChen-Yu Tsai1-0/+28
The R40 has five I2C controllers. Currently only I2C0 has its pinmux option defined. Add the options for the remaining four, and set them as the default, since each controller has only one possible pinmux configuration. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-05Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-0/+9
Pull ARM Device-tree updates from Olof Johansson: "As always, the bulk of updates. Some of the news this cycle: New SoC descriptions: - Broadcom BCM2711 - Amlogic Meson A1 and G12 - Freescale S32V234 - Marvell Armada AP807/AP807-quad and CP115 - Realtek RTD1293 and RTD1296 - Rockchip RK3308 New boards and platforms: - Allwinner: NanoPi Duo2 - Amlogic: Ugoos am6 - Atmel at91: Overkiz Kizbox2/4 - Broadcom: RPi4, Luxul XWC-2000 - Marvell: New Espressobin flavor - NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and OPOS6ULDev - Renesas: Salvator-XS - Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (653 commits) ARM: dts: logicpd-torpedo: Disable USB Host arm: dts: mt6323: add keys, power-controller, rtc and codec arm64: dts: mt8183: add systimer0 device node dt-bindings: mediatek: update bindings for MT8183 systimer arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board. arm64: dts: rockchip: Add Beelink A1 dt-bindings: ARM: rockchip: Add Beelink A1 arm64: dts: rockchip: Add RK3328 audio pipelines arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports arm64: dts: ti: k3-j721e-main: add USB controller nodes ARM: dts: aspeed-g6: Add timer description ARM: dts: aspeed: ast2600evb: Enable i2c buses ARM: dts: at91: add a dts and dtsi file for kizbox2 based boards dt-bindings: arm: at91: Document Kizbox2-2 board binding arm64: dts: meson-gx: fix i2c compatible arm64: dts: meson-gx: cec node should be disabled by default arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible arm64: dts: meson-gxm: fix gpu irq order arm64: dts: meson-g12a: fix gpu irq order ...
2019-11-01ARM: dts: sun8i: R40: add crypto engine nodeCorentin Labbe1-0/+9
The Crypto Engine is a hardware cryptographic offloader that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner R40 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-10-04ARM: dts: sunxi: Revert phy-names removal for ECHI and OHCIMaxime Ripard1-0/+4
This reverts commits 3d109bdca981 ("ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI"), 0a3df8bb6dad ("ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI") and 3c7ab90aaa28 ("arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCI"). It turns out that while the USB bindings were not mentionning it, the PHY client bindings were mandating that phy-names is set when phys is. Let's add it back. Fixes: 3d109bdca981 ("ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI") Fixes: 0a3df8bb6dad ("ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI") Fixes: 3c7ab90aaa28 ("arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCI") Reported-by: Emmanuel Vadot <manu@bidouilliste.com> Signed-off-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20191002112651.100504-1-mripard@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-08-23ARM: dts: sunxi: Add missing watchdog clocksMaxime Ripard1-0/+1
The watchdog has a clock on all our SoCs, but it wasn't always listed. Add it to the devicetree where it's missing. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-08-23ARM: dts: sunxi: Add missing watchdog interruptsMaxime Ripard1-0/+1
The watchdog has an interrupt on all our SoCs, but it wasn't always listed. Add it to the devicetree where it's missing. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-23ARM: dts: sunxi: Fix the HDMI PHY nameMaxime Ripard1-1/+1
Even though the binding mentions that the PHY name must be "phy", it turns out that all our DTs had "hdmi-phy" instead. The code doesn't care about the phy-names property, so we can just change our DTs to match the binding, without any side effect. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-22ARM: dts: sunxi: Unify the DE2 bus clocks orderMaxime Ripard1-4/+4
The DE2 bus takes two clocks, named bus and mod according to the binding. However, the order of these clocks change from one SoC to another. Even though it might not be an issue in most cases, having consistency will help if we ever need to have some code to deal with deprecated bindings, and in general it's just better. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-06-06ARM: dts: sun8i: r40: Change the RTC compatibleMaxime Ripard1-2/+1
Unlike what's being reported in the device tree so far, the RTC in the R40 is quite different from the H3. Indeed it doesn't have the internal oscillator output, and it has only a single interrupt. Let's add a compatible for it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCIMaxime Ripard1-4/+0
Neither the OHCI or EHCI bindings are using the phy-names property, so we can just drop it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: r40: Remove useless AHCI propertiesMaxime Ripard1-2/+0
The SATA controller never have any children nodes, so we don't need the address and size cells properties. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: r40: Fix AHCI reset-names propertyMaxime Ripard1-1/+1
The AHCI node was introduced with a typo in the reset-names property that got written resets-name instead. This was working because the reset is optional for that driver, and the controller was put out of reset by the bootloader. Fixes: 41c64d3318aa ("ARM: dts: sun8i: r40: add sata node") Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: r40: Fix Display Engine DTC warningsMaxime Ripard1-4/+1
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-09ARM: dts: sun8i: r40: Add pinmux setting for CLK_OUT_AChen-Yu Tsai1-0/+5
CLK_OUT_A, an external clock output function driven from the clock control unit, on the R40 is sometimes used to provide a low rate low power clock to a WiFi or Bluetooth controller. This patch adds a pinmux setting for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-09ARM: dts: sun8i: r40: Add pinmux settings for UART3 on PG pingroupChen-Yu Tsai1-0/+10
UART3 on the PG pingroup on the R40 SoC is commonly used to connect the bluetooth controller in a WiFi+Bluetooth combo chip, with the WiFi bits also on the PG pingroup. This patch adds two device nodes for UART3 on PG pingroup, one for the RX/TX pins, and one for the RTS/CTS pins. Consumers can reference either just the RX/TX pinmux setting or both, depending on the application. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-07ARM: dts: sun8i: r40: Add RTC device nodeChen-Yu Tsai1-3/+13
The R40 has an RTC hardware block, which has additional registers that are not related to RTC or clock functions, and is otherwise compatible with the H3's RTC. Add a device node for it, and fix up any references to the LOSC. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-12-06ARM: dts: sun8i: r40: Add clock accuracy for external oscillatorsChen-Yu Tsai1-0/+2
The R40 datasheet specifies a tolerance range for the external oscillators used. Add them to the device tree as the clock accuracy. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-10-29Merge tag 'armsoc-dt' of ↵Linus Torvalds1-0/+13
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree updates from Arnd Bergmann: "There are close to 800 indivudal changesets in this branch again, which feels like a lot. There are particularly many changes for the NVIDIA Tegra platform this time, in fact more than it has seen in the two years since the v4.9 merge window. Aside from this, it's been fairly normal, with lots of changes going into Renesas R-CAR, NXP i.MX, Allwinner Sunxi, Samsung Exynos, and TI OMAP. Most of the changes are for adding new features into existing boards, for brevity I'm only mentioning completely new machines and SoCs here. For the first time I think we have (slightly) more new 64-bit hardware than 32-bit: Two boards get added for TI OMAP: Moxa UC-2101 is an industrial computer, see https://www.moxa.com/product/UC-2100.htm; GTA04A5 is a minor variation of the motherboards of the GTA04 phone, see https://shop.goldelico.com/wiki.php?page=GTA04A5 Clearfog is a nice little board for quad-core Marvell Armada 8040 network processor, see https://www.solid-run.com/marvell-armada-family/clearfog-gt-8k/ Two additional server boards come with the Aspeed baseboard management controllers: Stardragon4800 is an arm64 reference platform made by HXT (based on Qualcomm's server chips), and TiogaPass is an Open Compute mainboard with x86 CPUs. Both use the ARM11 based AST2500 chips in the BMC. NXP i.MX usually sees a lot of new boards each release. This time there we only add one minor variant: ConnectCore 6UL SBC Pro uses the same SoM design as the ConnectCore 6UL SBC Express added later. However, there is a new chip, the i.MX6ULZ, which is an even smaller variant of the i.MX6ULL, with features removed. There is also support for the reference board design, the i.MX6ULZ 14x14 EVK. A new Raspberry Pi variant gets added, this one is the CM3 compute module based on bcm2837, it was launched in early 2017 but only now added to the kernel, both as 32-bit and as 64-bit files, as we tend to do for Raspberry Pi. On the Allwinner side, everything is again about cheap development boards, usually of the "Fruit Pi" variety. The new ones this time are: - Orange Pi Zero Plus2: http://www.orangepi.org/OrangePiZeroPlus2/ - Orange Pi One Plus: http://www.orangepi.org/OrangePiOneplus/ - Pine64 LTS: https://www.pine64.org/?product=pine-a64-lts - Banana Pi M2+ H5: http://www.banana-pi.org/m2plus.html The last one of these is now a 64-bit version of the earlier Banana Pi M2+ H3, with the same board layout. Similarly, for Rockchips, get get another variant of the 32-bit Asus Tinker board, the model 'S' based on rk3288, and three now boards based on the popular RK3399 chip: - ROC-RK3399-PC: https://libre.computer/products/boards/roc-rk3399-pc/ - Rock960: https://www.96boards.org/product/rock960/ - RockPro64: https://www.pine64.org/?page_id=61454 These are all quite powerful boards with lots of RAM and I/O, and the RK3399 is the same chip used in several Chromebooks. Finally, we get support for the PX30 (aka rk3326) chip, which is based on the low-end 64-bit Cortex-A35 CPU core. So far, only the evaluation board is supported. One more Banana Pi is added with a Mediatek chip: Banana Pi R64 is based on the MT7622 WiFi router platform, and the first product I've seen with a 64-bit Mediatek chip in that market: http://www.banana-pi.org/r64.html For HiSilicon, we gain support for the Hi3670 SoC and HiKey 370 development board, which are similar to the Hi3660 and Hikey 360 respectively, but add support for an NPU. Amlogic gets initial support for the Meson-G12A chip (S905D2), another quad-core Cortex-A53 SoC, and its evaluation platform. On the 32-bit side, we gain support for an actual end-user product, the Endless Computers Endless Mini based on Meson8b (S805), see https://endlessos.com/computers/ Qualcomm adds support for their MSM8998 SoC and evaluation platform. This chip is commonly known as the Snapdragon 835, and is used in high-end phones as well as low-end laptops. For Renesas, a very bare support for the r8a774a1 (RZ/G2M) is added, but no boards for this one. However, we do add boards for the previously added r8a77965 (R-Car M3-N): the M3NULCB Kingfisher and the M3NULCB Starter Kit Pro. While we have lots of DT changes for NVIDIA to update the existing files, the only board that gets added is the Toradex Colibri T20 on Colibri Evaluation Board for the old Tegra2. Synaptics add support for their AS370 SoC, which is part of the (formerly Marvell) Berlin line of set-top-box chips used e.g. in the various Google Chromecast. Only the .dtsi gets added at this point, no actual machines" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (721 commits) ARM: dts: socfgpa: remove ethernet aliases from dtsi arm64: dts: stratix10: add ethernet aliases dt-bindings: mediatek: Add bindig for MT7623 IOMMU and SMI dt-bindings: mediatek: Add JPEG Decoder binding for MT7623 dt-bindings: iommu: mediatek: Add binding for MT7623 dt-bindings: clock: mediatek: add support for MT7623 ARM: dts: mvebu: armada-385-db-88f6820-amc: auto-detect nand ECC properites ARM: dts: da850-lego-ev3: slow down A/DC as much as possible ARM: dts: da850-evm: Enable tca6416 on baseboard arm64: dts: uniphier: Add USB2 PHY nodes arm64: dts: uniphier: Add USB3 controller nodes ARM: dts: uniphier: Add USB2 PHY nodes ARM: dts: uniphier: Add USB3 controller nodes arm64: dts: meson-axg: s400: disable emmc arm64: dts: meson-axg: s400: add missing emmc pwrseq arm64: dts: clearfog-gt-8k: add PCIe slot description ARM: dts: at91: sama5d4_xplained: even nand memory partitions ARM: dts: at91: sama5d3_xplained: even nand memory partitions ARM: dts: at91: at91sam9x5cm: even nand memory partitions ARM: dts: at91: sama5d2_ptc_ek: fix bootloader env offsets ...
2018-09-20ARM: dts: sun8i: drop A64 HDMI PHY fallback compatible from R40 DTIcenowy Zheng1-2/+1
The R40 HDMI PHY seems to be different to the A64 one, the A64 one has no input mux, but the R40 one has. Drop the A64 fallback compatible from the HDMI PHY node in R40 DT. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> [wens@csie.org: Fix subject prefix order] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-09-05ARM: dts: sun8i: r40: add sata nodeCorentin Labbe1-0/+13
R40 have a sata controller which is the same as A20. This patch adds a DT node for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-19ARM: dts: sun8i: r40: Remove unused address-cells/size-cells of dwmac-sun8iCorentin Labbe1-2/+0
address-cells/size-cells is unnecessary for dwmac-sun8i node. It was in early days, but since a mdio node is used, it could be removed. This patch fix the following DT warning: Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-11ARM: dts: sun8i: r40: Disable TCONs by default.Jernej Skrabec1-0/+2
R40 has 4 TCONs, but only 2 of them can receive some kind of output at the same time. Let's disable them by default, so only those which are really connected on board can be enabled in board dts file. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-11ARM: dts: sun8i: r40: Add missing TCON-TOP - TCON connectionsJernej Skrabec1-0/+44
Current R40 is missing some graph connections between TCON TOP and TCONs. Add them. Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline") Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-11ARM: dts: sun8i: r40: Remove fallback compatible for TCON TVJernej Skrabec1-4/+2
A83T and R40 TCON TV are very similar. However, R40 TCON TV is wired differently, which makes it incompatible with A83T TCON TV. Because of that, remove fallback A83T TCON TV compatible. Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline") Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-11ARM: dts: sun8i: r40: Add mixer ids to TCON TOPJernej Skrabec1-2/+8
sun4i-drm DT binding, second paragraph of the first section says: For all connections between components up to the TCONs in the display pipeline, when there are multiple components of the same type at the same depth, the local endpoint ID must be the same as the remote component's index. Add mixer ids in R40 DT as mandated by DT binding. Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline") Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-11ARM: dts: sun8i: r40: Remove fallback display engine compatibleJernej Skrabec1-2/+1
R40 has pretty unique display pipeline. Because of that, H3 display engine compatible fallback should be removed. Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline") Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-06-28ARM: dts: sun8i: r40: Add HDMI pipelineJernej Skrabec1-0/+268
Add all entries needed for HDMI to function properly. Since R40 has highly configurable pipeline, both mixers and both TCON TVs are added. Board specific DT should then connect them together trough TCON TOP muxers to best fit the purpose of the board. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-24 22:35:08 +0000