diff options
| author | Len Brown <len.brown@intel.com> | 2017-06-23 20:45:54 -0700 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2017-06-24 20:03:41 -0700 |
| commit | f26b151977447be3b86f92c91e1caedc9b5eb8bf (patch) | |
| tree | 6ce904236f05380e4f9cd141416ba81987f863ed /tools/power/x86 | |
| parent | c91fc8519d87715a3a173475ea3778794c139996 (diff) | |
tools/power turbostat: decode MSR_IA32_MISC_ENABLE only on Intel
otherwise, turbostat bails on on AMD Opteron boxes:
turbostat: cpu26: msr offset 0x1a0 read failed: Input/output error
Reported-by: Kamil Kolakowski <kkolakow@redhat.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'tools/power/x86')
| -rw-r--r-- | tools/power/x86/turbostat/turbostat.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 1a3a5b436b80..33992a93148b 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -3943,6 +3943,9 @@ void decode_misc_enable_msr(void) { unsigned long long msr; + if (!genuine_intel) + return; + if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", base_cpu, msr, |