diff options
| author | Atish Patra <atishp@rivosinc.com> | 2022-01-20 01:09:13 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-01-20 09:26:59 -0800 |
| commit | 9a2451f1866344d38b4a1dc20396e3a03954fcd7 (patch) | |
| tree | 554497f0f45fad78ebdbed0e32e3470eea8adbbc /security | |
| parent | 3938d5a2f9369d1ebd56320629fed395ce327e9c (diff) | |
RISC-V: Avoid using per cpu array for ordered booting
Currently both order booting and spinwait approach uses a per cpu
array to update stack & task pointer. This approach will not work for the
following cases.
1. If NR_CPUs are configured to be less than highest hart id.
2. A platform has sparse hartid.
This issue can be fixed for ordered booting as the booting cpu brings up
one cpu at a time using SBI HSM extension which has opaque parameter
that is unused until now.
Introduce a common secondary boot data structure that can store the stack
and task pointer. Secondary harts will use this data while booting up
to setup the sp & tp.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'security')
0 files changed, 0 insertions, 0 deletions