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authorSylwester Nawrocki <s.nawrocki@samsung.com>2016-09-02 18:47:45 +0200
committerSylwester Nawrocki <s.nawrocki@samsung.com>2016-09-09 17:35:11 +0200
commit2ec865b79b3852de6c663073c7a004e1fb918c3b (patch)
treecbc4bd342ee1a0bba7a2674ab62a99a8f5fb75a8 /drivers
parent7c3ca061d4cfb25537d90a9ad936667b909133a0 (diff)
clk: samsung: clk-exynos-audss: Add exynos5410 compatible
Exynos5410 Audio Subsystem Clock Controller, comparing to the already supported IP block revisions, has additionally an I2S_MST divider so a new compatible string is added. It is not clear from the Exynos5410 User's Manual released on 2012.03.09 where in the clock tree the I2S_MST clock divider can be found exactly so this clock is left unimplemented for now. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/samsung/clk-exynos-audss.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 7d4026b01c9a..628f86b60eab 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -70,6 +70,7 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
struct exynos_audss_clk_drvdata {
unsigned int has_adma_clk:1;
+ unsigned int has_mst_clk:1;
unsigned int enable_epll:1;
unsigned int num_clks;
};
@@ -78,6 +79,11 @@ static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
.num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
};
+static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
+ .num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
+ .has_mst_clk = 1,
+};
+
static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
.num_clks = EXYNOS_AUDSS_MAX_CLKS,
.has_adma_clk = 1,
@@ -92,6 +98,9 @@ static const struct of_device_id exynos_audss_clk_of_match[] = {
.compatible = "samsung,exynos5250-audss-clock",
.data = &exynos4210_drvdata,
}, {
+ .compatible = "samsung,exynos5410-audss-clock",
+ .data = &exynos5410_drvdata,
+ }, {
.compatible = "samsung,exynos5420-audss-clock",
.data = &exynos5420_drvdata,
},