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authorAlex Deucher <alexander.deucher@amd.com>2018-01-05 10:25:57 -0500
committerAlex Deucher <alexander.deucher@amd.com>2018-02-19 14:17:14 -0500
commitb1d128689f9c602a3dbea37b47a27a568d55754d (patch)
tree6e7f5703c0ed9a28b140017fc3fc3bd0504a9cc4 /drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
parent73c732405fddfe16b122c77de83397289463b557 (diff)
drm/amdgpu: adjust HDP write queue flushing for tlb invalidation
Separate tlb invalidation and hdp flushing and move the HDP flush to the caller. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 12e49bd8fd2d..550abff5cb12 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -432,9 +432,6 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
uint32_t vmid)
{
- /* flush hdp cache */
- WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
-
/* bits 0-15 are the VM contexts0-15 */
WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
}