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authorRobert Jarzmik <robert.jarzmik@free.fr>2018-06-27 21:41:23 +0200
committerStephen Boyd <sboyd@kernel.org>2018-07-06 13:52:57 -0700
commitfc20654389364a55eeab837244b24f8da75009f6 (patch)
treea8ca51fda011e3f3d4417b5de2ef4821b569b519 /drivers/clk/pxa/clk-pxa3xx.c
parentce397d215ccd07b8ae3f71db689aedb85d56ab40 (diff)
clk: pxa: export 32kHz PLL
This clock is especially used by the RTC driver, so export it so that devicetree users can use it. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/pxa/clk-pxa3xx.c')
-rw-r--r--drivers/clk/pxa/clk-pxa3xx.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/clk/pxa/clk-pxa3xx.c b/drivers/clk/pxa/clk-pxa3xx.c
index 2d126df2bccd..7aa120c3bd08 100644
--- a/drivers/clk/pxa/clk-pxa3xx.c
+++ b/drivers/clk/pxa/clk-pxa3xx.c
@@ -286,9 +286,10 @@ static void __init pxa3xx_register_plls(void)
clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
CLK_GET_RATE_NOCACHE,
13 * MHz);
- clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
- CLK_GET_RATE_NOCACHE,
- 32768);
+ clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
+ clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
+ CLK_GET_RATE_NOCACHE,
+ 32768));
clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL,
CLK_GET_RATE_NOCACHE,
120 * MHz);