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authorAdam Ford <aford173@gmail.com>2024-02-03 10:52:44 -0600
committerUlf Hansson <ulf.hansson@linaro.org>2024-02-14 10:26:11 +0100
commit697624ee8ad557ab5417f985d2c804241a7ad30d (patch)
treef6a72490e0a5094091378ff20c6fbefa6c119295 /arch/sparc/Kconfig
parenta0691f280b3240dc4aeca7d0f0c824d0277c4856 (diff)
pmdomain: imx8mp-blk-ctrl: imx8mp_blk: Add fdcc clock to hdmimix domain
According to i.MX8MP RM and HDMI ADD, the fdcc clock is part of hdmi rx verification IP that should not enable for HDMI TX. But actually if the clock is disabled before HDMI/LCDIF probe, LCDIF will not get pixel clock from HDMI PHY and print the error logs: [CRTC:39:crtc-2] vblank wait timed out WARNING: CPU: 2 PID: 9 at drivers/gpu/drm/drm_atomic_helper.c:1634 drm_atomic_helper_wait_for_vblanks.part.0+0x23c/0x260 Add fdcc clock to LCDIF and HDMI TX power domains to fix the issue. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> Link: https://lore.kernel.org/r/20240203165307.7806-5-aford173@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'arch/sparc/Kconfig')
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