diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2021-03-02 15:09:52 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2021-03-24 16:06:44 +0100 |
| commit | ed34855b81799c561500228a9281de84fb5ecf4f (patch) | |
| tree | ce817fdfc35da9340a7f11df0570037abe9df59c /arch/arm/boot/dts/tegra30-cardhu.dtsi | |
| parent | 3744c7d88c00eb59e9543a1bcc23faf67af7bbaf (diff) | |
ARM: tegra: cardhu: Support CPU frequency and voltage scaling on all board variants
Enable CPU frequency and voltage scaling on all Tegra30 Cardhu board
variants.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30-cardhu.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra30-cardhu.dtsi | 40 |
1 files changed, 37 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index dab9989fa760..42ea949953c7 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 #include <dt-bindings/input/input.h> #include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" /** * This file contains common DT entry for all fab version of Cardhu. @@ -272,9 +274,14 @@ vddctrl_reg: vddctrl { regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; vio_reg: vio { @@ -342,17 +349,22 @@ interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>; }; - tps62361@60 { + vdd_core: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; regulator-name = "tps62361-vout"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-high; ti,vsel1-state-high; + + nvidia,tegra-core-regulator; }; }; @@ -424,6 +436,28 @@ #clock-cells = <0>; }; + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu1: cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu2: cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu3: cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + panel: panel { compatible = "chunghwa,claa101wb01"; ddc-i2c-bus = <&panelddc>; |