From 3cd88f993e8b24855ed135b36bc6ed53dff38f08 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 19 Apr 2012 19:35:10 +0100 Subject: Revert "ARM: 7359/2: smp_twd: Only wait for reprogramming on active cpus" This reverts commit 9f85550347f51c79a917b2aec04c90691c11e20a. Peter Zijlstra says: | Argh, how did that ever make it upstream, please drop. | | Russell, please make that go away upstream. | | Like I said, this is both completely the wrong way to solve, and you're | so not paying attention, see: | | 5fbd036b552f633abb394a319f7c62a5c86a9cd7 | 2baab4e90495ebc9826c93f79d74d6e60a828d24 | e3831edd59edf57ca11fc289f08961b20baf5146 | | What's even worse: | | git describe --contains 9f85550347f51c79a917b2aec04c90691c11e20a --match "v*" | v3.4-rc3~1^2~3 | | that nonsense got merged long after those other commits. Linus Walleij says: | My bad, was because the initial patch was submitted march 9th before | these fixes were merged: | http://marc.info/?l=linux-arm-kernel&m=133159655513844&w=2 | | It was pending for a while in Russell's patch tracker and I | rebased it to -rc2 without paying enough attention to recent | related scheduler fixes ... lesson learned. Signed-off-by: Russell King --- arch/arm/kernel/smp_twd.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 5b150afb995b..fef42b21cecb 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -118,14 +118,10 @@ static int twd_cpufreq_transition(struct notifier_block *nb, * The twd clock events must be reprogrammed to account for the new * frequency. The timer is local to a cpu, so cross-call to the * changing cpu. - * - * Only wait for it to finish, if the cpu is active to avoid - * deadlock when cpu1 is spinning on while(!cpu_active(cpu1)) during - * booting of that cpu. */ if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE) smp_call_function_single(freqs->cpu, twd_update_frequency, - NULL, cpu_active(freqs->cpu)); + NULL, 1); return NOTIFY_OK; } -- cgit v1.2.3 From a102962ffd45fe8bac68ea6d9f72d3ed19dc44e1 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sat, 31 Mar 2012 17:44:53 +0100 Subject: ARM: ux300: Fix unimplementable regulation constraints It doesn't make sense to grant permission to change the status of a regulator that is also set as always on and similarly it doesn't make sense to allow a driver to change the voltage of a regulator which can only be set to a single voltage. Signed-off-by: Mark Brown Signed-off-by: Linus Walleij --- arch/arm/mach-u300/i2c.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c index a38f80238ea9..cb04bd6ab3e7 100644 --- a/arch/arm/mach-u300/i2c.c +++ b/arch/arm/mach-u300/i2c.c @@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = { .min_uV = 1800000, .max_uV = 1800000, .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, .always_on = 1, .boot_on = 1, }, @@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = { .min_uV = 2500000, .max_uV = 2500000, .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, .always_on = 1, .boot_on = 1, }, @@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = { .max_uV = 1800000, .valid_modes_mask = REGULATOR_MODE_NORMAL, .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, + REGULATOR_CHANGE_VOLTAGE, .always_on = 1, .boot_on = 1, }, -- cgit v1.2.3 From 1344500e2d79d09db81f748984697cbdd6b02279 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 18 Apr 2012 15:29:58 +0200 Subject: ARM: u300: bump all IRQ numbers by one Since the VIC was converted to use generic IRQ domains IRQ 0 is silently ignored. This IRQ is used on the U300 so we're missing it now. Bump all IRQ numbers by one since they are now decoupled from the hardware IRQ numbers. Cc: Grant Likely Cc: Rob Herring Signed-off-by: Linus Walleij --- arch/arm/mach-u300/core.c | 6 +- arch/arm/mach-u300/include/mach/irqs.h | 150 ++++++++++++++++----------------- 2 files changed, 79 insertions(+), 77 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 1621ad07d284..33339745d432 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -1667,8 +1667,10 @@ void __init u300_init_irq(void) for (i = 0; i < U300_VIC_IRQS_END; i++) set_bit(i, (unsigned long *) &mask[0]); - vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]); - vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]); + vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START, + mask[0], mask[0]); + vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START, + mask[1], mask[1]); } diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h index ee78a26707eb..ec09c1e07b1a 100644 --- a/arch/arm/mach-u300/include/mach/irqs.h +++ b/arch/arm/mach-u300/include/mach/irqs.h @@ -12,101 +12,101 @@ #ifndef __MACH_IRQS_H #define __MACH_IRQS_H -#define IRQ_U300_INTCON0_START 0 -#define IRQ_U300_INTCON1_START 32 +#define IRQ_U300_INTCON0_START 1 +#define IRQ_U300_INTCON1_START 33 /* These are on INTCON0 - 30 lines */ -#define IRQ_U300_IRQ0_EXT 0 -#define IRQ_U300_IRQ1_EXT 1 -#define IRQ_U300_DMA 2 -#define IRQ_U300_VIDEO_ENC_0 3 -#define IRQ_U300_VIDEO_ENC_1 4 -#define IRQ_U300_AAIF_RX 5 -#define IRQ_U300_AAIF_TX 6 -#define IRQ_U300_AAIF_VGPIO 7 -#define IRQ_U300_AAIF_WAKEUP 8 -#define IRQ_U300_PCM_I2S0_FRAME 9 -#define IRQ_U300_PCM_I2S0_FIFO 10 -#define IRQ_U300_PCM_I2S1_FRAME 11 -#define IRQ_U300_PCM_I2S1_FIFO 12 -#define IRQ_U300_XGAM_GAMCON 13 -#define IRQ_U300_XGAM_CDI 14 -#define IRQ_U300_XGAM_CDICON 15 +#define IRQ_U300_IRQ0_EXT 1 +#define IRQ_U300_IRQ1_EXT 2 +#define IRQ_U300_DMA 3 +#define IRQ_U300_VIDEO_ENC_0 4 +#define IRQ_U300_VIDEO_ENC_1 5 +#define IRQ_U300_AAIF_RX 6 +#define IRQ_U300_AAIF_TX 7 +#define IRQ_U300_AAIF_VGPIO 8 +#define IRQ_U300_AAIF_WAKEUP 9 +#define IRQ_U300_PCM_I2S0_FRAME 10 +#define IRQ_U300_PCM_I2S0_FIFO 11 +#define IRQ_U300_PCM_I2S1_FRAME 12 +#define IRQ_U300_PCM_I2S1_FIFO 13 +#define IRQ_U300_XGAM_GAMCON 14 +#define IRQ_U300_XGAM_CDI 15 +#define IRQ_U300_XGAM_CDICON 16 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) /* MMIACC not used on the DB3210 or DB3350 chips */ -#define IRQ_U300_XGAM_MMIACC 16 +#define IRQ_U300_XGAM_MMIACC 17 #endif -#define IRQ_U300_XGAM_PDI 17 -#define IRQ_U300_XGAM_PDICON 18 -#define IRQ_U300_XGAM_GAMEACC 19 -#define IRQ_U300_XGAM_MCIDCT 20 -#define IRQ_U300_APEX 21 -#define IRQ_U300_UART0 22 -#define IRQ_U300_SPI 23 -#define IRQ_U300_TIMER_APP_OS 24 -#define IRQ_U300_TIMER_APP_DD 25 -#define IRQ_U300_TIMER_APP_GP1 26 -#define IRQ_U300_TIMER_APP_GP2 27 -#define IRQ_U300_TIMER_OS 28 -#define IRQ_U300_TIMER_MS 29 -#define IRQ_U300_KEYPAD_KEYBF 30 -#define IRQ_U300_KEYPAD_KEYBR 31 +#define IRQ_U300_XGAM_PDI 18 +#define IRQ_U300_XGAM_PDICON 19 +#define IRQ_U300_XGAM_GAMEACC 20 +#define IRQ_U300_XGAM_MCIDCT 21 +#define IRQ_U300_APEX 22 +#define IRQ_U300_UART0 23 +#define IRQ_U300_SPI 24 +#define IRQ_U300_TIMER_APP_OS 25 +#define IRQ_U300_TIMER_APP_DD 26 +#define IRQ_U300_TIMER_APP_GP1 27 +#define IRQ_U300_TIMER_APP_GP2 28 +#define IRQ_U300_TIMER_OS 29 +#define IRQ_U300_TIMER_MS 30 +#define IRQ_U300_KEYPAD_KEYBF 31 +#define IRQ_U300_KEYPAD_KEYBR 32 /* These are on INTCON1 - 32 lines */ -#define IRQ_U300_GPIO_PORT0 32 -#define IRQ_U300_GPIO_PORT1 33 -#define IRQ_U300_GPIO_PORT2 34 +#define IRQ_U300_GPIO_PORT0 33 +#define IRQ_U300_GPIO_PORT1 34 +#define IRQ_U300_GPIO_PORT2 35 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \ defined(CONFIG_MACH_U300_BS335) /* These are for DB3150, DB3200 and DB3350 */ -#define IRQ_U300_WDOG 35 -#define IRQ_U300_EVHIST 36 -#define IRQ_U300_MSPRO 37 -#define IRQ_U300_MMCSD_MCIINTR0 38 -#define IRQ_U300_MMCSD_MCIINTR1 39 -#define IRQ_U300_I2C0 40 -#define IRQ_U300_I2C1 41 -#define IRQ_U300_RTC 42 -#define IRQ_U300_NFIF 43 -#define IRQ_U300_NFIF2 44 +#define IRQ_U300_WDOG 36 +#define IRQ_U300_EVHIST 37 +#define IRQ_U300_MSPRO 38 +#define IRQ_U300_MMCSD_MCIINTR0 39 +#define IRQ_U300_MMCSD_MCIINTR1 40 +#define IRQ_U300_I2C0 41 +#define IRQ_U300_I2C1 42 +#define IRQ_U300_RTC 43 +#define IRQ_U300_NFIF 44 +#define IRQ_U300_NFIF2 45 #endif /* DB3150 and DB3200 have only 45 IRQs */ #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) -#define U300_VIC_IRQS_END 45 +#define U300_VIC_IRQS_END 46 #endif /* The DB3350-specific interrupt lines */ #ifdef CONFIG_MACH_U300_BS335 -#define IRQ_U300_ISP_F0 45 -#define IRQ_U300_ISP_F1 46 -#define IRQ_U300_ISP_F2 47 -#define IRQ_U300_ISP_F3 48 -#define IRQ_U300_ISP_F4 49 -#define IRQ_U300_GPIO_PORT3 50 -#define IRQ_U300_SYSCON_PLL_LOCK 51 -#define IRQ_U300_UART1 52 -#define IRQ_U300_GPIO_PORT4 53 -#define IRQ_U300_GPIO_PORT5 54 -#define IRQ_U300_GPIO_PORT6 55 -#define U300_VIC_IRQS_END 56 +#define IRQ_U300_ISP_F0 46 +#define IRQ_U300_ISP_F1 47 +#define IRQ_U300_ISP_F2 48 +#define IRQ_U300_ISP_F3 49 +#define IRQ_U300_ISP_F4 50 +#define IRQ_U300_GPIO_PORT3 51 +#define IRQ_U300_SYSCON_PLL_LOCK 52 +#define IRQ_U300_UART1 53 +#define IRQ_U300_GPIO_PORT4 54 +#define IRQ_U300_GPIO_PORT5 55 +#define IRQ_U300_GPIO_PORT6 56 +#define U300_VIC_IRQS_END 57 #endif /* The DB3210-specific interrupt lines */ #ifdef CONFIG_MACH_U300_BS365 -#define IRQ_U300_GPIO_PORT3 35 -#define IRQ_U300_GPIO_PORT4 36 -#define IRQ_U300_WDOG 37 -#define IRQ_U300_EVHIST 38 -#define IRQ_U300_MSPRO 39 -#define IRQ_U300_MMCSD_MCIINTR0 40 -#define IRQ_U300_MMCSD_MCIINTR1 41 -#define IRQ_U300_I2C0 42 -#define IRQ_U300_I2C1 43 -#define IRQ_U300_RTC 44 -#define IRQ_U300_NFIF 45 -#define IRQ_U300_NFIF2 46 -#define IRQ_U300_SYSCON_PLL_LOCK 47 -#define U300_VIC_IRQS_END 48 +#define IRQ_U300_GPIO_PORT3 36 +#define IRQ_U300_GPIO_PORT4 37 +#define IRQ_U300_WDOG 38 +#define IRQ_U300_EVHIST 39 +#define IRQ_U300_MSPRO 40 +#define IRQ_U300_MMCSD_MCIINTR0 41 +#define IRQ_U300_MMCSD_MCIINTR1 42 +#define IRQ_U300_I2C0 43 +#define IRQ_U300_I2C1 44 +#define IRQ_U300_RTC 45 +#define IRQ_U300_NFIF 46 +#define IRQ_U300_NFIF2 47 +#define IRQ_U300_SYSCON_PLL_LOCK 48 +#define U300_VIC_IRQS_END 49 #endif /* Maximum 8*7 GPIO lines */ @@ -117,6 +117,6 @@ #define IRQ_U300_GPIO_END (U300_VIC_IRQS_END) #endif -#define NR_IRQS (IRQ_U300_GPIO_END) +#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START) #endif -- cgit v1.2.3 From 8482c81c770960d7c0dc991a781cbd4afa7ea4cc Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sat, 14 Apr 2012 08:04:46 -0700 Subject: ARM: EXYNOS: use 'exynos4-sdhci' as device name for sdhci controllers With the addition of platform specific driver data in the sdhci driver for EXYNOS4 and EXYNOS5, the device name of sdhci controllers on EXYNOS4 and EXYNOS5 are changed accordingly. Signed-off-by: Thomas Abraham [kgene.kim@samsung.com: re-worked on top of v3.4-rc2] Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/clock-exynos4.c | 24 ++++++++++++------------ arch/arm/mach-exynos/clock-exynos5.c | 24 ++++++++++++------------ arch/arm/mach-exynos/common.c | 10 ++++++++++ arch/arm/plat-samsung/include/plat/sdhci.h | 28 ++++++++++++++++++++++++++++ 4 files changed, 62 insertions(+), 24 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index df54c2a92225..6efd1e5919fd 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = { .ctrlbit = (1 << 3), }, { .name = "hsmmc", - .devname = "s3c-sdhci.0", + .devname = "exynos4-sdhci.0", .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 5), }, { .name = "hsmmc", - .devname = "s3c-sdhci.1", + .devname = "exynos4-sdhci.1", .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 6), }, { .name = "hsmmc", - .devname = "s3c-sdhci.2", + .devname = "exynos4-sdhci.2", .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 7), }, { .name = "hsmmc", - .devname = "s3c-sdhci.3", + .devname = "exynos4-sdhci.3", .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 8), @@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = { static struct clksrc_clk exynos4_clk_sclk_mmc0 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.0", + .devname = "exynos4-sdhci.0", .parent = &exynos4_clk_dout_mmc0.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 0), @@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = { static struct clksrc_clk exynos4_clk_sclk_mmc1 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.1", + .devname = "exynos4-sdhci.1", .parent = &exynos4_clk_dout_mmc1.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 4), @@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = { static struct clksrc_clk exynos4_clk_sclk_mmc2 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.2", + .devname = "exynos4-sdhci.2", .parent = &exynos4_clk_dout_mmc2.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 8), @@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = { static struct clksrc_clk exynos4_clk_sclk_mmc3 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.3", + .devname = "exynos4-sdhci.3", .parent = &exynos4_clk_dout_mmc3.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 12), @@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk), CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk), CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk), - CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), - CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), - CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index d013982d0f8e..5cd7a8b8868c 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = { .ctrlbit = (1 << 20), }, { .name = "hsmmc", - .devname = "s3c-sdhci.0", + .devname = "exynos4-sdhci.0", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 12), }, { .name = "hsmmc", - .devname = "s3c-sdhci.1", + .devname = "exynos4-sdhci.1", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 13), }, { .name = "hsmmc", - .devname = "s3c-sdhci.2", + .devname = "exynos4-sdhci.2", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 14), }, { .name = "hsmmc", - .devname = "s3c-sdhci.3", + .devname = "exynos4-sdhci.3", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 15), @@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = { static struct clksrc_clk exynos5_clk_sclk_mmc0 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.0", + .devname = "exynos4-sdhci.0", .parent = &exynos5_clk_dout_mmc0.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 0), @@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = { static struct clksrc_clk exynos5_clk_sclk_mmc1 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.1", + .devname = "exynos4-sdhci.1", .parent = &exynos5_clk_dout_mmc1.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 4), @@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = { static struct clksrc_clk exynos5_clk_sclk_mmc2 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.2", + .devname = "exynos4-sdhci.2", .parent = &exynos5_clk_dout_mmc2.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 8), @@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = { static struct clksrc_clk exynos5_clk_sclk_mmc3 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.3", + .devname = "exynos4-sdhci.3", .parent = &exynos5_clk_dout_mmc3.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 12), @@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = { CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk), CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk), CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk), - CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk), - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), - CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), - CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk), + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 8614aab47cc0..b5e7f00da589 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -326,6 +326,11 @@ static void __init exynos4_map_io(void) s3c_fimc_setname(2, "exynos4-fimc"); s3c_fimc_setname(3, "exynos4-fimc"); + s3c_sdhci_setname(0, "exynos4-sdhci"); + s3c_sdhci_setname(1, "exynos4-sdhci"); + s3c_sdhci_setname(2, "exynos4-sdhci"); + s3c_sdhci_setname(3, "exynos4-sdhci"); + /* The I2C bus controllers are directly compatible with s3c2440 */ s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); @@ -344,6 +349,11 @@ static void __init exynos5_map_io(void) s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC; s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC; + s3c_sdhci_setname(0, "exynos4-sdhci"); + s3c_sdhci_setname(1, "exynos4-sdhci"); + s3c_sdhci_setname(2, "exynos4-sdhci"); + s3c_sdhci_setname(3, "exynos4-sdhci"); + /* The I2C bus controllers are directly compatible with s3c2440 */ s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 317e246ffc56..e834c5ef437c 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -18,6 +18,8 @@ #ifndef __PLAT_S3C_SDHCI_H #define __PLAT_S3C_SDHCI_H __FILE__ +#include + struct platform_device; struct mmc_host; struct mmc_card; @@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { } #endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ +static inline void s3c_sdhci_setname(int id, char *name) +{ + switch (id) { +#ifdef CONFIG_S3C_DEV_HSMMC + case 0: + s3c_device_hsmmc0.name = name; + break; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 + case 1: + s3c_device_hsmmc1.name = name; + break; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + case 2: + s3c_device_hsmmc2.name = name; + break; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + case 3: + s3c_device_hsmmc3.name = name; + break; +#endif + } +} + #endif /* __PLAT_S3C_SDHCI_H */ -- cgit v1.2.3 From 5699b0ca05f781d496d20ba87f916bd9eec7ea6a Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 20 Apr 2012 17:26:23 -0700 Subject: ARM: EXYNOS: Fix incorrect initialization of GIC Use the of_irq_init() call to setup the gic which also properly registers the gic device node pointer with gic irq domain, without which all interrupt specifier translations for gic fail. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index b5e7f00da589..6c0e4f54c94d 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -547,7 +547,7 @@ void __init exynos5_init_irq(void) { int irq; - gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); + of_irq_init(exynos4_dt_irq_match); for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) { combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), -- cgit v1.2.3 From 2b7b9a7d6c676691cd746a654e2c3b06a6feb9ba Mon Sep 17 00:00:00 2001 From: David Brown Date: Mon, 23 Apr 2012 15:34:20 -0700 Subject: ARM: msm: Fix gic irqdomain support As of commit 75294957be1dee7d22dd7d90bd31334ba410e836 Author: Grant Likely Date: Tue Feb 14 14:06:57 2012 -0700 irq_domain: Remove 'new' irq_domain in favour of the ppc one the ARM gic controller uses proper irq domains. Fix the MSM gic initialization and DT so that it works again. Signed-off-by: David Brown Acked-by: Grant Likely --- arch/arm/boot/dts/msm8660-surf.dts | 4 ++-- arch/arm/mach-msm/board-msm8x60.c | 25 +++++++++++++++---------- 2 files changed, 17 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index 15ded0deaa79..45bc4bb04e57 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts @@ -10,7 +10,7 @@ intc: interrupt-controller@02080000 { compatible = "qcom,msm-8660-qgic"; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <3>; reg = < 0x02080000 0x1000 >, < 0x02081000 0x1000 >; }; @@ -19,6 +19,6 @@ compatible = "qcom,msm-hsuart", "qcom,msm-uart"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; - interrupts = <195>; + interrupts = <0 195 0x0>; }; }; diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index 962e71169750..fb3496a52ef4 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void) msm_map_msm8x60_io(); } +#ifdef CONFIG_OF +static struct of_device_id msm_dt_gic_match[] __initdata = { + { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init }, + {} +}; +#endif + static void __init msm8x60_init_irq(void) { - gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, - (void *)MSM_QGIC_CPU_BASE); + if (!of_have_populated_dt()) + gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, + (void *)MSM_QGIC_CPU_BASE); +#ifdef CONFIG_OF + else + of_irq_init(msm_dt_gic_match); +#endif /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); @@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = { {} }; -static struct of_device_id msm_dt_gic_match[] __initdata = { - { .compatible = "qcom,msm-8660-qgic", }, - {} -}; - static void __init msm8x60_dt_init(void) { - irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS, - GIC_SPI_START); - if (of_machine_is_compatible("qcom,msm8660-surf")) { printk(KERN_INFO "Init surf UART registers\n"); msm8x60_init_uart12dm(); -- cgit v1.2.3 From 18ea1fcd7ef19e496c523d814d52261cc4777f51 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 21 Apr 2012 06:57:29 -0700 Subject: ARM: mini2440_defconfig: Fix build error This is needed to fix mini2440_defconfig after the platform files have been moved around. arm-none-linux-gnueabi-ld: no machine record defined arm-none-linux-gnueabi-ld: no machine record defined arm-none-linux-gnueabi-ld: no machine record defined make: *** [.tmp_vmlinux1] Error 1 Signed-off-by: Arnd Bergmann Signed-off-by: Kukjin Kim --- arch/arm/configs/mini2440_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index 42da9183acc8..082175c54e7c 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_BLK_DEV_INTEGRITY=y CONFIG_ARCH_S3C24XX=y +# CONFIG_CPU_S3C2410 is not set +CONFIG_CPU_S3C2440=y CONFIG_S3C_ADC=y CONFIG_S3C24XX_PWM=y CONFIG_MACH_MINI2440=y -- cgit v1.2.3 From 7518dde92c27f845a685cdc559c83c666cc01840 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Sat, 21 Apr 2012 07:55:33 -0700 Subject: ARM: S3C24XX: Fix build warning for S3C2410_PM warning: (CPU_S3C2440 && CPU_S3C2442) selects S3C2410_PM which has unmet direct dependencies (ARCH_S3C24XX && CPU_S3C2410) warning: (CPU_S3C2440 && CPU_S3C2442) selects S3C2410_PM which has unmet direct dependencies (ARCH_S3C24XX && CPU_S3C2410) Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c24xx/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 0f3a327ebcaa..b34287ab5afd 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS help Compile in platform device definition for Samsung TouchScreen. -# cpu-specific sections - -if CPU_S3C2410 - config S3C2410_DMA bool depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442) @@ -127,6 +123,10 @@ config S3C2410_PM help Power Management code common to S3C2410 and better +# cpu-specific sections + +if CPU_S3C2410 + config S3C24XX_SIMTEC_NOR bool help -- cgit v1.2.3 From ffabec4ef7ad6ca9365d39f643b8a24c0fce04e7 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Sat, 21 Apr 2012 08:31:38 -0700 Subject: ARM: EXYNOS: Fix resource on dev-dwmci.c Should be EXYNOS4_IRQ_DWMCI instead of IRQ_DWMCI, and use DEFINE_RES_{MEM,IRQ}. Reported-by: Jaehoon Chung Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/dev-dwmci.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/dev-dwmci.c b/arch/arm/mach-exynos/dev-dwmci.c index b025db4bf602..79035018fb74 100644 --- a/arch/arm/mach-exynos/dev-dwmci.c +++ b/arch/arm/mach-exynos/dev-dwmci.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data) } static struct resource exynos4_dwmci_resource[] = { - [0] = { - .start = EXYNOS4_PA_DWMCI, - .end = EXYNOS4_PA_DWMCI + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_DWMCI, - .end = IRQ_DWMCI, - .flags = IORESOURCE_IRQ, - } + [0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K), + [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI), }; static struct dw_mci_board exynos4_dwci_pdata = { -- cgit v1.2.3 From 6fff5a11fd07d7f918ac3737da4846558518c31d Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Tue, 24 Apr 2012 13:25:01 -0700 Subject: ARM: EXYNOS: Fix compilation error when CONFIG_OF is not defined Fixed following compile time error. arch/arm/mach-exynos/common.c: In function 'exynos5_init_irq': arch/arm/mach-exynos/common.c:539:2: error: implicit declaration of function 'of_irq_init' arch/arm/mach-exynos/common.c:539:14: error: 'exynos4_dt_irq_match' undeclared (first use in this function) arch/arm/mach-exynos/common.c:539:14: note: each undeclared identifier is reported only once for each function it appears in Cc: Thomas Abraham Signed-off-by: Tushar Behera Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/common.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 6c0e4f54c94d..5ccd6e80a607 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -547,7 +547,9 @@ void __init exynos5_init_irq(void) { int irq; +#ifdef CONFIG_OF of_irq_init(exynos4_dt_irq_match); +#endif for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) { combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), -- cgit v1.2.3 From 9b4d1cbb1391ae603c20cbf8c0beb66e38397196 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 24 Apr 2012 17:28:12 -0700 Subject: ARM: SAMSUNG: add missing MMC_CAP2_BROKEN_VOLTAGE capability Commit 6e8201f57c935 "mmc: core: add the capability for broken voltage" introduced a new quirk to indicate that MMC core should ignore voltage change errors reported by the regulators core. This is required to get SDHCI working on UniversalC210, NURI and GONI boards again after commit ceb6143b2df81c ("mmc: sdhci: fix vmmc handling"). Signed-off-by: Marek Szyprowski Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/mach-nuri.c | 1 + arch/arm/mach-exynos/mach-universal_c210.c | 1 + arch/arm/mach-s5pv210/mach-goni.c | 2 ++ 3 files changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index b4f1f902ce6d..ed90aef404c3 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c @@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = { .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_ERASE), + .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE, .cd_type = S3C_SDHCI_CD_PERMANENT, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index 7ebf79c2ab34..cb2b027f09a6 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c @@ -747,6 +747,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = { .max_width = 8, .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), + .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE, .cd_type = S3C_SDHCI_CD_PERMANENT, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index a8933de3d627..32395664e879 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -765,6 +766,7 @@ static void __init goni_pmic_init(void) /* MoviNAND */ static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = { .max_width = 4, + .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE, .cd_type = S3C_SDHCI_CD_PERMANENT, }; -- cgit v1.2.3 From db7b122cf5f769046d410f82a1e9fe7006ed955a Mon Sep 17 00:00:00 2001 From: Vasiliy Kulikov Date: Wed, 25 Apr 2012 16:01:51 -0700 Subject: arch/arm/mach-ux500/mbox-db5500.c: world-writable sysfs fifo file Don't allow everybody to use a modem. Signed-off-by: Vasiliy Kulikov Cc: Srinidhi Kasagar Acked-by: Linus Walleij Cc: Russell King Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/arm/mach-ux500/mbox-db5500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/mbox-db5500.c b/arch/arm/mach-ux500/mbox-db5500.c index 2b2d51caf9d8..0127490218cd 100644 --- a/arch/arm/mach-ux500/mbox-db5500.c +++ b/arch/arm/mach-ux500/mbox-db5500.c @@ -168,7 +168,7 @@ static ssize_t mbox_read_fifo(struct device *dev, return sprintf(buf, "0x%X\n", mbox_value); } -static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo); +static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo); static int mbox_show(struct seq_file *s, void *data) { -- cgit v1.2.3 From b95ace54a23e2f8ebb032744cebb17c9f43bf651 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sun, 22 Apr 2012 13:37:24 +0200 Subject: ARM: pxa: fix gpio wakeup setting In 3.3, gpio wakeup setting was broken. The call enable_irq_wake() didn't set up the PXA gpio registers (PWER, ...) anymore. Fix it at least for pxa27x. The driver doesn't seem to be used in pxa25x (weird ...), and the fix doesn't extend to pxa3xx and pxa95x (which don't have a gpio_set_wake() available). Signed-off-by: Robert Jarzmik Signed-off-by: Haojian Zhuang --- arch/arm/mach-pxa/pxa27x.c | 6 +++++- drivers/gpio/gpio-pxa.c | 21 +++++++++++++++++++-- include/linux/gpio-pxa.h | 4 ++++ 3 files changed, 28 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 6bce78edce7a..4726c246dcdc 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) pxa_register_device(&pxa27x_device_i2c_power, info); } +static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = { + .gpio_set_wake = gpio_set_wake, +}; + static struct platform_device *devices[] __initdata = { - &pxa_device_gpio, &pxa27x_device_udc, &pxa_device_pmu, &pxa_device_i2s, @@ -458,6 +461,7 @@ static int __init pxa27x_init(void) register_syscore_ops(&pxa2xx_mfp_syscore_ops); register_syscore_ops(&pxa2xx_clock_syscore_ops); + pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index 5689ce62fd81..fc3ace3fd4cb 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c @@ -64,6 +64,7 @@ struct pxa_gpio_chip { unsigned long irq_mask; unsigned long irq_edge_rise; unsigned long irq_edge_fall; + int (*set_wake)(unsigned int gpio, unsigned int on); #ifdef CONFIG_PM unsigned long saved_gplr; @@ -269,7 +270,8 @@ static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) (value ? GPSR_OFFSET : GPCR_OFFSET)); } -static int __devinit pxa_init_gpio_chip(int gpio_end) +static int __devinit pxa_init_gpio_chip(int gpio_end, + int (*set_wake)(unsigned int, unsigned int)) { int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; struct pxa_gpio_chip *chips; @@ -285,6 +287,7 @@ static int __devinit pxa_init_gpio_chip(int gpio_end) sprintf(chips[i].label, "gpio-%d", i); chips[i].regbase = gpio_reg_base + BANK_OFF(i); + chips[i].set_wake = set_wake; c->base = gpio; c->label = chips[i].label; @@ -412,6 +415,17 @@ static void pxa_mask_muxed_gpio(struct irq_data *d) writel_relaxed(gfer, c->regbase + GFER_OFFSET); } +static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) +{ + int gpio = pxa_irq_to_gpio(d->irq); + struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); + + if (c->set_wake) + return c->set_wake(gpio, on); + else + return 0; +} + static void pxa_unmask_muxed_gpio(struct irq_data *d) { int gpio = pxa_irq_to_gpio(d->irq); @@ -427,6 +441,7 @@ static struct irq_chip pxa_muxed_gpio_chip = { .irq_mask = pxa_mask_muxed_gpio, .irq_unmask = pxa_unmask_muxed_gpio, .irq_set_type = pxa_gpio_irq_type, + .irq_set_wake = pxa_gpio_set_wake, }; static int pxa_gpio_nums(void) @@ -471,6 +486,7 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev) struct pxa_gpio_chip *c; struct resource *res; struct clk *clk; + struct pxa_gpio_platform_data *info; int gpio, irq, ret; int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; @@ -516,7 +532,8 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev) } /* Initialize GPIO chips */ - pxa_init_gpio_chip(pxa_last_gpio); + info = dev_get_platdata(&pdev->dev); + pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL); /* clear all GPIO edge detects */ for_each_gpio_chip(gpio, c) { diff --git a/include/linux/gpio-pxa.h b/include/linux/gpio-pxa.h index 05071ee34c3f..d755b28ba635 100644 --- a/include/linux/gpio-pxa.h +++ b/include/linux/gpio-pxa.h @@ -13,4 +13,8 @@ extern int pxa_last_gpio; extern int pxa_irq_to_gpio(int irq); +struct pxa_gpio_platform_data { + int (*gpio_set_wake)(unsigned int gpio, unsigned int on); +}; + #endif /* __GPIO_PXA_H */ -- cgit v1.2.3 From 9f9d27e3f3317f39c91c286b6184f1ca05452968 Mon Sep 17 00:00:00 2001 From: Dmitry Artamonow Date: Sat, 14 Apr 2012 10:26:19 +0400 Subject: arm/sa1100: fix sa1100-rtc memory resource DEFINE_RES_MEM() takes the size of resource as a second argument, not the end address. Passing end address leads to following error in runtime during device registration: sa1100-rtc: failed to claim resource 0 Fix it. Signed-off-by: Dmitry Artamonow Signed-off-by: Haojian Zhuang --- arch/arm/mach-sa1100/generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 7c524b4e415d..16be4c56abe3 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda) } static struct resource sa1100_rtc_resources[] = { - DEFINE_RES_MEM(0x90010000, 0x9001003f), + DEFINE_RES_MEM(0x90010000, 0x40), DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"), DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"), }; -- cgit v1.2.3 From a13b878780ea98d8415203c4502a8fc5bc614656 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Thu, 12 Apr 2012 15:43:28 +0300 Subject: ARM: PXA2xx: MFP: fix bug with MFP_LPM_KEEP_OUTPUT Pins that have MFP_LPM_KEEP_OUTPUT set and are configured for output must retain the output state in low power mode. Currently, the pin direction configuration is overrided with values in gpdr_lpm[] array and do not obey the MFP_LPM_KEEP_OUTPUT setting. Fix the above bug and add some documentation to clarify the MFP_LPM_KEEP_OUTPUT setting purpose. Reported-by: Paul Parsons Signed-off-by: Igor Grinberg Tested-by: Paul Parsons Signed-off-by: Haojian Zhuang --- arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h | 7 +++++++ arch/arm/mach-pxa/mfp-pxa2xx.c | 12 ++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h index c54cef25895c..cbf51ae81855 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h @@ -17,6 +17,7 @@ * * bit 23 - Input/Output (PXA2xx specific) * bit 24 - Wakeup Enable(PXA2xx specific) + * bit 25 - Keep Output (PXA2xx specific) */ #define MFP_DIR_IN (0x0 << 23) @@ -25,6 +26,12 @@ #define MFP_DIR(x) (((x) >> 23) & 0x1) #define MFP_LPM_CAN_WAKEUP (0x1 << 24) + +/* + * MFP_LPM_KEEP_OUTPUT must be specified for pins that need to + * retain their last output level (low or high). + * Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input. + */ #define MFP_LPM_KEEP_OUTPUT (0x1 << 25) #define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index b0a842887780..d2373d79b657 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -366,14 +366,22 @@ static int pxa2xx_mfp_suspend(void) } for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { - saved_gafr[0][i] = GAFR_L(i); saved_gafr[1][i] = GAFR_U(i); saved_gpdr[i] = GPDR(i * 32); saved_pgsr[i] = PGSR(i); + } - GPDR(i * 32) = gpdr_lpm[i]; + /* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */ + for (i = 0; i < pxa_last_gpio; i++) { + if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) || + ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) && + (saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i)))) + GPDR(i) |= GPIO_bit(i); + else + GPDR(i) &= ~GPIO_bit(i); } + return 0; } -- cgit v1.2.3 From ef7c7c693b4b05a293678fd40ed1511bc94d6f61 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Thu, 12 Apr 2012 15:43:29 +0300 Subject: ARM: PXA2xx: MFP: fix potential direction bug Pins configured as input and have MFP_LPM_DRIVE_* flag set, can have a wrong output value for some period of time (spike) during the suspend sequence. This can happen because the direction of the pins (GPDR) is set by software and the output level is set by hardware (PGSR) at a later stage. Fix the above potential bug by setting the output levels first. Also save the actual levels of the pins before the suspend and restore them after the resume, but before the direction settings take place, so the same bug as described above will not happen in the resume sequence. Reported-by: Paul Parsons Signed-off-by: Igor Grinberg Tested-by: Paul Parsons Signed-off-by: Haojian Zhuang --- arch/arm/mach-pxa/mfp-pxa2xx.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index d2373d79b657..ef0426a159d4 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -33,6 +33,8 @@ #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) #define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5)) #define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c) +#define GPSR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18) +#define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24) #define PWER_WE35 (1 << 24) @@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {} #ifdef CONFIG_PM static unsigned long saved_gafr[2][4]; static unsigned long saved_gpdr[4]; +static unsigned long saved_gplr[4]; static unsigned long saved_pgsr[4]; static int pxa2xx_mfp_suspend(void) @@ -369,7 +372,11 @@ static int pxa2xx_mfp_suspend(void) saved_gafr[0][i] = GAFR_L(i); saved_gafr[1][i] = GAFR_U(i); saved_gpdr[i] = GPDR(i * 32); + saved_gplr[i] = GPLR(i * 32); saved_pgsr[i] = PGSR(i); + + GPSR(i * 32) = PGSR(i); + GPCR(i * 32) = ~PGSR(i); } /* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */ @@ -392,6 +399,8 @@ static void pxa2xx_mfp_resume(void) for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { GAFR_L(i) = saved_gafr[0][i]; GAFR_U(i) = saved_gafr[1][i]; + GPSR(i * 32) = saved_gplr[i]; + GPCR(i * 32) = ~saved_gplr[i]; GPDR(i * 32) = saved_gpdr[i]; PGSR(i) = saved_pgsr[i]; } -- cgit v1.2.3 From 53c50ef508cc7b47c8b912549d4e2593fd0e5049 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Thu, 19 Apr 2012 18:22:16 +0800 Subject: ARM: mmp: fix build issue on mmp with device tree Since irq_domain_add_simple() is removed, remove it in mmp-dt.c also. Signed-off-by: Haojian Zhuang Acked-by: Arnd Bergmann --- arch/arm/mach-mmp/mmp-dt.c | 22 ---------------------- 1 file changed, 22 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c index 67075395e400..ca22e3c04e90 100644 --- a/arch/arm/mach-mmp/mmp-dt.c +++ b/arch/arm/mach-mmp/mmp-dt.c @@ -32,31 +32,9 @@ static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = { {} }; -static int __init mmp_intc_add_irq_domain(struct device_node *np, - struct device_node *parent) -{ - irq_domain_add_simple(np, 0); - return 0; -} - -static int __init mmp_gpio_add_irq_domain(struct device_node *np, - struct device_node *parent) -{ - irq_domain_add_simple(np, IRQ_GPIO_START); - return 0; -} - -static const struct of_device_id mmp_irq_match[] __initconst = { - { .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, }, - { .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, }, - {} -}; - static void __init mmp_dt_init(void) { - of_irq_init(mmp_irq_match); - of_platform_populate(NULL, of_default_bus_match_table, mmp_auxdata_lookup, NULL); } -- cgit v1.2.3 From 3f4dd3224df9664a44bf05df56c7c12622f7a1c7 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Tue, 10 Apr 2012 15:12:45 +0800 Subject: ARM: mmp: append CONFIG_MACH_MMP2_DT Append CONFIG_MACH_MMP2_DT. CONFIG_MACH_MMP_DT is used to ARMv5 DT support. CONFIG_MACH_MMP2_DT is used to ARMv7 DT support. These two machine support can't be selected at the same time. Signed-off-by: Haojian Zhuang Acked-by: Arnd Bergmann --- arch/arm/mach-mmp/Kconfig | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index 5a90b9a3ab6e..ede721628150 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -2,16 +2,6 @@ if ARCH_MMP menu "Marvell PXA168/910/MMP2 Implmentations" -config MACH_MMP_DT - bool "Support MMP2 platforms from device tree" - select CPU_PXA168 - select CPU_PXA910 - select USE_OF - help - Include support for Marvell MMP2 based platforms using - the device tree. Needn't select any other machine while - MACH_MMP_DT is enabled. - config MACH_ASPENITE bool "Marvell's PXA168 Aspenite Development Board" select CPU_PXA168 @@ -94,6 +84,25 @@ config MACH_GPLUGD Say 'Y' here if you want to support the Marvell PXA168-based GuruPlug Display (gplugD) Board +config MACH_MMP_DT + bool "Support MMP (ARMv5) platforms from device tree" + select CPU_PXA168 + select CPU_PXA910 + select USE_OF + help + Include support for Marvell MMP2 based platforms using + the device tree. Needn't select any other machine while + MACH_MMP_DT is enabled. + +config MACH_MMP2_DT + bool "Support MMP2 (ARMv7) platforms from device tree" + depends on !CPU_MOHAWK + select CPU_MMP2 + select USE_OF + help + Include support for Marvell MMP2 based platforms using + the device tree. + endmenu config CPU_PXA168 -- cgit v1.2.3 From c24b31147a0615abd6f15c9e2b6349191860db35 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Thu, 12 Apr 2012 19:02:02 +0800 Subject: ARM: mmp: support DT in irq Merge irq-pxa168 and irq-mmp2. And support device tree also. Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, base irq starts from NR_IRQS_LEGACY. Signed-off-by: Haojian Zhuang Acked-by: Arnd Bergmann --- arch/arm/Kconfig | 1 + arch/arm/mach-mmp/Makefile | 8 +- arch/arm/mach-mmp/include/mach/entry-macro.S | 4 +- arch/arm/mach-mmp/include/mach/irqs.h | 27 +- arch/arm/mach-mmp/irq-mmp2.c | 158 ---------- arch/arm/mach-mmp/irq-pxa168.c | 54 ---- arch/arm/mach-mmp/irq.c | 445 +++++++++++++++++++++++++++ 7 files changed, 472 insertions(+), 225 deletions(-) delete mode 100644 arch/arm/mach-mmp/irq-mmp2.c delete mode 100644 arch/arm/mach-mmp/irq-pxa168.c create mode 100644 arch/arm/mach-mmp/irq.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cf006d40342c..4cf9d4280972 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -632,6 +632,7 @@ config ARCH_MMP select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select GPIO_PXA + select IRQ_DOMAIN select TICK_ONESHOT select PLAT_PXA select SPARSE_IRQ diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 4fc0ff5dc96d..77f63c12e0ba 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -2,12 +2,12 @@ # Makefile for Marvell's PXA168 processors line # -obj-y += common.o clock.o devices.o time.o +obj-y += common.o clock.o devices.o time.o irq.o # SoC support -obj-$(CONFIG_CPU_PXA168) += pxa168.o irq-pxa168.o -obj-$(CONFIG_CPU_PXA910) += pxa910.o irq-pxa168.o -obj-$(CONFIG_CPU_MMP2) += mmp2.o irq-mmp2.o sram.o +obj-$(CONFIG_CPU_PXA168) += pxa168.o +obj-$(CONFIG_CPU_PXA910) += pxa910.o +obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o # board support obj-$(CONFIG_MACH_ASPENITE) += aspenite.o diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S index 9cff9e7a2b26..bd152e24e6d7 100644 --- a/arch/arm/mach-mmp/include/mach/entry-macro.S +++ b/arch/arm/mach-mmp/include/mach/entry-macro.S @@ -6,13 +6,15 @@ * published by the Free Software Foundation. */ +#include #include .macro get_irqnr_preamble, base, tmp mrc p15, 0, \tmp, c0, c0, 0 @ CPUID and \tmp, \tmp, #0xff00 cmp \tmp, #0x5800 - ldr \base, =ICU_VIRT_BASE + ldr \base, =mmp_icu_base + ldr \base, [\base, #0] addne \base, \base, #0x10c @ PJ1 AP INT SEL register addeq \base, \base, #0x104 @ PJ4 IRQ SEL register .endm diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h index d0e746626a3d..fb492a50a817 100644 --- a/arch/arm/mach-mmp/include/mach/irqs.h +++ b/arch/arm/mach-mmp/include/mach/irqs.h @@ -125,7 +125,7 @@ #define IRQ_MMP2_RTC_MUX 5 #define IRQ_MMP2_TWSI1 7 #define IRQ_MMP2_GPU 8 -#define IRQ_MMP2_KEYPAD 9 +#define IRQ_MMP2_KEYPAD_MUX 9 #define IRQ_MMP2_ROTARY 10 #define IRQ_MMP2_TRACKBALL 11 #define IRQ_MMP2_ONEWIRE 12 @@ -163,11 +163,11 @@ #define IRQ_MMP2_DMA_FIQ 47 #define IRQ_MMP2_DMA_RIQ 48 #define IRQ_MMP2_GPIO 49 -#define IRQ_MMP2_SSP_MUX 51 +#define IRQ_MMP2_MIPI_HSI1_MUX 51 #define IRQ_MMP2_MMC2 52 #define IRQ_MMP2_MMC3 53 #define IRQ_MMP2_MMC4 54 -#define IRQ_MMP2_MIPI_HSI 55 +#define IRQ_MMP2_MIPI_HSI0_MUX 55 #define IRQ_MMP2_MSP 58 #define IRQ_MMP2_MIPI_SLIM_DMA 59 #define IRQ_MMP2_PJ4_FREQ_CHG 60 @@ -186,8 +186,14 @@ #define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0) #define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1) +/* secondary interrupt of INT #9 */ +#define IRQ_MMP2_KEYPAD_BASE (IRQ_MMP2_RTC_BASE + 2) +#define IRQ_MMP2_KPC (IRQ_MMP2_KEYPAD_BASE + 0) +#define IRQ_MMP2_ROTORY (IRQ_MMP2_KEYPAD_BASE + 1) +#define IRQ_MMP2_TBALL (IRQ_MMP2_KEYPAD_BASE + 2) + /* secondary interrupt of INT #17 */ -#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_RTC_BASE + 2) +#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_KEYPAD_BASE + 3) #define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0) #define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1) #define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2) @@ -212,11 +218,16 @@ #define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14) /* secondary interrupt of INT #51 */ -#define IRQ_MMP2_SSP_BASE (IRQ_MMP2_MISC_BASE + 15) -#define IRQ_MMP2_SSP1_SRDY (IRQ_MMP2_SSP_BASE + 0) -#define IRQ_MMP2_SSP3_SRDY (IRQ_MMP2_SSP_BASE + 1) +#define IRQ_MMP2_MIPI_HSI1_BASE (IRQ_MMP2_MISC_BASE + 15) +#define IRQ_MMP2_HSI1_CAWAKE (IRQ_MMP2_MIPI_HSI1_BASE + 0) +#define IRQ_MMP2_MIPI_HSI_INT1 (IRQ_MMP2_MIPI_HSI1_BASE + 1) + +/* secondary interrupt of INT #55 */ +#define IRQ_MMP2_MIPI_HSI0_BASE (IRQ_MMP2_MIPI_HSI1_BASE + 2) +#define IRQ_MMP2_HSI0_CAWAKE (IRQ_MMP2_MIPI_HSI0_BASE + 0) +#define IRQ_MMP2_MIPI_HSI_INT0 (IRQ_MMP2_MIPI_HSI0_BASE + 1) -#define IRQ_MMP2_MUX_END (IRQ_MMP2_SSP_BASE + 2) +#define IRQ_MMP2_MUX_END (IRQ_MMP2_MIPI_HSI0_BASE + 2) #define IRQ_GPIO_START 128 #define MMP_NR_BUILTIN_GPIO 192 diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c deleted file mode 100644 index 7895d277421e..000000000000 --- a/arch/arm/mach-mmp/irq-mmp2.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * linux/arch/arm/mach-mmp/irq-mmp2.c - * - * Generic IRQ handling, GPIO IRQ demultiplexing, etc. - * - * Author: Haojian Zhuang - * Copyright: Marvell International Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include - -#include -#include -#include - -#include "common.h" - -static void icu_mask_irq(struct irq_data *d) -{ - uint32_t r = __raw_readl(ICU_INT_CONF(d->irq)); - - r &= ~ICU_INT_ROUTE_PJ4_IRQ; - __raw_writel(r, ICU_INT_CONF(d->irq)); -} - -static void icu_unmask_irq(struct irq_data *d) -{ - uint32_t r = __raw_readl(ICU_INT_CONF(d->irq)); - - r |= ICU_INT_ROUTE_PJ4_IRQ; - __raw_writel(r, ICU_INT_CONF(d->irq)); -} - -static struct irq_chip icu_irq_chip = { - .name = "icu_irq", - .irq_mask = icu_mask_irq, - .irq_mask_ack = icu_mask_irq, - .irq_unmask = icu_unmask_irq, -}; - -static void pmic_irq_ack(struct irq_data *d) -{ - if (d->irq == IRQ_MMP2_PMIC) - mmp2_clear_pmic_int(); -} - -#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \ -static void _name_##_mask_irq(struct irq_data *d) \ -{ \ - uint32_t r; \ - r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base)); \ - __raw_writel(r, prefix##_MASK); \ -} - -#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ -static void _name_##_unmask_irq(struct irq_data *d) \ -{ \ - uint32_t r; \ - r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base)); \ - __raw_writel(r, prefix##_MASK); \ -} - -#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ -static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \ -{ \ - unsigned long status, mask, n; \ - mask = __raw_readl(prefix##_MASK); \ - while (1) { \ - status = __raw_readl(prefix##_STATUS) & ~mask; \ - if (status == 0) \ - break; \ - n = find_first_bit(&status, BITS_PER_LONG); \ - while (n < BITS_PER_LONG) { \ - generic_handle_irq(irq_base + n); \ - n = find_next_bit(&status, BITS_PER_LONG, n+1); \ - } \ - } \ -} - -#define SECOND_IRQ_CHIP(_name_, irq_base, prefix) \ -SECOND_IRQ_MASK(_name_, irq_base, prefix) \ -SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ -SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ -static struct irq_chip _name_##_irq_chip = { \ - .name = #_name_, \ - .irq_mask = _name_##_mask_irq, \ - .irq_unmask = _name_##_unmask_irq, \ -} - -SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4); -SECOND_IRQ_CHIP(rtc, IRQ_MMP2_RTC_BASE, MMP2_ICU_INT5); -SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17); -SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35); -SECOND_IRQ_CHIP(ssp, IRQ_MMP2_SSP_BASE, MMP2_ICU_INT51); - -static void init_mux_irq(struct irq_chip *chip, int start, int num) -{ - int irq; - - for (irq = start; num > 0; irq++, num--) { - struct irq_data *d = irq_get_irq_data(irq); - - /* mask and clear the IRQ */ - chip->irq_mask(d); - if (chip->irq_ack) - chip->irq_ack(d); - - irq_set_chip(irq, chip); - set_irq_flags(irq, IRQF_VALID); - irq_set_handler(irq, handle_level_irq); - } -} - -void __init mmp2_init_icu(void) -{ - int irq; - - for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { - icu_mask_irq(irq_get_irq_data(irq)); - irq_set_chip(irq, &icu_irq_chip); - set_irq_flags(irq, IRQF_VALID); - - switch (irq) { - case IRQ_MMP2_PMIC_MUX: - case IRQ_MMP2_RTC_MUX: - case IRQ_MMP2_TWSI_MUX: - case IRQ_MMP2_MISC_MUX: - case IRQ_MMP2_SSP_MUX: - break; - default: - irq_set_handler(irq, handle_level_irq); - break; - } - } - - /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register - * to be written to clear the interrupt - */ - pmic_irq_chip.irq_ack = pmic_irq_ack; - - init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2); - init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2); - init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5); - init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); - init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); - - irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); - irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); - irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); - irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); - irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); -} diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c deleted file mode 100644 index 89706a0d08f1..000000000000 --- a/arch/arm/mach-mmp/irq-pxa168.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * linux/arch/arm/mach-mmp/irq.c - * - * Generic IRQ handling, GPIO IRQ demultiplexing, etc. - * - * Author: Bin Yang - * Created: Sep 30, 2008 - * Copyright: Marvell International Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include - -#include - -#include "common.h" - -#define IRQ_ROUTE_TO_AP (ICU_INT_CONF_AP_INT | ICU_INT_CONF_IRQ) - -#define PRIORITY_DEFAULT 0x1 -#define PRIORITY_NONE 0x0 /* means IRQ disabled */ - -static void icu_mask_irq(struct irq_data *d) -{ - __raw_writel(PRIORITY_NONE, ICU_INT_CONF(d->irq)); -} - -static void icu_unmask_irq(struct irq_data *d) -{ - __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(d->irq)); -} - -static struct irq_chip icu_irq_chip = { - .name = "icu_irq", - .irq_ack = icu_mask_irq, - .irq_mask = icu_mask_irq, - .irq_unmask = icu_unmask_irq, -}; - -void __init icu_init_irq(void) -{ - int irq; - - for (irq = 0; irq < 64; irq++) { - icu_mask_irq(irq_get_irq_data(irq)); - irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } -} diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c new file mode 100644 index 000000000000..3705470c9f1e --- /dev/null +++ b/arch/arm/mach-mmp/irq.c @@ -0,0 +1,445 @@ +/* + * linux/arch/arm/mach-mmp/irq.c + * + * Generic IRQ handling, GPIO IRQ demultiplexing, etc. + * Copyright (C) 2008 - 2012 Marvell Technology Group Ltd. + * + * Author: Bin Yang + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" + +#define MAX_ICU_NR 16 + +struct icu_chip_data { + int nr_irqs; + unsigned int virq_base; + unsigned int cascade_irq; + void __iomem *reg_status; + void __iomem *reg_mask; + unsigned int conf_enable; + unsigned int conf_disable; + unsigned int conf_mask; + unsigned int clr_mfp_irq_base; + unsigned int clr_mfp_hwirq; + struct irq_domain *domain; +}; + +struct mmp_intc_conf { + unsigned int conf_enable; + unsigned int conf_disable; + unsigned int conf_mask; +}; + +void __iomem *mmp_icu_base; +static struct icu_chip_data icu_data[MAX_ICU_NR]; +static int max_icu_nr; + +extern void mmp2_clear_pmic_int(void); + +static void icu_mask_ack_irq(struct irq_data *d) +{ + struct irq_domain *domain = d->domain; + struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; + int hwirq; + u32 r; + + hwirq = d->irq - data->virq_base; + if (data == &icu_data[0]) { + r = readl_relaxed(mmp_icu_base + (hwirq << 2)); + r &= ~data->conf_mask; + r |= data->conf_disable; + writel_relaxed(r, mmp_icu_base + (hwirq << 2)); + } else { +#ifdef CONFIG_CPU_MMP2 + if ((data->virq_base == data->clr_mfp_irq_base) + && (hwirq == data->clr_mfp_hwirq)) + mmp2_clear_pmic_int(); +#endif + r = readl_relaxed(data->reg_mask) | (1 << hwirq); + writel_relaxed(r, data->reg_mask); + } +} + +static void icu_mask_irq(struct irq_data *d) +{ + struct irq_domain *domain = d->domain; + struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; + int hwirq; + u32 r; + + hwirq = d->irq - data->virq_base; + if (data == &icu_data[0]) { + r = readl_relaxed(mmp_icu_base + (hwirq << 2)); + r &= ~data->conf_mask; + r |= data->conf_disable; + writel_relaxed(r, mmp_icu_base + (hwirq << 2)); + } else { + r = readl_relaxed(data->reg_mask) | (1 << hwirq); + writel_relaxed(r, data->reg_mask); + } +} + +static void icu_unmask_irq(struct irq_data *d) +{ + struct irq_domain *domain = d->domain; + struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; + int hwirq; + u32 r; + + hwirq = d->irq - data->virq_base; + if (data == &icu_data[0]) { + r = readl_relaxed(mmp_icu_base + (hwirq << 2)); + r &= ~data->conf_mask; + r |= data->conf_enable; + writel_relaxed(r, mmp_icu_base + (hwirq << 2)); + } else { + r = readl_relaxed(data->reg_mask) & ~(1 << hwirq); + writel_relaxed(r, data->reg_mask); + } +} + +static struct irq_chip icu_irq_chip = { + .name = "icu_irq", + .irq_mask = icu_mask_irq, + .irq_mask_ack = icu_mask_ack_irq, + .irq_unmask = icu_unmask_irq, +}; + +static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + struct irq_domain *domain; + struct icu_chip_data *data; + int i; + unsigned long mask, status, n; + + for (i = 1; i < max_icu_nr; i++) { + if (irq == icu_data[i].cascade_irq) { + domain = icu_data[i].domain; + data = (struct icu_chip_data *)domain->host_data; + break; + } + } + if (i >= max_icu_nr) { + pr_err("Spurious irq %d in MMP INTC\n", irq); + return; + } + + mask = readl_relaxed(data->reg_mask); + while (1) { + status = readl_relaxed(data->reg_status) & ~mask; + if (status == 0) + break; + n = find_first_bit(&status, BITS_PER_LONG); + while (n < BITS_PER_LONG) { + generic_handle_irq(icu_data[i].virq_base + n); + n = find_next_bit(&status, BITS_PER_LONG, n + 1); + } + } +} + +static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hw) +{ + irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + return 0; +} + +static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node, + const u32 *intspec, unsigned int intsize, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + *out_hwirq = intspec[0]; + return 0; +} + +const struct irq_domain_ops mmp_irq_domain_ops = { + .map = mmp_irq_domain_map, + .xlate = mmp_irq_domain_xlate, +}; + +static struct mmp_intc_conf mmp_conf = { + .conf_enable = 0x51, + .conf_disable = 0x0, + .conf_mask = 0x7f, +}; + +static struct mmp_intc_conf mmp2_conf = { + .conf_enable = 0x20, + .conf_disable = 0x0, + .conf_mask = 0x7f, +}; + +/* MMP (ARMv5) */ +void __init icu_init_irq(void) +{ + int irq; + + max_icu_nr = 1; + mmp_icu_base = ioremap(0xd4282000, 0x1000); + icu_data[0].conf_enable = mmp_conf.conf_enable; + icu_data[0].conf_disable = mmp_conf.conf_disable; + icu_data[0].conf_mask = mmp_conf.conf_mask; + icu_data[0].nr_irqs = 64; + icu_data[0].virq_base = 0; + icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0, + &irq_domain_simple_ops, + &icu_data[0]); + for (irq = 0; irq < 64; irq++) { + icu_mask_irq(irq_get_irq_data(irq)); + irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + irq_set_default_host(icu_data[0].domain); +} + +/* MMP2 (ARMv7) */ +void __init mmp2_init_icu(void) +{ + int irq; + + max_icu_nr = 8; + mmp_icu_base = ioremap(0xd4282000, 0x1000); + icu_data[0].conf_enable = mmp2_conf.conf_enable; + icu_data[0].conf_disable = mmp2_conf.conf_disable; + icu_data[0].conf_mask = mmp2_conf.conf_mask; + icu_data[0].nr_irqs = 64; + icu_data[0].virq_base = 0; + icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0, + &irq_domain_simple_ops, + &icu_data[0]); + icu_data[1].reg_status = mmp_icu_base + 0x150; + icu_data[1].reg_mask = mmp_icu_base + 0x168; + icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE; + icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE; + icu_data[1].nr_irqs = 2; + icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE; + icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs, + icu_data[1].virq_base, 0, + &irq_domain_simple_ops, + &icu_data[1]); + icu_data[2].reg_status = mmp_icu_base + 0x154; + icu_data[2].reg_mask = mmp_icu_base + 0x16c; + icu_data[2].nr_irqs = 2; + icu_data[2].virq_base = IRQ_MMP2_RTC_BASE; + icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs, + icu_data[2].virq_base, 0, + &irq_domain_simple_ops, + &icu_data[2]); + icu_data[3].reg_status = mmp_icu_base + 0x180; + icu_data[3].reg_mask = mmp_icu_base + 0x17c; + icu_data[3].nr_irqs = 3; + icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE; + icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs, + icu_data[3].virq_base, 0, + &irq_domain_simple_ops, + &icu_data[3]); + icu_data[4].reg_status = mmp_icu_base + 0x158; + icu_data[4].reg_mask = mmp_icu_base + 0x170; + icu_data[4].nr_irqs = 5; + icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE; + icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs, + icu_data[4].virq_base, 0, + &irq_domain_simple_ops, + &icu_data[4]); + icu_data[5].reg_status = mmp_icu_base + 0x15c; + icu_data[5].reg_mask = mmp_icu_base + 0x174; + icu_data[5].nr_irqs = 15; + icu_data[5].virq_base = IRQ_MMP2_MISC_BASE; + icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs, + icu_data[5].virq_base, 0, + &irq_domain_simple_ops, + &icu_data[5]); + icu_data[6].reg_status = mmp_icu_base + 0x160; + icu_data[6].reg_mask = mmp_icu_base + 0x178; + icu_data[6].nr_irqs = 2; + icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE; + icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs, + icu_data[6].virq_base, 0, + &irq_domain_simple_ops, + &icu_data[6]); + icu_data[7].reg_status = mmp_icu_base + 0x188; + icu_data[7].reg_mask = mmp_icu_base + 0x184; + icu_data[7].nr_irqs = 2; + icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE; + icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs, + icu_data[7].virq_base, 0, + &irq_domain_simple_ops, + &icu_data[7]); + for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) { + icu_mask_irq(irq_get_irq_data(irq)); + switch (irq) { + case IRQ_MMP2_PMIC_MUX: + case IRQ_MMP2_RTC_MUX: + case IRQ_MMP2_KEYPAD_MUX: + case IRQ_MMP2_TWSI_MUX: + case IRQ_MMP2_MISC_MUX: + case IRQ_MMP2_MIPI_HSI1_MUX: + case IRQ_MMP2_MIPI_HSI0_MUX: + irq_set_chip(irq, &icu_irq_chip); + irq_set_chained_handler(irq, icu_mux_irq_demux); + break; + default: + irq_set_chip_and_handler(irq, &icu_irq_chip, + handle_level_irq); + break; + } + set_irq_flags(irq, IRQF_VALID); + } + irq_set_default_host(icu_data[0].domain); +} + +#ifdef CONFIG_OF +static const struct of_device_id intc_ids[] __initconst = { + { .compatible = "mrvl,mmp-intc", .data = &mmp_conf }, + { .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf }, + {} +}; + +static const struct of_device_id mmp_mux_irq_match[] __initconst = { + { .compatible = "mrvl,mmp2-mux-intc" }, + {} +}; + +int __init mmp2_mux_init(struct device_node *parent) +{ + struct device_node *node; + const struct of_device_id *of_id; + struct resource res; + int i, irq_base, ret, irq; + u32 nr_irqs, mfp_irq; + + node = parent; + max_icu_nr = 1; + for (i = 1; i < MAX_ICU_NR; i++) { + node = of_find_matching_node(node, mmp_mux_irq_match); + if (!node) + break; + of_id = of_match_node(&mmp_mux_irq_match[0], node); + ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", + &nr_irqs); + if (ret) { + pr_err("Not found mrvl,intc-nr-irqs property\n"); + ret = -EINVAL; + goto err; + } + ret = of_address_to_resource(node, 0, &res); + if (ret < 0) { + pr_err("Not found reg property\n"); + ret = -EINVAL; + goto err; + } + icu_data[i].reg_status = mmp_icu_base + res.start; + ret = of_address_to_resource(node, 1, &res); + if (ret < 0) { + pr_err("Not found reg property\n"); + ret = -EINVAL; + goto err; + } + icu_data[i].reg_mask = mmp_icu_base + res.start; + icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0); + if (!icu_data[i].cascade_irq) { + ret = -EINVAL; + goto err; + } + + irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); + if (irq_base < 0) { + pr_err("Failed to allocate IRQ numbers for mux intc\n"); + ret = irq_base; + goto err; + } + if (!of_property_read_u32(node, "mrvl,clr-mfp-irq", + &mfp_irq)) { + icu_data[i].clr_mfp_irq_base = irq_base; + icu_data[i].clr_mfp_hwirq = mfp_irq; + } + irq_set_chained_handler(icu_data[i].cascade_irq, + icu_mux_irq_demux); + icu_data[i].nr_irqs = nr_irqs; + icu_data[i].virq_base = irq_base; + icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs, + irq_base, 0, + &mmp_irq_domain_ops, + &icu_data[i]); + for (irq = irq_base; irq < irq_base + nr_irqs; irq++) + icu_mask_irq(irq_get_irq_data(irq)); + } + max_icu_nr = i; + return 0; +err: + of_node_put(node); + max_icu_nr = i; + return ret; +} + +void __init mmp_dt_irq_init(void) +{ + struct device_node *node; + const struct of_device_id *of_id; + struct mmp_intc_conf *conf; + int nr_irqs, irq_base, ret, irq; + + node = of_find_matching_node(NULL, intc_ids); + if (!node) { + pr_err("Failed to find interrupt controller in arch-mmp\n"); + return; + } + of_id = of_match_node(intc_ids, node); + conf = of_id->data; + + ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs); + if (ret) { + pr_err("Not found mrvl,intc-nr-irqs property\n"); + return; + } + + mmp_icu_base = of_iomap(node, 0); + if (!mmp_icu_base) { + pr_err("Failed to get interrupt controller register\n"); + return; + } + + irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0); + if (irq_base < 0) { + pr_err("Failed to allocate IRQ numbers\n"); + goto err; + } else if (irq_base != NR_IRQS_LEGACY) { + pr_err("ICU's irqbase should be started from 0\n"); + goto err; + } + icu_data[0].conf_enable = conf->conf_enable; + icu_data[0].conf_disable = conf->conf_disable; + icu_data[0].conf_mask = conf->conf_mask; + icu_data[0].nr_irqs = nr_irqs; + icu_data[0].virq_base = 0; + icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0, + &mmp_irq_domain_ops, + &icu_data[0]); + irq_set_default_host(icu_data[0].domain); + for (irq = 0; irq < nr_irqs; irq++) + icu_mask_irq(irq_get_irq_data(irq)); + mmp2_mux_init(node); + return; +err: + iounmap(mmp_icu_base); +} +#endif -- cgit v1.2.3 From c68ef2b5921cf26225533c8ed109386578060a98 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Thu, 12 Apr 2012 19:05:40 +0800 Subject: ARM: mmp: support DT in timer Parse timer from DTS file. Avoid to use hardcoding marco for register. Signed-off-by: Haojian Zhuang Acked-by: Arnd Bergmann --- arch/arm/mach-mmp/time.c | 81 +++++++++++++++++++++++++++++++++++------------- 1 file changed, 60 insertions(+), 21 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 71fc4ee4602c..936447c70977 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -25,6 +25,9 @@ #include #include +#include +#include +#include #include #include @@ -41,6 +44,8 @@ #define MAX_DELTA (0xfffffffe) #define MIN_DELTA (16) +static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE; + /* * FIXME: the timer needs some delay to stablize the counter capture */ @@ -48,12 +53,12 @@ static inline uint32_t timer_read(void) { int delay = 100; - __raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(1)); + __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); while (delay--) cpu_relax(); - return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(1)); + return __raw_readl(mmp_timer_base + TMR_CVWR(1)); } static u32 notrace mmp_read_sched_clock(void) @@ -68,12 +73,12 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id) /* * Clear pending interrupt status. */ - __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0)); + __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); /* * Disable timer 0. */ - __raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER); + __raw_writel(0x02, mmp_timer_base + TMR_CER); c->event_handler(c); @@ -90,23 +95,23 @@ static int timer_set_next_event(unsigned long delta, /* * Disable timer 0. */ - __raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER); + __raw_writel(0x02, mmp_timer_base + TMR_CER); /* * Clear and enable timer match 0 interrupt. */ - __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0)); - __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0)); + __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); + __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); /* * Setup new clockevent timer value. */ - __raw_writel(delta - 1, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0)); + __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0)); /* * Enable timer 0. */ - __raw_writel(0x03, TIMERS_VIRT_BASE + TMR_CER); + __raw_writel(0x03, mmp_timer_base + TMR_CER); local_irq_restore(flags); @@ -124,7 +129,7 @@ static void timer_set_mode(enum clock_event_mode mode, case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: /* disable the matching interrupt */ - __raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0)); + __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); break; case CLOCK_EVT_MODE_RESUME: case CLOCK_EVT_MODE_PERIODIC: @@ -157,27 +162,27 @@ static struct clocksource cksrc = { static void __init timer_config(void) { - uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR); + uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR); - __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */ + __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */ ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) : (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3)); - __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR); + __raw_writel(ccr, mmp_timer_base + TMR_CCR); /* set timer 0 to periodic mode, and timer 1 to free-running mode */ - __raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CMR); + __raw_writel(0x2, mmp_timer_base + TMR_CMR); - __raw_writel(0x1, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* periodic */ - __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */ - __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0)); + __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */ + __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */ + __raw_writel(0x0, mmp_timer_base + TMR_IER(0)); - __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(1)); /* free-running */ - __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(1)); /* clear status */ - __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(1)); + __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */ + __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */ + __raw_writel(0x0, mmp_timer_base + TMR_IER(1)); /* enable timer 1 counter */ - __raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CER); + __raw_writel(0x2, mmp_timer_base + TMR_CER); } static struct irqaction timer_irq = { @@ -203,3 +208,37 @@ void __init timer_init(int irq) clocksource_register_hz(&cksrc, CLOCK_TICK_RATE); clockevents_register_device(&ckevt); } + +#ifdef CONFIG_OF +static struct of_device_id mmp_timer_dt_ids[] = { + { .compatible = "mrvl,mmp-timer", }, + {} +}; + +void __init mmp_dt_init_timer(void) +{ + struct device_node *np; + int irq, ret; + + np = of_find_matching_node(NULL, mmp_timer_dt_ids); + if (!np) { + ret = -ENODEV; + goto out; + } + + irq = irq_of_parse_and_map(np, 0); + if (!irq) { + ret = -EINVAL; + goto out; + } + mmp_timer_base = of_iomap(np, 0); + if (!mmp_timer_base) { + ret = -ENOMEM; + goto out; + } + timer_init(irq); + return; +out: + pr_err("Failed to get timer from device tree with error:%d\n", ret); +} +#endif -- cgit v1.2.3 From a56f9162dd2b160b7faff610116ddcfe33a59081 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Thu, 19 Apr 2012 17:46:53 +0800 Subject: ARM: mmp: support mmp2 with device tree Signed-off-by: Haojian Zhuang Acked-by: Arnd Bergmann --- arch/arm/mach-mmp/Makefile | 1 + arch/arm/mach-mmp/mmp2-dt.c | 60 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 arch/arm/mach-mmp/mmp2-dt.c (limited to 'arch/arm') diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 77f63c12e0ba..b920b9bfbdb6 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -19,5 +19,6 @@ obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o obj-$(CONFIG_MACH_FLINT) += flint.o obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o obj-$(CONFIG_MACH_MMP_DT) += mmp-dt.o +obj-$(CONFIG_MACH_MMP2_DT) += mmp2-dt.o obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o obj-$(CONFIG_MACH_GPLUGD) += gplugd.o diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c new file mode 100644 index 000000000000..535a5ed5977b --- /dev/null +++ b/arch/arm/mach-mmp/mmp2-dt.c @@ -0,0 +1,60 @@ +/* + * linux/arch/arm/mach-mmp/mmp2-dt.c + * + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" + +extern void __init mmp_dt_irq_init(void); +extern void __init mmp_dt_init_timer(void); + +static struct sys_timer mmp_dt_timer = { + .init = mmp_dt_init_timer, +}; + +static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL), + OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL), + OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.2", NULL), + OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL), + OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL), + OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL), + OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL), + OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL), + {} +}; + +static void __init mmp2_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + mmp2_auxdata_lookup, NULL); +} + +static const char *mmp2_dt_board_compat[] __initdata = { + "mrvl,mmp2-brownstone", + NULL, +}; + +DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)") + .map_io = mmp_map_io, + .init_irq = mmp_dt_irq_init, + .timer = &mmp_dt_timer, + .init_machine = mmp2_dt_init, + .dt_compat = mmp2_dt_board_compat, +MACHINE_END -- cgit v1.2.3 From 641f4d562cf69e1839c84c9415169644025ec247 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Thu, 19 Apr 2012 18:36:31 +0800 Subject: ARM: mmp: support pxa910 with device tree Suppot gpio/irq/timer in mmp-dt driver. Support PXA910 also in mmp-dt driver. Signed-off-by: Haojian Zhuang Acked-by: Arnd Bergmann --- arch/arm/mach-mmp/mmp-dt.c | 50 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 40 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c index ca22e3c04e90..033cc31b3c72 100644 --- a/arch/arm/mach-mmp/mmp-dt.c +++ b/arch/arm/mach-mmp/mmp-dt.c @@ -14,14 +14,19 @@ #include #include #include +#include #include #include "common.h" -extern struct sys_timer pxa168_timer; -extern void __init icu_init_irq(void); +extern void __init mmp_dt_irq_init(void); +extern void __init mmp_dt_init_timer(void); -static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = { +static struct sys_timer mmp_dt_timer = { + .init = mmp_dt_init_timer, +}; + +static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL), OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL), OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL), @@ -32,22 +37,47 @@ static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = { {} }; -static void __init mmp_dt_init(void) +static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL), + OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL), + OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL), + OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL), + OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL), + OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL), + OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL), + {} +}; + +static void __init pxa168_dt_init(void) { + of_platform_populate(NULL, of_default_bus_match_table, + pxa168_auxdata_lookup, NULL); +} +static void __init pxa910_dt_init(void) +{ of_platform_populate(NULL, of_default_bus_match_table, - mmp_auxdata_lookup, NULL); + pxa910_auxdata_lookup, NULL); } -static const char *pxa168_dt_board_compat[] __initdata = { +static const char *mmp_dt_board_compat[] __initdata = { "mrvl,pxa168-aspenite", + "mrvl,pxa910-dkb", NULL, }; DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)") .map_io = mmp_map_io, - .init_irq = icu_init_irq, - .timer = &pxa168_timer, - .init_machine = mmp_dt_init, - .dt_compat = pxa168_dt_board_compat, + .init_irq = mmp_dt_irq_init, + .timer = &mmp_dt_timer, + .init_machine = pxa168_dt_init, + .dt_compat = mmp_dt_board_compat, +MACHINE_END + +DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)") + .map_io = mmp_map_io, + .init_irq = mmp_dt_irq_init, + .timer = &mmp_dt_timer, + .init_machine = pxa910_dt_init, + .dt_compat = mmp_dt_board_compat, MACHINE_END -- cgit v1.2.3 From ff290fc3ed7c4f451ea029190624cff692f028a5 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Thu, 19 Apr 2012 18:44:50 +0800 Subject: ARM: dts: refresh dts file for arch mmp Append mmp2 and pxa910 dts files. Update PXA168 dts files for irq, timer, gpio components. Signed-off-by: Haojian Zhuang Acked-by: Arnd Bergmann --- arch/arm/boot/dts/mmp2-brownstone.dts | 38 ++++++ arch/arm/boot/dts/mmp2.dtsi | 220 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/pxa168.dtsi | 67 ++++++++--- arch/arm/boot/dts/pxa910-dkb.dts | 38 ++++++ arch/arm/boot/dts/pxa910.dtsi | 140 ++++++++++++++++++++++ 5 files changed, 487 insertions(+), 16 deletions(-) create mode 100644 arch/arm/boot/dts/mmp2-brownstone.dts create mode 100644 arch/arm/boot/dts/mmp2.dtsi create mode 100644 arch/arm/boot/dts/pxa910-dkb.dts create mode 100644 arch/arm/boot/dts/pxa910.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts new file mode 100644 index 000000000000..153a4b2d12b5 --- /dev/null +++ b/arch/arm/boot/dts/mmp2-brownstone.dts @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +/dts-v1/; +/include/ "mmp2.dtsi" + +/ { + model = "Marvell MMP2 Aspenite Development Board"; + compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2"; + + chosen { + bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; + }; + + memory { + reg = <0x00000000 0x04000000>; + }; + + soc { + apb@d4000000 { + uart3: uart@d4018000 { + status = "okay"; + }; + twsi1: i2c@d4011000 { + status = "okay"; + }; + rtc: rtc@d4010000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi new file mode 100644 index 000000000000..80f74e256408 --- /dev/null +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + i2c0 = &twsi1; + i2c1 = &twsi2; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + axi@d4200000 { /* AXI */ + compatible = "mrvl,axi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4200000 0x00200000>; + ranges; + + intc: interrupt-controller@d4282000 { + compatible = "mrvl,mmp2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd4282000 0x1000>; + mrvl,intc-nr-irqs = <64>; + }; + + intcmux4@d4282150 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <4>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x150 0x4>, <0x168 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <2>; + }; + + intcmux5: interrupt-controller@d4282154 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <5>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x154 0x4>, <0x16c 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <2>; + mrvl,clr-mfp-irq = <1>; + }; + + intcmux9: interrupt-controller@d4282180 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <9>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x180 0x4>, <0x17c 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <3>; + }; + + intcmux17: interrupt-controller@d4282158 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <17>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x158 0x4>, <0x170 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <5>; + }; + + intcmux35: interrupt-controller@d428215c { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <35>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x15c 0x4>, <0x174 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <15>; + }; + + intcmux51: interrupt-controller@d4282160 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <51>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x160 0x4>, <0x178 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <2>; + }; + + intcmux55: interrupt-controller@d4282188 { + compatible = "mrvl,mmp2-mux-intc"; + interrupts = <55>; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x188 0x4>, <0x184 0x4>; + reg-names = "mux status", "mux mask"; + mrvl,intc-nr-irqs = <2>; + }; + }; + + apb@d4000000 { /* APB */ + compatible = "mrvl,apb-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4000000 0x00200000>; + ranges; + + timer0: timer@d4014000 { + compatible = "mrvl,mmp-timer"; + reg = <0xd4014000 0x100>; + interrupts = <13>; + }; + + uart1: uart@d4030000 { + compatible = "mrvl,mmp-uart"; + reg = <0xd4030000 0x1000>; + interrupts = <27>; + status = "disabled"; + }; + + uart2: uart@d4017000 { + compatible = "mrvl,mmp-uart"; + reg = <0xd4017000 0x1000>; + interrupts = <28>; + status = "disabled"; + }; + + uart3: uart@d4018000 { + compatible = "mrvl,mmp-uart"; + reg = <0xd4018000 0x1000>; + interrupts = <24>; + status = "disabled"; + }; + + uart4: uart@d4016000 { + compatible = "mrvl,mmp-uart"; + reg = <0xd4016000 0x1000>; + interrupts = <46>; + status = "disabled"; + }; + + gpio@d4019000 { + compatible = "mrvl,mmp-gpio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4019000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <49>; + interrupt-names = "gpio_mux"; + interrupt-controller; + #interrupt-cells = <1>; + ranges; + + gcb0: gpio@d4019000 { + reg = <0xd4019000 0x4>; + }; + + gcb1: gpio@d4019004 { + reg = <0xd4019004 0x4>; + }; + + gcb2: gpio@d4019008 { + reg = <0xd4019008 0x4>; + }; + + gcb3: gpio@d4019100 { + reg = <0xd4019100 0x4>; + }; + + gcb4: gpio@d4019104 { + reg = <0xd4019104 0x4>; + }; + + gcb5: gpio@d4019108 { + reg = <0xd4019108 0x4>; + }; + }; + + twsi1: i2c@d4011000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4011000 0x1000>; + interrupts = <7>; + mrvl,i2c-fast-mode; + status = "disabled"; + }; + + twsi2: i2c@d4025000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4025000 0x1000>; + interrupts = <58>; + status = "disabled"; + }; + + rtc: rtc@d4010000 { + compatible = "mrvl,mmp-rtc"; + reg = <0xd4010000 0x1000>; + interrupts = <1 0>; + interrupt-names = "rtc 1Hz", "rtc alarm"; + interrupt-parent = <&intcmux5>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index d32d5128f225..31a718696080 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi @@ -18,13 +18,6 @@ i2c1 = &twsi2; }; - intc: intc-interrupt-controller@d4282000 { - compatible = "mrvl,mmp-intc", "mrvl,intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - }; - soc { #address-cells = <1>; #size-cells = <1>; @@ -32,6 +25,23 @@ interrupt-parent = <&intc>; ranges; + axi@d4200000 { /* AXI */ + compatible = "mrvl,axi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4200000 0x00200000>; + ranges; + + intc: interrupt-controller@d4282000 { + compatible = "mrvl,mmp-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd4282000 0x1000>; + mrvl,intc-nr-irqs = <64>; + }; + + }; + apb@d4000000 { /* APB */ compatible = "mrvl,apb-bus", "simple-bus"; #address-cells = <1>; @@ -39,40 +49,65 @@ reg = <0xd4000000 0x00200000>; ranges; + timer0: timer@d4014000 { + compatible = "mrvl,mmp-timer"; + reg = <0xd4014000 0x100>; + interrupts = <13>; + }; + uart1: uart@d4017000 { - compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; + compatible = "mrvl,mmp-uart"; reg = <0xd4017000 0x1000>; interrupts = <27>; status = "disabled"; }; uart2: uart@d4018000 { - compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; + compatible = "mrvl,mmp-uart"; reg = <0xd4018000 0x1000>; interrupts = <28>; status = "disabled"; }; uart3: uart@d4026000 { - compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; + compatible = "mrvl,mmp-uart"; reg = <0xd4026000 0x1000>; interrupts = <29>; status = "disabled"; }; - gpio: gpio@d4019000 { - compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio"; + gpio@d4019000 { + compatible = "mrvl,mmp-gpio"; + #address-cells = <1>; + #size-cells = <1>; reg = <0xd4019000 0x1000>; + gpio-controller; + #gpio-cells = <2>; interrupts = <49>; interrupt-names = "gpio_mux"; - gpio-controller; - #gpio-cells = <1>; interrupt-controller; #interrupt-cells = <1>; + ranges; + + gcb0: gpio@d4019000 { + reg = <0xd4019000 0x4>; + }; + + gcb1: gpio@d4019004 { + reg = <0xd4019004 0x4>; + }; + + gcb2: gpio@d4019008 { + reg = <0xd4019008 0x4>; + }; + + gcb3: gpio@d4019100 { + reg = <0xd4019100 0x4>; + }; }; twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; + compatible = "mrvl,mmp-twsi"; reg = <0xd4011000 0x1000>; interrupts = <7>; mrvl,i2c-fast-mode; @@ -80,7 +115,7 @@ }; twsi2: i2c@d4025000 { - compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; + compatible = "mrvl,mmp-twsi"; reg = <0xd4025000 0x1000>; interrupts = <58>; status = "disabled"; diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts new file mode 100644 index 000000000000..e92be5a474e7 --- /dev/null +++ b/arch/arm/boot/dts/pxa910-dkb.dts @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +/dts-v1/; +/include/ "pxa910.dtsi" + +/ { + model = "Marvell PXA910 DKB Development Board"; + compatible = "mrvl,pxa910-dkb", "mrvl,pxa910"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; + }; + + memory { + reg = <0x00000000 0x10000000>; + }; + + soc { + apb@d4000000 { + uart1: uart@d4017000 { + status = "okay"; + }; + twsi1: i2c@d4011000 { + status = "okay"; + }; + rtc: rtc@d4010000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi new file mode 100644 index 000000000000..aebf32de73b4 --- /dev/null +++ b/arch/arm/boot/dts/pxa910.dtsi @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + i2c0 = &twsi1; + i2c1 = &twsi2; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + axi@d4200000 { /* AXI */ + compatible = "mrvl,axi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4200000 0x00200000>; + ranges; + + intc: interrupt-controller@d4282000 { + compatible = "mrvl,mmp-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd4282000 0x1000>; + mrvl,intc-nr-irqs = <64>; + }; + + }; + + apb@d4000000 { /* APB */ + compatible = "mrvl,apb-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4000000 0x00200000>; + ranges; + + timer0: timer@d4014000 { + compatible = "mrvl,mmp-timer"; + reg = <0xd4014000 0x100>; + interrupts = <13>; + }; + + timer1: timer@d4016000 { + compatible = "mrvl,mmp-timer"; + reg = <0xd4016000 0x100>; + interrupts = <29>; + status = "disabled"; + }; + + uart1: uart@d4017000 { + compatible = "mrvl,mmp-uart"; + reg = <0xd4017000 0x1000>; + interrupts = <27>; + status = "disabled"; + }; + + uart2: uart@d4018000 { + compatible = "mrvl,mmp-uart"; + reg = <0xd4018000 0x1000>; + interrupts = <28>; + status = "disabled"; + }; + + uart3: uart@d4036000 { + compatible = "mrvl,mmp-uart"; + reg = <0xd4036000 0x1000>; + interrupts = <59>; + status = "disabled"; + }; + + gpio@d4019000 { + compatible = "mrvl,mmp-gpio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4019000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <49>; + interrupt-names = "gpio_mux"; + interrupt-controller; + #interrupt-cells = <1>; + ranges; + + gcb0: gpio@d4019000 { + reg = <0xd4019000 0x4>; + }; + + gcb1: gpio@d4019004 { + reg = <0xd4019004 0x4>; + }; + + gcb2: gpio@d4019008 { + reg = <0xd4019008 0x4>; + }; + + gcb3: gpio@d4019100 { + reg = <0xd4019100 0x4>; + }; + }; + + twsi1: i2c@d4011000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4011000 0x1000>; + interrupts = <7>; + mrvl,i2c-fast-mode; + status = "disabled"; + }; + + twsi2: i2c@d4037000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4037000 0x1000>; + interrupts = <54>; + status = "disabled"; + }; + + rtc: rtc@d4010000 { + compatible = "mrvl,mmp-rtc"; + reg = <0xd4010000 0x1000>; + interrupts = <5 6>; + interrupt-names = "rtc 1Hz", "rtc alarm"; + status = "disabled"; + }; + }; + }; +}; -- cgit v1.2.3