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path: root/drivers/mmc/host/mmci.h
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2017-02-13mmc: core/mmci: restore pre/post_req behaviourLinus Walleij1-1/+2
commit 64b12a68a9f74bb32d8efd7af1ad8a2ba02fc884 "mmc: core: fix prepared requests while doing bkops" is fixing a bug in the wrong way. A bug in the MMCI device driver is fixed by amending the MMC core. Thinking about it: what the pre- and post-callbacks are doing is to essentially map and unmap SG lists for DMA transfers. Why would we not be able to do that just because a BKOPS command is sent inbetween? Having to unprepare/prepare the next asynchronous request for DMA seems wrong. Looking the backtrace in that commit we can see what the real problem actually is: mmci_data_irq() is calling mmci_dma_unmap() twice which is goung to call arm_dma_unmap_sg() twice and v7_dma_inv_range() twice for the same sglist and that will crash. This happens because a request is prepared, then a BKOPS is sent. The IRQ completing the BKOPS command goes through mmci_data_irq() and thinks that a DMA operation has just been completed because dma_inprogress() reports true. It then proceeds to unmap the sglist. But that was wrong! dma_inprogress() should NOT be true because no DMA was actually in progress! We had just prepared the sglist, and the DMA channel dma_current has been configured, but NOT started! Because of this, the sglist is already unmapped when we get our actual data completion IRQ, and we are unmapping the sglist once more, and we get this crash. Therefore, we need to revert this solution pushing the problem to the core and causing problems, and instead augment the implementation such that dma_inprogress() only reports true if some DMA has actually been started. After this we can keep the request prepared during the BKOPS and we need not unprepare/reprepare it. Fixes: 64b12a68a9f7 ("mmc: core: fix prepared requests while doing bkops") Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-11-29mmc: mmci: refactor ST Micro busy detectionLinus Walleij1-1/+1
The ST Micro-specific busy detection was made after the assumption that only this variant supports busy detection. So when doing busy detection, the host immediately tries to use some ST-specific register bits. Since the qualcomm variant also supports some busy detection schemes, encapsulate the variant flags better in the variant struct and prepare to add more variants by just providing some bitmasks to the logic. Put the entire busy detection logic within an if()-clause in the mmci_cmd_irq() function so the code is only executed when busy detection is enabled, and so that it is kept in (almost) one place, and add comments describing what is going on so the code can be understood. Tested on the Ux500 by introducing some prints in the busy detection path and noticing how the IRQ is enabled, used and disabled successfully. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-11-29mmc: mmci: clean up header definesLinus Walleij1-31/+38
There was some confusion in the CPSM (Command Path State Machine) and DPSM (Data Path State Machine) regarding the naming of the registers, clarify the meaning of this acronym so the naming is understandable, and consistently use BIT() to define these fields. Consequently name the register bit defines MCI_[C|D]PSM_* and adjust the driver as well. Include new definitions for a few bits found in a patch from Srinivas Kandagatla. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2014-07-09mmc: mmci: Add Qcom specific rx_fifocnt logic.Srinivas Kandagatla1-0/+1
MCIFIFOCNT register behaviour on Qcom chips is very different than the other pl180 integrations. MCIFIFOCNT register contains the number of words that are still waiting to be transferred through the FIFO. It keeps decrementing once the host CPU reads the MCIFIFO. With the existing logic and the MCIFIFOCNT behaviour, mmci_pio_read will loop forever, as the FIFOCNT register will always return transfer size before reading the FIFO. Also the data sheet states that "This register is only useful for debug purposes and should not be used for normal operation since it does not reflect data which may or may not be in the pipeline". This patch implements a qcom specific get_rx_fifocnt function which is implemented based on status register flags. Based on qcom_fifo flag in variant data structure, the corresponding get_rx_fifocnt function is selected. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2014-07-09mmc: mmci: add explicit clk controlSrinivas Kandagatla1-0/+2
On Controllers like Qcom SD card controller where cclk is mclk and mclk should be directly controlled by the driver. This patch adds support to control mclk directly in the driver, and also adds explicit_mclk_control flag in variant structure giving more flexibility to the driver. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> [Ulf Hansson] Fixed checkpatch warning Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2014-07-09mmc: mmci: Add Qualcomm specific register defines.Srinivas Kandagatla1-0/+17
This patch adds a Qualcomm SD Card controller specific register variations to header file. Qualcomm SDCC controller is pl180, with slight changes in the register layout from standard pl180 register set. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2014-05-12mmc: mmci: Enforce DT for signal direction and feedback clockUlf Hansson1-0/+11
Remove the option to provide signal direction configuration and feeback clock as platform data, enforce it through DT. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2014-05-12mmc: mmci: Convert to the mmc gpio APIUlf Hansson1-3/+0
To avoid duplication of code while handling card detect and write protect GPIO pins/irqs, let's convert to use the mmc gpio API. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2014-04-09Merge tag 'mmc-updates-for-3.15-rc1' of ↵Linus Torvalds1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc Pull MMC updates from Chris Ball: "MMC highlights for 3.15: Core: - CONFIG_MMC_UNSAFE_RESUME=y is now default behavior - DT bindings for SDHCI UHS, eMMC HS200, high-speed DDR, at 1.8/1.2V - Add GPIO descriptor based slot-gpio card detect API Drivers: - dw_mmc: Refactor SOCFPGA support as a variant inside dw_mmc-pltfm.c - mmci: Support HW busy detection on ux500 - omap: Support MMC_ERASE - omap_hsmmc: Support MMC_PM_KEEP_POWER, MMC_PM_WAKE_SDIO_IRQ, (a)cmd23 - rtsx: Support pre-req/post-req async - sdhci: Add support for Realtek RTS5250 controllers - sdhci-acpi: Add support for 80860F16, fix 80860F14/SDIO card detect - sdhci-msm: Add new driver for Qualcomm SDHCI chipset support - sdhci-pxav3: Add support for Marvell Armada 380 and 385 SoCs" * tag 'mmc-updates-for-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc: (102 commits) mmc: sdhci-acpi: Intel SDIO has broken card detect mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller mmc: sdhci-msm: Add platform_execute_tuning implementation mmc: sdhci-msm: Initial support for Qualcomm chipsets mmc: sdhci-msm: Qualcomm SDHCI binding documentation sdhci: only reprogram retuning timer when flag is set mmc: rename ARCH_BCM to ARCH_BCM_MOBILE mmc: sdhci: Allow for irq being shared mmc: sdhci-acpi: Add device id 80860F16 mmc: sdhci-acpi: Fix broken card detect for ACPI HID 80860F14 mmc: slot-gpio: Add GPIO descriptor based CD GPIO API mmc: slot-gpio: Split out CD IRQ request into a separate function mmc: slot-gpio: Record GPIO descriptors instead of GPIO numbers Revert "dts: socfpga: Add support for SD/MMC on the SOCFPGA platform" mmc: sdhci-spear: use generic card detection gpio support mmc: sdhci-spear: remove support for power gpio mmc: sdhci-spear: simplify resource handling mmc: sdhci-spear: fix platform_data usage mmc: sdhci-spear: fix error handling paths for DT mmc: sdhci-bcm-kona: fix build errors when built-in ...
2014-02-23mmc: mmci: Enable support for busy detection for ux500 variantUlf Hansson1-0/+2
The ux500 variants have HW busy detection support, which is indicated by the busy_detect flag. For these variants let's enable the MMC_CAP_WAIT_WHILE_BUSY flag and add the support for it. The mmc core will provide the RSP_BUSY command flag for those requests we should care about busy detection. Regarding the max_busy_timeout, the HW don't support busy detection timeouts so at this initial step let's make it simple and set it to zero to indicate we are able to support any timeout. Cc: Russell King <linux@arm.linux.org.uk> Cc: Johan Rudholm <jrudholm@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
2014-02-12ARM: 7956/1: mmci: rename some extended flagsLinus Walleij1-4/+5
These four (so far unused) flags are only found in the ST Micro versions of MMCI, so infix them properly with the _ST_ infix. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-09-19ARM: 7831/1: mmc: mmci: Adapt to new pinctrl handlingUlf Hansson1-4/+0
There is no need for every driver to fetch a pinctrl handle and to select the default state. Instead this is handled by the device driver core, thus we can remove this piece of code from mmci. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-05-23ARM: 7726/1: mmc: mmci: Add card_busy function to improve UHS card supportUlf Hansson1-0/+2
To verify a signal voltage switch at initialization of UHS cards the .card_busy callback is used. For some of the ST-variants, card busy detection on the DAT0 pin is supported. We extend the variant struct with a busy_detect flag to indicate support for it. A corresponding busy detect function, which polls the busy status bit, is then set to the .card_busy callback. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-05-23ARM: 7725/1: mmc: mmci: Cache MMCIDATACTRL registerUlf Hansson1-0/+1
Add a cache variable in the host struct that reflects the current data in the MMCIDATACTRL register. This patch will not introduce any functional change but instead provide an easy option to keep specific bits in the register between each data transfer. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-05-23ARM: 7721/1: mmc: mmci: Fixup regulator handling for vqmmcUlf Hansson1-0/+1
We can not rely on regulator_is_enabled to decide whether to enable|disable the regulator. It would mean that the reference counter for it is not balanced properly. Instead keep track of our internal state by using a new flag in the host struct, so we can take correct decisions. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-01-28ARM: 7631/1: mmc: mmci: Add new VE MMCI variantPawel Moll1-0/+2
The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208 and v116/216) contains a modified version of the PL180 MMCI, with PeriphID Configuration value changed to 0x2. This version adds an optional "hardware flow control" feature. When enabled MMC card clock will be automatically disabled when FIFO is about to over/underflow and re-enabled once the host retrieved some data. This makes the controller immune to over/underrun errors caused by big interrupt handling latencies. This patch adds relevant device variant in the driver. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-01-08ARM: 7620/1: mmc: mmci: Convert to use mmc_regulator_get_supplyUlf Hansson1-1/+0
By using the mmc_regulator_get_supply API we are able to do some cleanups of the regulator code. Additionally let the regulator API handle the error printing. Cc: Chris Ball <cjb@laptop.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-11-04ARM: 7562/2: MMCI: fetch pinctrl handle and set default stateLinus Walleij1-0/+4
This fetches the pinctrl resource for the MMCI driver, and if a "default" state is found, it is activated. Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-02-02ARM: 7280/1: mmc: mmci: Cache MMCICLOCK and MMCIPOWER registerUlf Hansson1-1/+2
Instead of reading a register value everytime we need to apply a new value for it, maintain a cached copy for it. This also means we are able to skip writes that are not needed. Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-20ARM: 7218/1: mmc: mmci: Provide option to configure bus signal directionUlf Hansson1-10/+0
The ST Micro variant supports bus signal direction indication. A new member in the variant struct is added for this. Moreover the actual signal direction configuration is board specific, thus the amba mmci platform data is extended with a new member to be able provide mmci with these specific board configurations. This patch is based upon a patch from Sebastian Rasmussen. Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sebastian Rasmussen <sebastian.rasmussen@stericsson.com> Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-20ARM: 7215/1: mmc: mmci: Increase max_segs from 16 to 128Ulf Hansson1-1/+1
A significant increase (10-20%) in performance throughput for USB mass storage is the reason for incrementing the value. By some reason the USB driver allocates buffers which requires a scattergather list to contain a lot more than 16 elements to get optimal performance. This change sets the maximum elements to 128. Tests with large reads and large writes (100 MiB) show that the throughput increase is significant for write (10% for this test) but not for read. Tests are run on a Linux host with ext4 FS on the gadget mass storage device. The sg-len still exceeds 16 for the read tests but the performance gain is low or nothing. Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Per Forlin <per.forlin@stericsson.com> Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-20mmc: mmci: implement pre_req() and post_req()Per Forlin1-0/+8
pre_req() runs dma_map_sg() and prepares the dma descriptor for the next mmc data transfer. post_req() runs dma_unmap_sg. If not calling pre_req() before mmci_request(), mmci_request() will prepare the cache and dma just like it did it before. It is optional to use pre_req() and post_req() for mmci. Signed-off-by: Per Forlin <per.forlin@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-07-06ARM: 6980/1: mmci: use StartBitErr to detect bad connectionsLinus Walleij1-1/+4
Stresstesting insert/remove of SD-cards can trigger a StartBitErr. This made the driver to hang in forever waiting for a non ocurring data timeout. This bit and interrupt is documented in the original PL180 TRM, just never implemented until now. Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com> Reviewed-by: Linus Walleij <linus.walleij@stericsson.com> Reviewed-by: Jonas Aberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-05-11ARM: 6785/1: mmci: separate out ST Micro register definesLinus Walleij1-14/+27
The mmci.h header contained a few registers not clearly marked as ST Micro only, rectify this and remove the HWFC magic in the process. The idea is to make the mmci.h header file more ordered so other vendors with PL180 derivates can see where to put in their custom register defines. Includes portions of an earlier patch from Sebastian Rasmussen. Acked-by: Sebastian Rasmussen <sebastian.rasmussen@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-04ARM: mmci: add dmaengine-based DMA supportRussell King1-0/+13
Based on a patch from Linus Walleij. Add dmaengine based support for DMA to the MMCI driver, using the Primecell DMA engine interface. The changes over Linus' driver are: - rename txsize_threshold to dmasize_threshold, as this reflects the purpose more. - use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'. - clean up requesting of dma channels. - don't release a single channel twice when it's shared between tx and rx. - get rid of 'dma_enable' bool - instead check whether the channel is NULL. - detect incomplete DMA at the end of a transfer. Some DMA controllers (eg, PL08x) are unable to be configured for scatter DMA and also listen to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI. They can do one or other but not both. As MMCI uses LBREQ/LSREQ for the final burst/words, PL08x does not transfer the last few words. - map and unmap DMA buffers using the DMA engine struct device, not the MMCI struct device - the DMA engine is doing the DMA transfer, not us. - avoid double-unmapping of the DMA buffers on MMCI data errors. - don't check for negative values from the dmaengine tx submission function - Dan says this must never fail. - use new dmaengine helper functions rather than using the ugly function pointers directly. - allow DMA code to be fully optimized away using dma_inprogress() which is defined to constant 0 if DMA engine support is disabled. - request maximum segment size from the DMA engine struct device and set this appropriately. - removed checking of buffer alignment - the DMA engine should deal with its own restrictions on buffer alignment, not the individual DMA engine users. - removed setting DMAREQCTL - this confuses some DMA controllers as it causes LBREQ to be asserted for the last seven transfers, rather than six SREQ and one LSREQ. - removed burst setting - the DMA controller should not burst past the transfer size required to complete the DMA operation. Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-04ARM: mmci: no need for separate host->data_xferedRussell King1-2/+0
We don't need to store the number of bytes transferred in our host structure - we can store this directly in data->bytes_xfered. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-24ARM: 6632/3: mmci: stop using the blockend interruptsLinus Walleij1-4/+1
Implement a suggestion from Russell to drop the use of blockend interrupts altogether and instead rely on the data counter. Tested with error-free cards on U300, U8500 and RealView PB1176. Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-11-10ARM: 6399/3: mmci: handle broken MCI_DATABLOCKEND hardwareLinus Walleij1-0/+3
On the U300 the MCI_DATAEND and MCI_DATABLOCKEND IRQs can arrive out-of-order. Replace an ugly #ifdef hack with a proper runtime solution which models what is really happening. In the U300 DMA mode and on all Ux500 models, the MCI_DATABLOCKEND flag isn't properly cleared in hardware following and ACK leading to all kind of weird behaviour when the flag is still up in subsequent interrupts, so we add two flags indicating the error and handle this runtime. Cc: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-11-10ARM: 6311/2: mmci: work with only one irqLinus Walleij1-0/+6
The DBx500 variants have only one IRQ line hooked up. Allow these (and any other implementations which choose to use only one irq) to work by directing the PIO interrupts also to the first IRQ line. Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-11ARM: 6437/2: mmci: add some register defines for ST Micro variantsLinus Walleij1-4/+10
This adds a few registers to the MMCI/PL180 derivates that is used for some odd control stuff like SDIO. Signed-off-by: Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-23ARM: 6308/1: mmci: support card detection interruptsRabin Vincent1-0/+1
If an IRQ can be requested on the card detected GPIO, use it instead of polling. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-08-26ARM: 6310/1: mmci: support different FIFO sizesRabin Vincent1-7/+0
The Ux500 variant has a 32-word FIFO (TXFIFOEMPTY is asserted when it has 2 left) and TXFIFOHALFEMPTY is repurposed as TXFIFOBURSTWRITEABLE, with a burst being defined as 8-words. Likewise for RX. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-29ARM: 6245/1: mmci: enable hardware flow control on Ux500 variantsRabin Vincent1-2/+0
Although both the U300 and Ux500 use ST variants, the HWFCEN bits are at different positions, so use the variant_data to store the information. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-29ARM: 6244/1: mmci: add variant data and default MCICLOCK supportRabin Vincent1-0/+2
Add a variant_data structure to handle the differences between the various variants of this peripheral. Add a first quirk for a default MCICLOCK value, required on the Ux500 variant where the enable bit needs to be always set, since it controls access to some registers. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-27ARM: 6237/1: mmci: use sg_miter API to fix multi-page sg handlingRabin Vincent1-34/+1
The mmci driver's SG list iteration logic assumes that each SG entry spans only one page, and only maps and flushes one page of the sg. This is not a valid assumption. Fix it by converting the driver to the sg_miter API, which correctly handles sgs which span multiple pages. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-04-14ARM: 6032/1: ARM: MMCI: support 8bit mode on the ST Micro versionLinus Walleij1-2/+4
This adds support for an 8bit wide bus to the card (data lines MCIDAT0 through 7 exist) on the ST Micro version and alters the U300 platform to support this. Also add some ST_ prefix to the ST-specific registers. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-09-22ARM: 5721/1: MMCI enable the use of a regulatorLinus Walleij1-0/+1
This enables the use of a regulator to power the MMCI/PL180 PrimeCell. The OCR mask is calculated and voltage is set using the new MMC core functions for discovering voltage ranges in regulators. The platform translate_vdd function which basically controls the 4 lines out of the PL180 is disabled if you use a regulator instead. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-09-22ARM: 5720/1: Move MMCI header to amba include dirLinus Walleij1-1/+1
This moves the mmci platform data definition struct away from arch/arm/include/asm/mach/mmc.h into the more proper place among the other primecells in include/linux/amba/mmci.h and at the same time renames it to "mmci.h", and also the struct in this file confusingly named mmc_platform_data has been renamed mmci_platform_data for clarity. Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-07-09MMC: MMCI: use gpiolib for card detect/write protectRussell King1-0/+2
Use gpiolib where available (and when valid GPIOs are provided) for write protect/card detect status reporting. We fall back to the old 'status' method where gpiolib support is not available. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-02mmci: Add support for ST Micro derivateLinus Walleij1-0/+28
This patch adds support for the ST Microelectronics version of the PL180 PrimeCell. They use designer ID 0x80 and have a few alterations/bugfixes related to open drain and HW flow control. They also add some SDIO registers, I am unsure if these are in ST HW only or if this is things also added in later ARM revisions, but they are included in the mmci.h file for completeness. Signed-off-by: Linus Walleij <linus.walleij@ericsson.com> Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2007-10-23mmc: fix sg->page falloutEmil Medve1-1/+1
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
2007-07-26mmc: update header file pathsPierre Ossman1-1/+1
Make sure all headers in the files reflect their true position in the tree. Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2007-05-01mmc: Move host and card drivers to subdirsPierre Ossman1-0/+179
Clean up the drivers/mmc directory by moving card and host drivers into subdirectories. Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>