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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2014-09-25clk: Remove .owner field for driverKiran Padwal15-15/+0
2014-09-25Merge branch 'clk-next-rockchip' into clk-nextMike Turquette1-36/+56
2014-09-25clk: rockchip: add clock node in PD_VIDEOKever Yang1-0/+20
2014-09-26Merge tag 'at91-soc2' of git://github.com/at91linux/linux-at91 into next/socArnd Bergmann4-0/+135
2014-09-25clk: rockchip: use the clock id for nodes initKever Yang1-34/+34
2014-09-25clk: rockchip: add missing rk3288 npll rate tableHeiko Stübner1-1/+1
2014-09-25clk: rockchip: rk3288: fix softreset register countMark yao1-1/+1
2014-09-24clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiationThomas Abraham1-4/+3
2014-09-22clk: qcom: Add support for banked MD RCGsStephen Boyd3-56/+77
2014-09-22clk: qcom: Add support for setting rates on PLLsStephen Boyd2-1/+87
2014-09-22clk: qcom: Consolidate frequency finding logicStephen Boyd4-32/+27
2014-09-22clk: qcom: Add IPQ8064 PLL required for USBAndy Gross1-1/+30
2014-09-22clk: samsung: exynos4: fix g3d clocksMarek Szyprowski1-4/+2
2014-09-22clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocksMarek Szyprowski1-2/+2
2014-09-22clk: samsung: exynos4: add missing smmu_g2d clock and update commentsMarek Szyprowski1-0/+1
2014-09-22clk: samsung: exynos3250: Register DMC clk providerKrzysztof Kozlowski1-0/+195
2014-09-22clk: samsung: exynos5260: fix typo in clock nameChander Kashyap1-1/+1
2014-09-22clk: samsung: exynos3250: fix width field of mout_mmc0/1Pankaj Dubey1-2/+2
2014-09-22clk: samsung: exynos3250: fix width and shift of div_spi0_isp clockPankaj Dubey1-1/+1
2014-09-22clk: samsung: exynos3250: fix mout_cam_blk parent listPankaj Dubey1-0/+1
2014-09-22clk: at91: add a driver for the h32mx clockAlexandre Belloni4-0/+135
2014-09-18clk: tegra: Make clock initialization more robustTomeu Vizoso1-2/+7
2014-09-18clk: tegra124: Add PLL_M_UD and PLL_C_UD clocksMikko Perttunen1-0/+8
2014-09-17Merge branch 'clk-fixes' into clk-nextMike Turquette7-10/+24
2014-09-16clk: mvebu: fix sscg node lookupThomas Petazzoni2-5/+5
2014-09-13clk: sunxi: add correct divider table for sun4i-apb0 clockChen-Yu Tsai1-0/+9
2014-09-10Merge branch 'clk-next-debugfs-lock' into clk-nextMike Turquette1-46/+27
2014-09-10clk: Don't hold prepare_lock across debugfs creationStephen Boyd1-46/+27
2014-09-10clk: rockchip: also protect hclk_peri as criticalHeiko Stübner2-0/+2
2014-09-10clk: fractional-divider: cast parent_rate to u64 before multiplyingHeiko Stübner1-1/+1
2014-09-09clk: Add driver for Maxim 77802 PMIC clocksJavier Martinez Canillas3-0/+106
2014-09-09clk: max77686: Convert to the generic max clock driverJavier Martinez Canillas2-168/+9
2014-09-09clk: Add generic driver for Maxim PMIC clocksJavier Martinez Canillas4-0/+228
2014-09-09clk: max77686: Add DT include for MAX77686 PMIC clockJavier Martinez Canillas1-6/+1
2014-09-09clk/efm32gg: fix dt init prototypeUwe Kleine-König1-3/+3
2014-09-09clk: zynq: Move const initdata into correct code sectionSoren Brinkmann1-15/+14
2014-09-09clk: zynq: Remove pointless return at end of void functionSoren Brinkmann1-1/+0
2014-09-09clk: zynq: Remove unnecessary OOM messageSoren Brinkmann1-3/+1
2014-09-09clk: mvebu: armada-375: Fix the description of the SAR in the commentGregory CLEMENT1-2/+2
2014-09-09clk: mvebu: armada-370: Fix timer drift caused by the SSCG deviationGregory CLEMENT1-0/+8
2014-09-09clk: mvebu: Fix clk frequency value if SSCG is enabledGregory CLEMENT2-0/+89
2014-09-03clk: prevent erronous parsing of children during rate changeTero Kristo1-1/+6
2014-09-03clk: rockchip: Fix the clocks for i2c1 and i2c2Doug Anderson1-2/+2
2014-09-03Merge branch 'for-v3.17-rc/ti-clk-driver' of github.com:t-kristo/linux-pm int...Mike Turquette2-2/+11
2014-09-02clk: qcom: Fix sdc 144kHz frequency entryStephen Boyd1-1/+1
2014-09-02clk: at91: fix div by zero in USB clock driverBoris BREZILLON1-2/+5
2014-09-02clk: at91: rework rm9200 USB clock to propagate set_rate to the parent clkBoris BREZILLON1-3/+10
2014-09-02clk: at91: fix recalc_rate implementation of PLL driverBoris BREZILLON1-8/+3
2014-09-02clk: at91: rework PLL rate calculationBoris BREZILLON1-70/+77
2014-09-02clk: at91: fix PLL_MAX_COUNT macro definitionBoris BREZILLON1-1/+1