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path: root/drivers/clk/bcm
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2015-12-24Merge branch 'clk-bcm2835' into clk-nextMichael Turquette1-54/+101
2015-12-24clk: bcm2835: Add PWM clock supportRemi Pommarel1-0/+13
Register the pwm clock for bcm2835. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24clk: bcm2835: Support for clock parent selectionRemi Pommarel1-45/+77
Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple parent clocks. These clocks divide the rate of a parent which can be selected by setting the proper bits in the clock control register. Previously all these parents where handled by a mux clock. But a mux clock cannot be used because updating clock control register to select parent needs a password to be xor'd with the parent index. This patch get rid of mux clock and make these clocks handle their own parent, allowing them to select the one to use. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24clk: bcm2835: add a round up ability to the clock divisorRemi Pommarel1-10/+12
Make bcm2835_clock_choose_div to optionally round up the chosen MASH divisor so that the resulting average rate will not be higher than the requested one. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-22Merge branch 'clk-bcm2835' into clk-nextMichael Turquette2-0/+86
2015-12-22clk: bcm2835: Add a driver for the auxiliary peripheral clock gates.Eric Anholt2-0/+86
There are a pair of SPI masters and a mini UART that were last minute additions. As a result, they didn't get integrated in the same way as the other gates off of the VPU clock in CPRMAN. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-11-20clk: bcm: Add BCM63138 clock supportFlorian Fainelli3-0/+33
BCM63138 has a simple clocking domain which is primarily the ARMPLL clocking complex, from which the ARM (CPU), APB and AXI clocks would be derived from. Since the ARMPLL controller is entirely compatible with the iProc ARM PLL, we just initialize it without additional parameters. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21Merge branch 'clk-iproc' into clk-nextStephen Boyd7-157/+637
* clk-iproc: clk: iproc: define Broadcom NS2 iProc clock binding clk: iproc: define Broadcom NSP iProc clock binding clk: ns2: add clock support for Broadcom Northstar 2 SoC clk: iproc: Separate status and control variables clk: iproc: Split off dig_filter clk: iproc: Add PLL base write function clk: nsp: add clock support for Broadcom Northstar Plus SoC clk: iproc: Add PWRCTRL support clk: cygnus: Convert all macros to all caps ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
2015-10-21clk: ns2: add clock support for Broadcom Northstar 2 SoCJon Mason2-0/+289
The Broadcom Northstar 2 SoC is architected under the iProc architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, LCPLL DDR, LCPLL Ports, all derived from an onboard crystal. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21clk: iproc: Separate status and control variablesJon Mason2-40/+62
Some PLLs have separate registers for Status and Control. The means the pll_base needs to be split into 2 new variables, so that those PLLs can specify device tree registers for those independently. Also, add a new driver flag to identify this presence of the split, and let the driver know that additional registers need to be used. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21clk: iproc: Split off dig_filterJon Mason4-17/+38
The PLL loop filter/gain can be located in a separate register on some SoCs. Split these off into a separate variable, so that an offset can be added if necessary. Also, make the necessary modifications to the Cygnus and NSP drivers for this change. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21clk: iproc: Add PLL base write functionJon Mason1-47/+33
All writes to the PLL base address must be flushed if the IPROC_CLK_NEEDS_READ_BACK flag is set. If we add a function to make the necessary write and reads, we can make sure that any future code which makes PLL base writes will do the correct thing. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21clk: nsp: add clock support for Broadcom Northstar Plus SoCJon Mason2-0/+137
The Broadcom Northstar Plus SoC is architected under the iProc architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all derived from an onboard crystal. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21clk: iproc: Add PWRCTRL supportJon Mason2-17/+44
Some iProc SoC clocks use a different way to control clock power, via the PWRDWN bit in the PLL control register. Since the PLL control register is used to access the PWRDWN bit, there is no need for the pwr_base when this is being used. A new flag, IPROC_CLK_EMBED_PWRCTRL, has been added to identify this usage. We can use the AON interface to write the values to enable/disable PWRDOWN. Signed-off-by: Jon Mason <jonmason@broadcom.com> [sboyd@codeaurora.org: Remove useless parentheses] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21clk: cygnus: Convert all macros to all capsJon Mason1-73/+73
The macros that are being used to initialize the values of the clk structures should be all caps. Find and replace all of them with their relevant counterparts. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabledArnd Bergmann1-3/+1
When CONFIG_CYGNUS is set but CONFIG_COMMON_CLK_IPROC is disabled, the following link failures are caused: drivers/built-in.o: In function `cygnus_armpll_init': :(.init.text+0x1d290): undefined reference to `iproc_armpll_setup' drivers/built-in.o: In function `cygnus_genpll_clk_init': :(.init.text+0x1d2c4): undefined reference to `iproc_pll_clk_setup' drivers/built-in.o: In function `cygnus_lcpll0_clk_init': :(.init.text+0x1d304): undefined reference to `iproc_pll_clk_setup' drivers/built-in.o: In function `cygnus_mipipll_clk_init': :(.init.text+0x1d344): undefined reference to `iproc_pll_clk_setup' drivers/built-in.o: In function `cygnus_asiu_init': :(.init.text+0x1d370): undefined reference to `iproc_asiu_setup' It is fixed it by always selecting COMMON_CLK_IPROC from ARCH_BCM_IPROC, and making COMMON_CLK_IPROC a silent option (thus preventing it from being erroneously disabled by a user). Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21clk: iproc: Fix PLL output frequency calculationSimran Rai1-8/+5
This patch affects the clocks that use fractional ndivider in their PLL output frequency calculation. Instead of 2^20 divide factor, the clock's ndiv integer shift was used. Fixed the bug by replacing ndiv integer shift with 2^20 factor. Signed-off-by: Simran Rai <ssimran@broadcom.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") Cc: <stable@vger.kernel.org> # v4.1+ Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-10-16clk: Allow drivers to build if COMPILE_TEST is enabledJavier Martinez Canillas1-2/+2
These drivers only have runtime but no build time dependencies so can be built for testing purposes if the Kconfig COMPILE_TEST option is enabled. This is useful to have more build coverage and make sure that drivers are not affected by changes that could cause build regressions. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Acked-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-12clk: bcm2835: Add support for programming the audio domain clocksEric Anholt1-1/+1521
This adds support for enabling, disabling, and setting the rate of the audio domain clocks. It will be necessary for setting the pixel clock for HDMI in the VC4 driver and let us write a cpufreq driver. It will also improve compatibility with user changes to the firmware's config.txt, since our previous fixed clocks are unaware of it. The firmware also has support for configuring the clocks through the mailbox channel, but the pixel clock setup by the firmware doesn't work, and it's Raspberry Pi specific anyway. The only conflicts we should have with the firmware would be if we made firmware calls that result in clock management (like opening firmware V3D or ISP access, which we don't support in upstream), or on hardware over-thermal or under-voltage (when the firmware would rewrite PLLB to take the ARM out of overclock). If that happens, our cached .recalc_rate() results would be incorrect, but that's no worse than our current state where we used fixed clocks. The existing fixed clocks in the code are left in place to provide backwards compatibility with old device tree files. Signed-off-by: Eric Anholt <eric@anholt.net> Tested-by: Martin Sperl <kernel@martin.sperl.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-01clk: bcm2835: Move under bcm/ with other Broadcom SoC clk drivers.Eric Anholt2-0/+56
clk-bcm2835.c predates the drivers under bcm/, but all the new BCM drivers are going in there so let's follow them. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: bcm: Convert to clk_hw based provider APIsStephen Boyd1-10/+10
We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd1-0/+1
* cleanup-clk-h-includes: (62 commits) clk: Remove clk.h from clk-provider.h clk: h8300: Remove clk.h and clkdev.h includes clk: at91: Include clk.h and slab.h clk: ti: Switch clk-provider.h include to clk.h clk: pistachio: Include clk.h clk: ingenic: Include clk.h clk: si570: Include clk.h clk: moxart: Include clk.h clk: cdce925: Include clk.h clk: Include clk.h in clk.c clk: zynq: Include clk.h clk: ti: Include clk.h clk: sunxi: Include clk.h and remove unused clkdev.h includes clk: st: Include clk.h clk: qcom: Include clk.h clk: highbank: Include clk.h clk: bcm: Include clk.h clk: versatile: Remove clk.h and clkdev.h includes clk: ux500: Remove clk.h and clkdev.h includes clk: tegra: Properly include clk.h ...
2015-07-28Merge branch 'clk-determine-rate-struct' into clk-nextStephen Boyd1-13/+21
* clk-determine-rate-struct: clk: fix some determine_rate implementations clk: change clk_ops' ->determine_rate() prototype
2015-07-27clk: change clk_ops' ->determine_rate() prototypeBoris Brezillon1-13/+21
Clock rates are stored in an unsigned long field, but ->determine_rate() (which returns a rounded rate from a requested one) returns a long value (errors are reported using negative error codes), which can lead to long overflow if the clock rate exceed 2Ghz. Change ->determine_rate() prototype to return 0 or an error code, and pass a pointer to a clk_rate_request structure containing the expected target rate and the rate constraints imposed by clk users. The clk_rate_request structure might be extended in the future to contain other kind of constraints like the rounding policy, the maximum clock inaccuracy or other things that are not yet supported by the CCF (power consumption constraints ?). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Jonathan Corbet <corbet@lwn.net> CC: Tony Lindgren <tony@atomide.com> CC: Ralf Baechle <ralf@linux-mips.org> CC: "Emilio López" <emilio@elopez.com.ar> CC: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Tero Kristo <t-kristo@ti.com> CC: Peter De Schrijver <pdeschrijver@nvidia.com> CC: Prashant Gaikwad <pgaikwad@nvidia.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Thierry Reding <thierry.reding@gmail.com> CC: Alexandre Courbot <gnurou@gmail.com> CC: linux-doc@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-omap@vger.kernel.org CC: linux-mips@linux-mips.org CC: linux-tegra@vger.kernel.org [sboyd@codeaurora.org: Fix parent dereference problem in __clk_determine_rate()] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> [sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate clocks without parents or a rate determining op] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20clk: bcm: Include clk.hStephen Boyd1-0/+1
This clock provider uses the consumer API, so include clk.h explicitly. Acked-by: Alex Elder <elder@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-02clk: iproc: fix bit manipulation arithmeticRay Jui1-2/+3
A 32-bit variable should be type casted to 64-bit before arithmetic operation and assigning it to a 64-bit variable Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-02clk: iproc: fix memory leak from clock nameRay Jui2-12/+2
of_property_read_string_index takes array of pointers and assign them to strings read from device tree property. No additional memory allocation is needed prior to calling of_property_read_string_index. In fact, since the array of pointers will be re-assigned to other strings, any memory that it points to prior to calling of_property_read_string_index will be leaked Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-18clk: cygnus: add clock support for Broadcom CygnusRay Jui2-0/+266
The Broadcom Cygnus SoC is architected under the iProc architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, MIPIPLL, all dervied from an onboard crystal. Cygnus also has various ASIU clocks that are derived directly from the onboard crystal. Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-06-18clk: iproc: add initial common clock supportRay Jui6-0/+1462
This adds basic and generic support for various iProc PLLs and clocks including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks. SoCs under the iProc architecture can define their specific register offsets and clock parameters for their PLL and clock controllers. These parameters can be passed as arugments into the generic iProc PLL and clock setup functions Derived from code originally provided by Jonathan Richardson <jonathar@broadcom.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-05-14clk: bcm/kona: Remove ccu_listStephen Boyd2-6/+0
This list doesn't look to be used. Let's remove it and any associated code that would be manipulating this list. This also silences this error: drivers/clk/bcm/clk-kona-setup.c:24:1: warning: symbol 'ccu_list' was not declared. Should it be static? Reviewed-by: Alex Elder <elder@linaro.org> Cc: Tim Kryger <tim.kryger@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-14clk: bcm/kona: Silence sparse warningsStephen Boyd1-1/+1
drivers/clk/bcm/clk-kona.c:1243:16: warning: odd constant _Bool cast (ffffffffffffffea becomes 1) Reviewed-by: Alex Elder <elder@linaro.org> Cc: Tim Kryger <tim.kryger@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-17clk: bcm/kona: use DIV_ROUND_CLOSEST_ULL()Javi Merino2-22/+7
Now that the kernel provides DIV_ROUND_CLOSEST_ULL(), drop the internal implementation and use the kernel one. Signed-off-by: Javi Merino <javi.merino@arm.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Alex Elder <elder@linaro.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2015-02-02clk: Add rate constraints to clocksTomeu Vizoso1-0/+2
Adds a way for clock consumers to set maximum and minimum rates. This can be used for thermal drivers to set minimum rates, or by misc. drivers to set maximum rates to assure a minimum performance level. Changes the signature of the determine_rate callback by adding the parameters min_rate and max_rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [sboyd@codeaurora.org: set req_rate in __clk_init] Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate migrated clk-private.h changes to clk.c]
2014-12-03clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso1-2/+2
This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-05-27clk: bcm/kona: implement determine_rate()Alex Elder1-1/+53
Implement the clk->determine_rate method for Broadcom Kona peripheral clocks. This allows a peripheral clock to be re-parented in order to satisfy a rate change request. This takes the place of the previous kona_peri_clk_round_rate() functionality, though that function remains because it is used by the new one. The parent clock that allows the peripheral clock to produce a rate closest to the one requested is the one selected, though the current parent is used by default. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-04-30clk: bcm21664: use common clock frameworkAlex Elder3-1/+292
Define the set of CCUs and provided clocks sufficient to satisfy the needs of all the existing clock references for BCM21664. Replace the "fake" fixed-rate clocks used previously with "real" ones. Note that only the minimal set of these clocks and CCUs is defined here. More clock definitions will need to be added as required by the addition of additional drivers. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-04-30clk: bcm281xx: move compatible string definitionsAlex Elder1-12/+0
The Broadcom 281xx clock code uses a #define for the compatible string for it's clock control units (CCUs). Rather than defining those in the C source file, define them in the header file that's shared by both the code and the device tree source file (along with all the clock ids). Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-04-30clk: bcm281xx: add clock hysteresis supportAlex Elder3-0/+82
Add support for clock gate hysteresis control. For now, if it's defined for a clock, it's enabled. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-04-30clk: bcm281xx: add clock policy supportAlex Elder3-0/+318
Add support for CCU policy engine control, and also for setting the mask bits for bus clocks that require a policy change to get activated. This includes adding validity checking framework for CCUs, to validate the policy fields if defined. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-04-30clk: bcm281xx: define CCU clock data staticallyAlex Elder3-143/+133
Rather than "manually" setting up each CCU's clock entries at run time, define a flexible array of generic Kona clock structures within the CCU structure itself. Each of these entries contains generic kona clock information (like its CCU pointer and clock framework initialization data). Each also has a pointer to a structure contianing clock type-dependent initialization data (like register definitions). Since we'll iterate over these arrays we need to be sure they have slots for all potential clock index values. (E.g. for the root CCU we must have at least BCM281XX_ROOT_CCU_CLOCK_COUNT slots.) To ensure this we always define an extra entry and fill it using the special initializer LAST_KONA_CLK. Just about everything we need to know about a clock can be defined statically. As a result, kona_clk_setup() can be changed to take just a kona_clk structure as its argument, and peri_clk_setup() can be simplified. With the information pre-defined we are also able to handle most clock setup genericially. We can do away with the CCU-specific callback functions that previously were needed to set up the entries in CCU's clock array. Move the definition of the ccu_data structure down in "clk-kona.h" to avoid a forward dependency. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-04-30clk: bcm281xx: initialize CCU structures staticallyAlex Elder4-119/+97
We know up front how many CCU's we'll support, so there's no need to allocate their data structures dynamically. Define a macro KONA_CCU_COMMON() to simplify the initialization of many of the fields in a ccu_data structure. Pass the address of a statically defined CCU structure to kona_dt_ccu_setup() rather than having that function allocate one. We also know at build time how many clocks a given CCU will provide, though the number of of them for each CCU is different. Record the number of clocks we need in the CCU's clk_onecell_data struct (which is used when we register the CCU with the common clock code as a clock provider). Rename that struct field "clk_data" (because "data" alone gets a little confusing). Use the known clock count to move the allocation of each CCU's clocks array into ccu_clks_setup() rather than having each CCU's setup callback function do it. (The real motivation behind all of this is that we'll be doing some static initialization of some additional CCU-specific data soon.) Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-04-30clk: bcm281xx: change some symbol namesAlex Elder1-11/+16
As I developed the bcm281xx clock code I understood there were restrictions on device tree "compatible" strings names, and as a result "bcm11351" was used in places despite the part family being more properly called "bcm281xx". This can be a little confusing. In some cases I went to far and things using "bcm11351" when that was not necessary. This patch remedies this. It renames the symbol used to define the "compatible" string (but not its value) so it uses "BCM281XX". Similarly, the name names provided to the CLK_OF_DECLARE() macro are changed, hoping to minimize the number of places that the confusing "11351" string is used. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-04-30clk: bcm281xx: use init_data.name for clock nameAlex Elder3-12/+14
Use the init_data.name field to hold the name of a Kona clock rather than duplicating it. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-04-30clk: bcm281xx: warn if ccu_wait_bit() failsAlex Elder1-0/+3
Don't let a failure of ccu_wait_bit() go unnoticed. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-04-30clk: bcm281xx: don't use unnamed structs or unionsAlex Elder3-61/+64
The Broadcom Kona clock code, as originally written, made use of unnamed union and struct fields. This is a feature present in C11, and is a GNU extension otherwise. It worked very well for me. Unfortunately, Russell King reported that this feature was not supported in a build environment he used, which meant attempting to build this code failed spectacularly. Add names to these unnamed fields, and update the code accordingly. Reported-by: Russell King <linux@arm.linux.org.uk> Tested-by: Markus Mayer <markus.mayer@linaro.org> Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-24clk: bcm281xx: don't disable unused peripheral clocksAlex Elder1-1/+1
Add the CLK_IGNORE_UNUSED flag when setting up a peripheral clock. This prevents unused clocks from getting disabled, and by doing this we can use the common clock code even before we've resolved all the spots that need to get a reference to their clock. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-24clk: bcm281xx: add initial clock framework supportAlex Elder6-0/+2640
Add code for device tree support of clocks in the BCM281xx family of SoCs. Machines in this family use peripheral clocks implemented by "Kona" clock control units (CCUs). (Other Broadcom SoC families use Kona style CCUs as well, but support for them is not yet upstream.) A BCM281xx SoC has multiple CCUs, each of which manages a set of clocks on the SoC. A Kona peripheral clock is composite clock that may include a gate, a parent clock multiplexor, and zero, one or two dividers. There is a variety of gate types, and many gates implement hardware-managed gating (often called "auto-gating"). Most dividers divide their input clock signal by an integer value (one or more). There are also "fractional" dividers which allow division by non-integer values. To accomodate such dividers, clock rates and dividers are generally maintained by the code in "scaled" form, which allows integer and fractional dividers to be handled in a uniform way. If present, the gate for a Kona peripheral clock must be enabled when a change is made to its multiplexor or one of its dividers. Additionally, dividers and multiplexors have trigger registers which must be used whenever the divider value or selected parent clock is changed. The same trigger is often used for a divider and multiplexor, and a BCM281xx peripheral clock occasionally has two triggers. The gate, dividers, and parent clock selector are treated in this code as "components" of a peripheral clock. Their functionality is implemented directly--e.g. the common clock framework gate implementation is not used for a Kona peripheral clock gate. (This has being considered though, and the intention is to evolve this code to leverage common code as much as possible.) The source code is divided into three general portions: drivers/clk/bcm/clk-kona.h drivers/clk/bcm/clk-kona.c These implement the basic Kona clock functionality, including the clk_ops methods and various routines to manipulate registers and interpret their values. This includes some functions used to set clocks to a desired initial state (though this feature is only partially implemented here). drivers/clk/bcm/clk-kona-setup.c This contains generic run-time initialization code for data structures representing Kona CCUs and clocks. This encapsulates the clock structure initialization that can't be done statically. Note that there is a great deal of validity-checking code here, making explicit certain assumptions in the code. This is mostly useful for adding new clock definitions and could possibly be disabled for production use. drivers/clk/bcm/clk-bcm281xx.c This file defines the specific CCUs used by BCM281XX family SoCs, as well as the specific clocks implemented by each. It declares a device tree clock match entry for each CCU defined. include/dt-bindings/clock/bcm281xx.h This file defines the selector (index) values used to identify a particular clock provided by a CCU. It consists entirely of C preprocessor constants, to be used by both the C source and device tree source files. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
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