drm-misc - Kernel DRM miscellaneous fixes and cross-tree changes

Age	Commit message (Collapse)	Author	Files	Lines
2012-08-31	MIPS: OCTEON: Update register definitions.	David Daney	1	-1/+1742
	Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2011-12-07	MIPS: Octeon: Update SOC PCI related register definitions for new chips.	David Daney	1	-2/+2
	Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2986/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29	MIPS: Octeon: Update register definitions for CN63XX chips	David Daney	1	-381/+300
	The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores. Join some lines back together. This makes some of them exceed 80 columns, but they are uninteresting and this unclutters things. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1668/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17	MIPS: Add register definitions for PCI.	David Daney	1	-0/+2560
	Here we add the register definitions for the processor blocks used by the following PCI support patch. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>