summaryrefslogtreecommitdiff
path: root/arch/arm/mm/context.c
AgeCommit message (Expand)AuthorFilesLines
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
2015-12-02ARM: 8465/1: mm: keep reserved ASIDs in sync with mm after multiple rolloversWill Deacon1-12/+26
2015-02-03ARM: 8299/1: mm: ensure local active ASID is marked as allocated on rolloverWill Deacon1-15/+11
2014-11-21ARM: 8203/1: mm: try to re-use old ASID assignments following a rolloverWill Deacon1-24/+34
2013-12-29ARM: 7926/1: mm: flesh out and fix the comments in the ASID allocatorWill Deacon1-6/+10
2013-12-29ARM: 7925/1: mm: keep track of last ASID allocation to improve bitmap searchingWill Deacon1-1/+3
2013-12-29ARM: 7924/1: mm: don't bother with reserved ttbr0 when running with LPAEWill Deacon1-10/+11
2013-08-12ARM: tlb: don't perform inner-shareable invalidation for local TLB opsWill Deacon1-6/+1
2013-07-26ARM: 7789/1: Do not run dummy_flush_tlb_a15_erratum() on non-Cortex-A15Fabio Estevam1-1/+2
2013-06-29Merge branch 'devel-stable' into for-nextRussell King1-7/+2
2013-06-24ARM: 7769/1: Cortex-A15: fix erratum 798181 implementationMarc Zyngier1-1/+28
2013-06-24ARM: 7768/1: prevent risks of out-of-bound access in ASID allocatorMarc Zyngier1-9/+8
2013-06-24ARM: 7767/1: let the ASID allocator handle suspended animationMarc Zyngier1-0/+9
2013-05-30ARM: LPAE: use 64-bit accessors for TTBR registersCyril Chemparathy1-7/+2
2013-04-03ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB opera...Catalin Marinas1-1/+2
2013-03-03ARM: 7661/1: mm: perform explicit branch predictor maintenance when requiredWill Deacon1-1/+3
2013-03-03ARM: 7659/1: mm: make mm->context.id an atomic64_t variableWill Deacon1-8/+13
2013-03-03ARM: 7658/1: mm: fix race updating mm->context.id on ASID rolloverWill Deacon1-3/+3
2013-02-16ARM: 7649/1: mm: mm->context.id fix for big-endianBen Dooks1-0/+3
2012-11-26ARM: 7582/2: rename kvm_seq to vmalloc_seq so to avoid confusion with KVMNicolas Pitre1-2/+2
2012-11-05ARM: mm: use bitmap operations when allocating new ASIDsWill Deacon1-19/+35
2012-11-05ARM: mm: avoid taking ASID spinlock on fastpathWill Deacon1-8/+15
2012-11-05ARM: mm: remove IPI broadcasting on ASID rolloverWill Deacon1-100/+86
2012-08-25ARM: 7502/1: contextidr: avoid using bfi instruction during notifierWill Deacon1-3/+4
2012-07-09ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current processWill Deacon1-0/+35
2012-04-17ARM: Remove current_mm per-cpu variableCatalin Marinas1-11/+1
2012-04-17ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUsCatalin Marinas1-2/+2
2012-04-17ARM: Use TTBR1 instead of reserved context IDWill Deacon1-18/+27
2011-12-08ARM: LPAE: Add context switching supportCatalin Marinas1-2/+17
2011-09-13locking, ARM: Annotate low level hw locks as rawThomas Gleixner1-7/+7
2011-06-09Revert "ARM: 6944/1: mm: allow ASID 0 to be allocated to tasks"Russell King1-3/+3
2011-06-09Revert "ARM: 6943/1: mm: use TTBR1 instead of reserved context ID"Russell King1-6/+5
2011-05-26ARM: 6944/1: mm: allow ASID 0 to be allocated to tasksWill Deacon1-3/+3
2011-05-26ARM: 6943/1: mm: use TTBR1 instead of reserved context IDWill Deacon1-5/+6
2010-02-15ARM: 5905/1: ARM: Global ASID allocation on SMPCatalin Marinas1-14/+110
2009-10-29ARM: Fix errata 411920 workaroundsRussell King1-4/+1
2009-09-24cpumask: use mm_cpumask() wrapper: armRusty Russell1-1/+1
2007-05-09Merge branches 'armv7', 'at91', 'misc' and 'omap' into develRussell King1-3/+7
2007-05-09[ARM] armv7: add support for asid-tagged VIVT I-cacheCatalin Marinas1-0/+7
2007-05-08[ARM] Fix ASID version switchRussell King1-3/+7
2007-02-08[ARM] 4128/1: Architecture compliant TTBR changing sequenceCatalin Marinas1-2/+10
2006-09-20[ARM] Move mmu.c out of the wayRussell King1-0/+45
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 09:48:52 +0000